diff --git a/src/target/riscv/debug_defines.c b/src/target/riscv/debug_defines.c index da20e19c7..d514c6e03 100644 --- a/src/target/riscv/debug_defines.c +++ b/src/target/riscv/debug_defines.c @@ -1,6 +1,6 @@ /* * This file is auto-generated by running 'make debug_defines' in - * https://github.com/riscv/riscv-debug-spec/ (f546ddf) + * https://github.com/riscv/riscv-debug-spec/ (40b9a05) */ #include "debug_defines.h" @@ -63,15 +63,15 @@ static riscv_debug_reg_field_list_t dtm_idcode_get_1(riscv_debug_reg_ctx_t conte } static const char *dtm_dtmcs_errinfo_values[8] = { - [0] = "not implemented", - [1] = "dmi error", - [2] = "communication error", - [3] = "device error", + [0] = "not_implemented", + [1] = "dmi_error", + [2] = "communication_error", + [3] = "device_error", [4] = "unknown" }; static const char *dtm_dtmcs_version_values[16] = { - [0] = "0.11", - [1] = "1.0", + [0] = "0_11", + [1] = "1_0", [15] = "custom" }; static riscv_debug_reg_field_list_t dtm_dtmcs_get_abits(riscv_debug_reg_ctx_t context) @@ -219,32 +219,32 @@ static riscv_debug_reg_field_list_t dtm_dmi_get_op(riscv_debug_reg_ctx_t context static const char *csr_dcsr_debugver_values[16] = { [0] = "none", - [4] = "1.0", + [4] = "1_0", [15] = "custom" }; static const char *csr_dcsr_ebreakvs_values[2] = { [0] = "exception", - [1] = "debug mode" + [1] = "debug_mode" }; static const char *csr_dcsr_ebreakvu_values[2] = { [0] = "exception", - [1] = "debug mode" + [1] = "debug_mode" }; static const char *csr_dcsr_ebreakm_values[2] = { [0] = "exception", - [1] = "debug mode" + [1] = "debug_mode" }; static const char *csr_dcsr_ebreaks_values[2] = { [0] = "exception", - [1] = "debug mode" + [1] = "debug_mode" }; static const char *csr_dcsr_ebreaku_values[2] = { [0] = "exception", - [1] = "debug mode" + [1] = "debug_mode" }; static const char *csr_dcsr_stepie_values[2] = { - [0] = "interrupts disabled", - [1] = "interrupts enabled" + [0] = "interrupts_disabled", + [1] = "interrupts_enabled" }; static const char *csr_dcsr_stopcount_values[2] = { [0] = "normal", @@ -491,6 +491,36 @@ static riscv_debug_reg_field_list_t csr_dpc_get_dpc(riscv_debug_reg_ctx_t contex return result; } +static riscv_debug_reg_field_list_t csr_dscratch0_get_dscratch0(riscv_debug_reg_ctx_t context) +{ + assert(context.DXLEN.is_set); + riscv_debug_reg_field_list_t result = { + .field = { + .name = "dscratch0", + .lsb = 0, + .msb = (context.DXLEN.value + -1), + .values = NULL + }, + .get_next = NULL + }; + return result; +} + +static riscv_debug_reg_field_list_t csr_dscratch1_get_dscratch1(riscv_debug_reg_ctx_t context) +{ + assert(context.DXLEN.is_set); + riscv_debug_reg_field_list_t result = { + .field = { + .name = "dscratch1", + .lsb = 0, + .msb = (context.DXLEN.value + -1), + .values = NULL + }, + .get_next = NULL + }; + return result; +} + static riscv_debug_reg_field_list_t csr_tselect_get_index(riscv_debug_reg_ctx_t context) { assert(context.XLEN.is_set); @@ -660,12 +690,12 @@ static riscv_debug_reg_field_list_t csr_tcontrol_get_mte(riscv_debug_reg_ctx_t c return result; } -static riscv_debug_reg_field_list_t csr_hcontext_get_hcontext(riscv_debug_reg_ctx_t context) +static riscv_debug_reg_field_list_t csr_scontext_get_data(riscv_debug_reg_ctx_t context) { assert(context.XLEN.is_set); riscv_debug_reg_field_list_t result = { .field = { - .name = "hcontext", + .name = "data", .lsb = 0, .msb = (context.XLEN.value + -1), .values = NULL @@ -675,12 +705,12 @@ static riscv_debug_reg_field_list_t csr_hcontext_get_hcontext(riscv_debug_reg_ct return result; } -static riscv_debug_reg_field_list_t csr_scontext_get_data(riscv_debug_reg_ctx_t context) +static riscv_debug_reg_field_list_t csr_mcontext_get_hcontext(riscv_debug_reg_ctx_t context) { assert(context.XLEN.is_set); riscv_debug_reg_field_list_t result = { .field = { - .name = "data", + .name = "hcontext", .lsb = 0, .msb = (context.XLEN.value + -1), .values = NULL @@ -701,10 +731,10 @@ static const char *csr_mcontrol_timing_values[2] = { static const char *csr_mcontrol_sizelo_values[4] = {}; static const char *csr_mcontrol_action_values[16] = { [0] = "breakpoint", - [1] = "debug mode", - [2] = "trace on", - [3] = "trace off", - [4] = "trace notify", + [1] = "debug_mode", + [2] = "trace_on", + [3] = "trace_off", + [4] = "trace_notify", [8] = "external0", [9] = "external1" }; @@ -717,12 +747,12 @@ static const char *csr_mcontrol_match_values[16] = { [1] = "napot", [2] = "ge", [3] = "lt", - [4] = "mask low", - [5] = "mask high", - [8] = "not equal", - [9] = "not napot", - [12] = "not mask low", - [13] = "not mask high" + [4] = "mask_low", + [5] = "mask_high", + [8] = "not_equal", + [9] = "not_napot", + [12] = "not_mask_low", + [13] = "not_mask_high" }; static riscv_debug_reg_field_list_t csr_mcontrol_get_dmode(riscv_debug_reg_ctx_t context) { @@ -985,10 +1015,10 @@ static const char *csr_mcontrol6_size_values[8] = { }; static const char *csr_mcontrol6_action_values[16] = { [0] = "breakpoint", - [1] = "debug mode", - [2] = "trace on", - [3] = "trace off", - [4] = "trace notify", + [1] = "debug_mode", + [2] = "trace_on", + [3] = "trace_off", + [4] = "trace_notify", [8] = "external0", [9] = "external1" }; @@ -1001,12 +1031,12 @@ static const char *csr_mcontrol6_match_values[16] = { [1] = "napot", [2] = "ge", [3] = "lt", - [4] = "mask low", - [5] = "mask high", - [8] = "not equal", - [9] = "not napot", - [12] = "not mask low", - [13] = "not mask high" + [4] = "mask_low", + [5] = "mask_high", + [8] = "not_equal", + [9] = "not_napot", + [12] = "not_mask_low", + [13] = "not_mask_high" }; static const char *csr_mcontrol6_uncertainen_values[2] = { [0] = "disabled", @@ -1282,10 +1312,10 @@ static riscv_debug_reg_field_list_t csr_mcontrol6_get_load(riscv_debug_reg_ctx_t static const char *csr_icount_action_values[64] = { [0] = "breakpoint", - [1] = "debug mode", - [2] = "trace on", - [3] = "trace off", - [4] = "trace notify", + [1] = "debug_mode", + [2] = "trace_on", + [3] = "trace_off", + [4] = "trace_notify", [8] = "external0", [9] = "external1" }; @@ -1447,10 +1477,10 @@ static riscv_debug_reg_field_list_t csr_icount_get_action(riscv_debug_reg_ctx_t static const char *csr_itrigger_action_values[64] = { [0] = "breakpoint", - [1] = "debug mode", - [2] = "trace on", - [3] = "trace off", - [4] = "trace notify", + [1] = "debug_mode", + [2] = "trace_on", + [3] = "trace_off", + [4] = "trace_notify", [8] = "external0", [9] = "external1" }; @@ -1599,10 +1629,10 @@ static riscv_debug_reg_field_list_t csr_itrigger_get_action(riscv_debug_reg_ctx_ static const char *csr_etrigger_action_values[64] = { [0] = "breakpoint", - [1] = "debug mode", - [2] = "trace on", - [3] = "trace off", - [4] = "trace notify", + [1] = "debug_mode", + [2] = "trace_on", + [3] = "trace_off", + [4] = "trace_notify", [8] = "external0", [9] = "external1" }; @@ -1737,10 +1767,10 @@ static riscv_debug_reg_field_list_t csr_etrigger_get_action(riscv_debug_reg_ctx_ static const char *csr_tmexttrigger_action_values[64] = { [0] = "breakpoint", - [1] = "debug mode", - [2] = "trace on", - [3] = "trace off", - [4] = "trace notify", + [1] = "debug_mode", + [2] = "trace_on", + [3] = "trace_off", + [4] = "trace_notify", [8] = "external0", [9] = "external1" }; @@ -2002,9 +2032,9 @@ static const char *dm_dmstatus_confstrptrvalid_values[2] = { }; static const char *dm_dmstatus_version_values[16] = { [0] = "none", - [1] = "0.11", - [2] = "0.13", - [3] = "1.0", + [1] = "0_11", + [2] = "0_13", + [3] = "1_0", [15] = "custom" }; static riscv_debug_reg_field_list_t dm_dmstatus_get_allhalted(riscv_debug_reg_ctx_t context) @@ -2592,15 +2622,15 @@ static const char *dm_abstractcs_busy_values[2] = { [1] = "busy" }; static const char *dm_abstractcs_relaxedpriv_values[2] = { - [0] = "full checks", - [1] = "relaxed checks" + [0] = "full_checks", + [1] = "relaxed_checks" }; static const char *dm_abstractcs_cmderr_values[8] = { [0] = "none", [1] = "busy", - [2] = "not supported", + [2] = "not_supported", [3] = "exception", - [4] = "halt/resume", + [4] = "halt_resume", [5] = "bus", [6] = "reserved", [7] = "other" @@ -2979,7 +3009,7 @@ static riscv_debug_reg_field_list_t dm_haltsum3_get_haltsum3(riscv_debug_reg_ctx static const char *dm_sbcs_sbversion_values[8] = { [0] = "legacy", - [1] = "1.0" + [1] = "1_0" }; static const char *dm_sbcs_sbaccess_values[8] = { [0] = "8bit", @@ -3578,398 +3608,6 @@ static riscv_debug_reg_field_list_t virt_priv_get_prv(riscv_debug_reg_ctx_t cont return result; } -static riscv_debug_reg_field_list_t dmi_sercs_get_full3(riscv_debug_reg_ctx_t context) -{ - riscv_debug_reg_field_list_t result = { - .field = { - .name = "full3", - .lsb = 9, - .msb = 9, - .values = NULL - }, - .get_next = NULL - }; - return result; -} - -static riscv_debug_reg_field_list_t dmi_sercs_get_error2(riscv_debug_reg_ctx_t context) -{ - riscv_debug_reg_field_list_t result = { - .field = { - .name = "error2", - .lsb = 8, - .msb = 8, - .values = NULL - }, - .get_next = dmi_sercs_get_full3 - }; - return result; -} - -static riscv_debug_reg_field_list_t dmi_sercs_get_valid2(riscv_debug_reg_ctx_t context) -{ - riscv_debug_reg_field_list_t result = { - .field = { - .name = "valid2", - .lsb = 7, - .msb = 7, - .values = NULL - }, - .get_next = dmi_sercs_get_error2 - }; - return result; -} - -static riscv_debug_reg_field_list_t dmi_sercs_get_full2(riscv_debug_reg_ctx_t context) -{ - riscv_debug_reg_field_list_t result = { - .field = { - .name = "full2", - .lsb = 6, - .msb = 6, - .values = NULL - }, - .get_next = dmi_sercs_get_valid2 - }; - return result; -} - -static riscv_debug_reg_field_list_t dmi_sercs_get_error1(riscv_debug_reg_ctx_t context) -{ - riscv_debug_reg_field_list_t result = { - .field = { - .name = "error1", - .lsb = 5, - .msb = 5, - .values = NULL - }, - .get_next = dmi_sercs_get_full2 - }; - return result; -} - -static riscv_debug_reg_field_list_t dmi_sercs_get_valid1(riscv_debug_reg_ctx_t context) -{ - riscv_debug_reg_field_list_t result = { - .field = { - .name = "valid1", - .lsb = 4, - .msb = 4, - .values = NULL - }, - .get_next = dmi_sercs_get_error1 - }; - return result; -} - -static riscv_debug_reg_field_list_t dmi_sercs_get_full1(riscv_debug_reg_ctx_t context) -{ - riscv_debug_reg_field_list_t result = { - .field = { - .name = "full1", - .lsb = 3, - .msb = 3, - .values = NULL - }, - .get_next = dmi_sercs_get_valid1 - }; - return result; -} - -static riscv_debug_reg_field_list_t dmi_sercs_get_serialcount(riscv_debug_reg_ctx_t context) -{ - riscv_debug_reg_field_list_t result = { - .field = { - .name = "serialcount", - .lsb = 0x1c, - .msb = 0x1f, - .values = NULL - }, - .get_next = dmi_sercs_get_full1 - }; - return result; -} - -static riscv_debug_reg_field_list_t dmi_sercs_get_serial(riscv_debug_reg_ctx_t context) -{ - riscv_debug_reg_field_list_t result = { - .field = { - .name = "serial", - .lsb = 0x18, - .msb = 0x1a, - .values = NULL - }, - .get_next = dmi_sercs_get_serialcount - }; - return result; -} - -static riscv_debug_reg_field_list_t dmi_sercs_get_error7(riscv_debug_reg_ctx_t context) -{ - riscv_debug_reg_field_list_t result = { - .field = { - .name = "error7", - .lsb = 0x17, - .msb = 0x17, - .values = NULL - }, - .get_next = dmi_sercs_get_serial - }; - return result; -} - -static riscv_debug_reg_field_list_t dmi_sercs_get_valid7(riscv_debug_reg_ctx_t context) -{ - riscv_debug_reg_field_list_t result = { - .field = { - .name = "valid7", - .lsb = 0x16, - .msb = 0x16, - .values = NULL - }, - .get_next = dmi_sercs_get_error7 - }; - return result; -} - -static riscv_debug_reg_field_list_t dmi_sercs_get_full7(riscv_debug_reg_ctx_t context) -{ - riscv_debug_reg_field_list_t result = { - .field = { - .name = "full7", - .lsb = 0x15, - .msb = 0x15, - .values = NULL - }, - .get_next = dmi_sercs_get_valid7 - }; - return result; -} - -static riscv_debug_reg_field_list_t dmi_sercs_get_error6(riscv_debug_reg_ctx_t context) -{ - riscv_debug_reg_field_list_t result = { - .field = { - .name = "error6", - .lsb = 0x14, - .msb = 0x14, - .values = NULL - }, - .get_next = dmi_sercs_get_full7 - }; - return result; -} - -static riscv_debug_reg_field_list_t dmi_sercs_get_error0(riscv_debug_reg_ctx_t context) -{ - riscv_debug_reg_field_list_t result = { - .field = { - .name = "error0", - .lsb = 2, - .msb = 2, - .values = NULL - }, - .get_next = dmi_sercs_get_error6 - }; - return result; -} - -static riscv_debug_reg_field_list_t dmi_sercs_get_valid6(riscv_debug_reg_ctx_t context) -{ - riscv_debug_reg_field_list_t result = { - .field = { - .name = "valid6", - .lsb = 0x13, - .msb = 0x13, - .values = NULL - }, - .get_next = dmi_sercs_get_error0 - }; - return result; -} - -static riscv_debug_reg_field_list_t dmi_sercs_get_full6(riscv_debug_reg_ctx_t context) -{ - riscv_debug_reg_field_list_t result = { - .field = { - .name = "full6", - .lsb = 0x12, - .msb = 0x12, - .values = NULL - }, - .get_next = dmi_sercs_get_valid6 - }; - return result; -} - -static riscv_debug_reg_field_list_t dmi_sercs_get_error5(riscv_debug_reg_ctx_t context) -{ - riscv_debug_reg_field_list_t result = { - .field = { - .name = "error5", - .lsb = 0x11, - .msb = 0x11, - .values = NULL - }, - .get_next = dmi_sercs_get_full6 - }; - return result; -} - -static riscv_debug_reg_field_list_t dmi_sercs_get_valid5(riscv_debug_reg_ctx_t context) -{ - riscv_debug_reg_field_list_t result = { - .field = { - .name = "valid5", - .lsb = 0x10, - .msb = 0x10, - .values = NULL - }, - .get_next = dmi_sercs_get_error5 - }; - return result; -} - -static riscv_debug_reg_field_list_t dmi_sercs_get_full5(riscv_debug_reg_ctx_t context) -{ - riscv_debug_reg_field_list_t result = { - .field = { - .name = "full5", - .lsb = 0xf, - .msb = 0xf, - .values = NULL - }, - .get_next = dmi_sercs_get_valid5 - }; - return result; -} - -static riscv_debug_reg_field_list_t dmi_sercs_get_error4(riscv_debug_reg_ctx_t context) -{ - riscv_debug_reg_field_list_t result = { - .field = { - .name = "error4", - .lsb = 0xe, - .msb = 0xe, - .values = NULL - }, - .get_next = dmi_sercs_get_full5 - }; - return result; -} - -static riscv_debug_reg_field_list_t dmi_sercs_get_valid4(riscv_debug_reg_ctx_t context) -{ - riscv_debug_reg_field_list_t result = { - .field = { - .name = "valid4", - .lsb = 0xd, - .msb = 0xd, - .values = NULL - }, - .get_next = dmi_sercs_get_error4 - }; - return result; -} - -static riscv_debug_reg_field_list_t dmi_sercs_get_full4(riscv_debug_reg_ctx_t context) -{ - riscv_debug_reg_field_list_t result = { - .field = { - .name = "full4", - .lsb = 0xc, - .msb = 0xc, - .values = NULL - }, - .get_next = dmi_sercs_get_valid4 - }; - return result; -} - -static riscv_debug_reg_field_list_t dmi_sercs_get_error3(riscv_debug_reg_ctx_t context) -{ - riscv_debug_reg_field_list_t result = { - .field = { - .name = "error3", - .lsb = 0xb, - .msb = 0xb, - .values = NULL - }, - .get_next = dmi_sercs_get_full4 - }; - return result; -} - -static riscv_debug_reg_field_list_t dmi_sercs_get_valid3(riscv_debug_reg_ctx_t context) -{ - riscv_debug_reg_field_list_t result = { - .field = { - .name = "valid3", - .lsb = 0xa, - .msb = 0xa, - .values = NULL - }, - .get_next = dmi_sercs_get_error3 - }; - return result; -} - -static riscv_debug_reg_field_list_t dmi_sercs_get_valid0(riscv_debug_reg_ctx_t context) -{ - riscv_debug_reg_field_list_t result = { - .field = { - .name = "valid0", - .lsb = 1, - .msb = 1, - .values = NULL - }, - .get_next = dmi_sercs_get_valid3 - }; - return result; -} - -static riscv_debug_reg_field_list_t dmi_sercs_get_full0(riscv_debug_reg_ctx_t context) -{ - riscv_debug_reg_field_list_t result = { - .field = { - .name = "full0", - .lsb = 0, - .msb = 0, - .values = NULL - }, - .get_next = dmi_sercs_get_valid0 - }; - return result; -} - -static riscv_debug_reg_field_list_t dmi_sertx_get_data(riscv_debug_reg_ctx_t context) -{ - riscv_debug_reg_field_list_t result = { - .field = { - .name = "data", - .lsb = 0, - .msb = 0x1f, - .values = NULL - }, - .get_next = NULL - }; - return result; -} - -static riscv_debug_reg_field_list_t dmi_serrx_get_data(riscv_debug_reg_ctx_t context) -{ - riscv_debug_reg_field_list_t result = { - .field = { - .name = "data", - .lsb = 0, - .msb = 0x1f, - .values = NULL - }, - .get_next = NULL - }; - return result; -} - riscv_debug_reg_info_t get_riscv_debug_reg_info(enum riscv_debug_reg_ordinal reg_ordinal) { static const riscv_debug_reg_info_t debug_reg_info[] = { @@ -3997,6 +3635,14 @@ riscv_debug_reg_info_t get_riscv_debug_reg_info(enum riscv_debug_reg_ordinal reg .name = "dpc", .get_fields_head = csr_dpc_get_dpc }, + [CSR_DSCRATCH0_ORDINAL] = { + .name = "dscratch0", + .get_fields_head = csr_dscratch0_get_dscratch0 + }, + [CSR_DSCRATCH1_ORDINAL] = { + .name = "dscratch1", + .get_fields_head = csr_dscratch1_get_dscratch1 + }, [CSR_TSELECT_ORDINAL] = { .name = "tselect", .get_fields_head = csr_tselect_get_index @@ -4021,14 +3667,14 @@ riscv_debug_reg_info_t get_riscv_debug_reg_info(enum riscv_debug_reg_ordinal reg .name = "tcontrol", .get_fields_head = csr_tcontrol_get_mte }, - [CSR_HCONTEXT_ORDINAL] = { - .name = "hcontext", - .get_fields_head = csr_hcontext_get_hcontext - }, [CSR_SCONTEXT_ORDINAL] = { .name = "scontext", .get_fields_head = csr_scontext_get_data }, + [CSR_MCONTEXT_ORDINAL] = { + .name = "mcontext", + .get_fields_head = csr_mcontext_get_hcontext + }, [CSR_MCONTROL_ORDINAL] = { .name = "mcontrol", .get_fields_head = csr_mcontrol_get_load @@ -4201,18 +3847,6 @@ riscv_debug_reg_info_t get_riscv_debug_reg_info(enum riscv_debug_reg_ordinal reg .name = "priv", .get_fields_head = virt_priv_get_prv }, - [DMI_SERCS_ORDINAL] = { - .name = "sercs", - .get_fields_head = dmi_sercs_get_full0 - }, - [DMI_SERTX_ORDINAL] = { - .name = "sertx", - .get_fields_head = dmi_sertx_get_data - }, - [DMI_SERRX_ORDINAL] = { - .name = "serrx", - .get_fields_head = dmi_serrx_get_data - }, }; return debug_reg_info[reg_ordinal]; } diff --git a/src/target/riscv/debug_defines.h b/src/target/riscv/debug_defines.h index a1dea5a91..dbe5142a8 100644 --- a/src/target/riscv/debug_defines.h +++ b/src/target/riscv/debug_defines.h @@ -1,6 +1,6 @@ /* * This file is auto-generated by running 'make debug_defines' in - * https://github.com/riscv/riscv-debug-spec/ (f546ddf) + * https://github.com/riscv/riscv-debug-spec/ (40b9a05) */ #ifndef DEBUG_DEFINES_H @@ -9,15 +9,15 @@ /* * Identifies the release version of this part. */ -#define DTM_IDCODE_VERSION_OFFSET 0x1c -#define DTM_IDCODE_VERSION_LENGTH 4 -#define DTM_IDCODE_VERSION 0xf0000000U +#define DTM_IDCODE_VERSION_OFFSET 0x1cULL +#define DTM_IDCODE_VERSION_LENGTH 4ULL +#define DTM_IDCODE_VERSION 0xf0000000ULL /* * Identifies the designer's part number of this part. */ -#define DTM_IDCODE_PARTNUMBER_OFFSET 0xc -#define DTM_IDCODE_PARTNUMBER_LENGTH 0x10 -#define DTM_IDCODE_PARTNUMBER 0xffff000 +#define DTM_IDCODE_PARTNUMBER_OFFSET 0xcULL +#define DTM_IDCODE_PARTNUMBER_LENGTH 0x10ULL +#define DTM_IDCODE_PARTNUMBER 0xffff000ULL /* * Identifies the designer/manufacturer of this part. Bits 6:0 must be * bits 6:0 of the designer/manufacturer's Identification Code as @@ -25,12 +25,12 @@ * count of the number of continuation characters (0x7f) in that same * Identification Code. */ -#define DTM_IDCODE_MANUFID_OFFSET 1 -#define DTM_IDCODE_MANUFID_LENGTH 0xb -#define DTM_IDCODE_MANUFID 0xffe -#define DTM_IDCODE_1_OFFSET 0 -#define DTM_IDCODE_1_LENGTH 1 -#define DTM_IDCODE_1 1 +#define DTM_IDCODE_MANUFID_OFFSET 1ULL +#define DTM_IDCODE_MANUFID_LENGTH 0xbULL +#define DTM_IDCODE_MANUFID 0xffeULL +#define DTM_IDCODE_1_OFFSET 0ULL +#define DTM_IDCODE_1_LENGTH 1ULL +#define DTM_IDCODE_1 1ULL #define DTM_DTMCS 0x10 /* * This optional field may provide additional detail about an error @@ -38,9 +38,9 @@ * \FdtmDmiOp is updated by the hardware or when 1 is written to * \FdtmDtmcsDmireset. */ -#define DTM_DTMCS_ERRINFO_OFFSET 0x12 -#define DTM_DTMCS_ERRINFO_LENGTH 3 -#define DTM_DTMCS_ERRINFO 0x1c0000 +#define DTM_DTMCS_ERRINFO_OFFSET 0x12ULL +#define DTM_DTMCS_ERRINFO_LENGTH 3ULL +#define DTM_DTMCS_ERRINFO 0x1c0000ULL /* * not implemented: This field is not implemented. */ @@ -74,16 +74,16 @@ * complete (e.g. a reset condition caused an inflight DMI transaction to * be cancelled). */ -#define DTM_DTMCS_DTMHARDRESET_OFFSET 0x11 -#define DTM_DTMCS_DTMHARDRESET_LENGTH 1 -#define DTM_DTMCS_DTMHARDRESET 0x20000 +#define DTM_DTMCS_DTMHARDRESET_OFFSET 0x11ULL +#define DTM_DTMCS_DTMHARDRESET_LENGTH 1ULL +#define DTM_DTMCS_DTMHARDRESET 0x20000ULL /* * Writing 1 to this bit clears the sticky error state and resets * \FdtmDtmcsErrinfo, but does not affect outstanding DMI transactions. */ -#define DTM_DTMCS_DMIRESET_OFFSET 0x10 -#define DTM_DTMCS_DMIRESET_LENGTH 1 -#define DTM_DTMCS_DMIRESET 0x10000 +#define DTM_DTMCS_DMIRESET_OFFSET 0x10ULL +#define DTM_DTMCS_DMIRESET_LENGTH 1ULL +#define DTM_DTMCS_DMIRESET 0x10000ULL /* * This is a hint to the debugger of the minimum number of * cycles a debugger should spend in @@ -99,24 +99,24 @@ * * And so on. */ -#define DTM_DTMCS_IDLE_OFFSET 0xc -#define DTM_DTMCS_IDLE_LENGTH 3 -#define DTM_DTMCS_IDLE 0x7000 +#define DTM_DTMCS_IDLE_OFFSET 0xcULL +#define DTM_DTMCS_IDLE_LENGTH 3ULL +#define DTM_DTMCS_IDLE 0x7000ULL /* * Read-only alias of \FdtmDmiOp. */ -#define DTM_DTMCS_DMISTAT_OFFSET 0xa -#define DTM_DTMCS_DMISTAT_LENGTH 2 -#define DTM_DTMCS_DMISTAT 0xc00 +#define DTM_DTMCS_DMISTAT_OFFSET 0xaULL +#define DTM_DTMCS_DMISTAT_LENGTH 2ULL +#define DTM_DTMCS_DMISTAT 0xc00ULL /* * The size of \FdmSbaddressZeroAddress in \RdtmDmi. */ -#define DTM_DTMCS_ABITS_OFFSET 4 -#define DTM_DTMCS_ABITS_LENGTH 6 -#define DTM_DTMCS_ABITS 0x3f0 -#define DTM_DTMCS_VERSION_OFFSET 0 -#define DTM_DTMCS_VERSION_LENGTH 4 -#define DTM_DTMCS_VERSION 0xf +#define DTM_DTMCS_ABITS_OFFSET 4ULL +#define DTM_DTMCS_ABITS_LENGTH 6ULL +#define DTM_DTMCS_ABITS 0x3f0ULL +#define DTM_DTMCS_VERSION_OFFSET 0ULL +#define DTM_DTMCS_VERSION_LENGTH 4ULL +#define DTM_DTMCS_VERSION 0xfULL /* * 0.11: Version described in spec version 0.11. */ @@ -136,22 +136,22 @@ * \FdtmDmiOp defines what this register contains after every possible * operation. */ -#define DTM_DMI_ADDRESS_OFFSET 0x22 +#define DTM_DMI_ADDRESS_OFFSET 0x22ULL #define DTM_DMI_ADDRESS_LENGTH(abits) (abits) #define DTM_DMI_ADDRESS(abits) ((0x400000000ULL * (1ULL << (abits))) + -0x400000000ULL) /* * The data to send to the DM over the DMI during Update-DR, and * the data returned from the DM as a result of the previous operation. */ -#define DTM_DMI_DATA_OFFSET 2 -#define DTM_DMI_DATA_LENGTH 0x20 +#define DTM_DMI_DATA_OFFSET 2ULL +#define DTM_DMI_DATA_LENGTH 0x20ULL #define DTM_DMI_DATA 0x3fffffffcULL /* * When the debugger writes this field, it has the following meaning: */ -#define DTM_DMI_OP_OFFSET 0 -#define DTM_DMI_OP_LENGTH 2 -#define DTM_DMI_OP 3 +#define DTM_DMI_OP_OFFSET 0ULL +#define DTM_DMI_OP_LENGTH 2ULL +#define DTM_DMI_OP 3ULL /* * nop: Ignore \FdmSbdataZeroData and \FdmSbaddressZeroAddress. * @@ -217,9 +217,9 @@ */ #define DTM_DMI_OP_BUSY 3 #define CSR_DCSR 0x7b0 -#define CSR_DCSR_DEBUGVER_OFFSET 0x1c -#define CSR_DCSR_DEBUGVER_LENGTH 4 -#define CSR_DCSR_DEBUGVER 0xf0000000U +#define CSR_DCSR_DEBUGVER_OFFSET 0x1cULL +#define CSR_DCSR_DEBUGVER_LENGTH 4ULL +#define CSR_DCSR_DEBUGVER 0xf0000000ULL /* * none: There is no debug support. */ @@ -233,9 +233,9 @@ * available version of this spec. */ #define CSR_DCSR_DEBUGVER_CUSTOM 15 -#define CSR_DCSR_EBREAKVS_OFFSET 0x11 -#define CSR_DCSR_EBREAKVS_LENGTH 1 -#define CSR_DCSR_EBREAKVS 0x20000 +#define CSR_DCSR_EBREAKVS_OFFSET 0x11ULL +#define CSR_DCSR_EBREAKVS_LENGTH 1ULL +#define CSR_DCSR_EBREAKVS 0x20000ULL /* * exception: {\tt ebreak} instructions in VS-mode behave as described in the * Privileged Spec. @@ -248,9 +248,9 @@ /* * This bit is hardwired to 0 if the hart does not support virtualization mode. */ -#define CSR_DCSR_EBREAKVU_OFFSET 0x10 -#define CSR_DCSR_EBREAKVU_LENGTH 1 -#define CSR_DCSR_EBREAKVU 0x10000 +#define CSR_DCSR_EBREAKVU_OFFSET 0x10ULL +#define CSR_DCSR_EBREAKVU_LENGTH 1ULL +#define CSR_DCSR_EBREAKVU 0x10000ULL /* * exception: {\tt ebreak} instructions in VU-mode behave as described in the * Privileged Spec. @@ -263,9 +263,9 @@ /* * This bit is hardwired to 0 if the hart does not support virtualization mode. */ -#define CSR_DCSR_EBREAKM_OFFSET 0xf -#define CSR_DCSR_EBREAKM_LENGTH 1 -#define CSR_DCSR_EBREAKM 0x8000 +#define CSR_DCSR_EBREAKM_OFFSET 0xfULL +#define CSR_DCSR_EBREAKM_LENGTH 1ULL +#define CSR_DCSR_EBREAKM 0x8000ULL /* * exception: {\tt ebreak} instructions in M-mode behave as described in the * Privileged Spec. @@ -275,9 +275,9 @@ * debug mode: {\tt ebreak} instructions in M-mode enter Debug Mode. */ #define CSR_DCSR_EBREAKM_DEBUG_MODE 1 -#define CSR_DCSR_EBREAKS_OFFSET 0xd -#define CSR_DCSR_EBREAKS_LENGTH 1 -#define CSR_DCSR_EBREAKS 0x2000 +#define CSR_DCSR_EBREAKS_OFFSET 0xdULL +#define CSR_DCSR_EBREAKS_LENGTH 1ULL +#define CSR_DCSR_EBREAKS 0x2000ULL /* * exception: {\tt ebreak} instructions in S-mode behave as described in the * Privileged Spec. @@ -290,9 +290,9 @@ /* * This bit is hardwired to 0 if the hart does not support S-mode. */ -#define CSR_DCSR_EBREAKU_OFFSET 0xc -#define CSR_DCSR_EBREAKU_LENGTH 1 -#define CSR_DCSR_EBREAKU 0x1000 +#define CSR_DCSR_EBREAKU_OFFSET 0xcULL +#define CSR_DCSR_EBREAKU_LENGTH 1ULL +#define CSR_DCSR_EBREAKU 0x1000ULL /* * exception: {\tt ebreak} instructions in U-mode behave as described in the * Privileged Spec. @@ -305,9 +305,9 @@ /* * This bit is hardwired to 0 if the hart does not support U-mode. */ -#define CSR_DCSR_STEPIE_OFFSET 0xb -#define CSR_DCSR_STEPIE_LENGTH 1 -#define CSR_DCSR_STEPIE 0x800 +#define CSR_DCSR_STEPIE_OFFSET 0xbULL +#define CSR_DCSR_STEPIE_LENGTH 1ULL +#define CSR_DCSR_STEPIE 0x800ULL /* * interrupts disabled: Interrupts (including NMI) are disabled during single stepping * with \FcsrDcsrStep set. @@ -326,9 +326,9 @@ * The debugger must not change the value of this bit while the hart * is running. */ -#define CSR_DCSR_STOPCOUNT_OFFSET 0xa -#define CSR_DCSR_STOPCOUNT_LENGTH 1 -#define CSR_DCSR_STOPCOUNT 0x400 +#define CSR_DCSR_STOPCOUNT_OFFSET 0xaULL +#define CSR_DCSR_STOPCOUNT_LENGTH 1ULL +#define CSR_DCSR_STOPCOUNT 0x400ULL /* * normal: Increment counters as usual. */ @@ -344,9 +344,9 @@ /* * An implementation may hardwire this bit to 0 or 1. */ -#define CSR_DCSR_STOPTIME_OFFSET 9 -#define CSR_DCSR_STOPTIME_LENGTH 1 -#define CSR_DCSR_STOPTIME 0x200 +#define CSR_DCSR_STOPTIME_OFFSET 9ULL +#define CSR_DCSR_STOPTIME_LENGTH 1ULL +#define CSR_DCSR_STOPTIME 0x200ULL /* * normal: \Rtime continues to reflect \Rmtime. */ @@ -370,9 +370,9 @@ * cycle, hardware should set \FcsrDcsrCause to the cause with the highest * priority. See table~\ref{tab:dcsrcausepriority} for priorities. */ -#define CSR_DCSR_CAUSE_OFFSET 6 -#define CSR_DCSR_CAUSE_LENGTH 3 -#define CSR_DCSR_CAUSE 0x1c0 +#define CSR_DCSR_CAUSE_OFFSET 6ULL +#define CSR_DCSR_CAUSE_LENGTH 3ULL +#define CSR_DCSR_CAUSE 0x1c0ULL /* * ebreak: An {\tt ebreak} instruction was executed. */ @@ -410,12 +410,12 @@ * when exiting Debug Mode. * This bit is hardwired to 0 on harts that do not support virtualization mode. */ -#define CSR_DCSR_V_OFFSET 5 -#define CSR_DCSR_V_LENGTH 1 -#define CSR_DCSR_V 0x20 -#define CSR_DCSR_MPRVEN_OFFSET 4 -#define CSR_DCSR_MPRVEN_LENGTH 1 -#define CSR_DCSR_MPRVEN 0x10 +#define CSR_DCSR_V_OFFSET 5ULL +#define CSR_DCSR_V_LENGTH 1ULL +#define CSR_DCSR_V 0x20ULL +#define CSR_DCSR_MPRVEN_OFFSET 4ULL +#define CSR_DCSR_MPRVEN_LENGTH 1ULL +#define CSR_DCSR_MPRVEN 0x10ULL /* * disabled: \FcsrMstatusMprv in \Rmstatus is ignored in Debug Mode. */ @@ -434,9 +434,9 @@ * reliable debugging may no longer be possible once this bit becomes set. * This is implementation-dependent. */ -#define CSR_DCSR_NMIP_OFFSET 3 -#define CSR_DCSR_NMIP_LENGTH 1 -#define CSR_DCSR_NMIP 8 +#define CSR_DCSR_NMIP_OFFSET 3ULL +#define CSR_DCSR_NMIP_LENGTH 1ULL +#define CSR_DCSR_NMIP 8ULL /* * When set and not in Debug Mode, the hart will only execute a single * instruction and then enter Debug Mode. See Section~\ref{stepBit} @@ -445,9 +445,9 @@ * The debugger must not change the value of this bit while the hart * is running. */ -#define CSR_DCSR_STEP_OFFSET 2 -#define CSR_DCSR_STEP_LENGTH 1 -#define CSR_DCSR_STEP 4 +#define CSR_DCSR_STEP_OFFSET 2ULL +#define CSR_DCSR_STEP_LENGTH 1ULL +#define CSR_DCSR_STEP 4ULL /* * Contains the privilege mode the hart was operating in when Debug * Mode was entered. The encoding is described in Table @@ -458,23 +458,29 @@ * encoding written is not supported or the debugger is not allowed to * change to it, the hart may change to any supported privilege mode. */ -#define CSR_DCSR_PRV_OFFSET 0 -#define CSR_DCSR_PRV_LENGTH 2 -#define CSR_DCSR_PRV 3 +#define CSR_DCSR_PRV_OFFSET 0ULL +#define CSR_DCSR_PRV_LENGTH 2ULL +#define CSR_DCSR_PRV 3ULL #define CSR_DPC 0x7b1 -#define CSR_DPC_DPC_OFFSET 0 +#define CSR_DPC_DPC_OFFSET 0ULL #define CSR_DPC_DPC_LENGTH(DXLEN) (DXLEN) -#define CSR_DPC_DPC(DXLEN) ((1ULL << (DXLEN)) + -1) +#define CSR_DPC_DPC(DXLEN) ((1ULL << (DXLEN)) + -1ULL) #define CSR_DSCRATCH0 0x7b2 +#define CSR_DSCRATCH0_DSCRATCH0_OFFSET 0ULL +#define CSR_DSCRATCH0_DSCRATCH0_LENGTH(DXLEN) (DXLEN) +#define CSR_DSCRATCH0_DSCRATCH0(DXLEN) ((1ULL << (DXLEN)) + -1ULL) #define CSR_DSCRATCH1 0x7b3 +#define CSR_DSCRATCH1_DSCRATCH1_OFFSET 0ULL +#define CSR_DSCRATCH1_DSCRATCH1_LENGTH(DXLEN) (DXLEN) +#define CSR_DSCRATCH1_DSCRATCH1(DXLEN) ((1ULL << (DXLEN)) + -1ULL) #define CSR_TSELECT 0x7a0 -#define CSR_TSELECT_INDEX_OFFSET 0 +#define CSR_TSELECT_INDEX_OFFSET 0ULL #define CSR_TSELECT_INDEX_LENGTH(XLEN) (XLEN) -#define CSR_TSELECT_INDEX(XLEN) ((1ULL << (XLEN)) + -1) +#define CSR_TSELECT_INDEX(XLEN) ((1ULL << (XLEN)) + -1ULL) #define CSR_TDATA1 0x7a1 -#define CSR_TDATA1_TYPE_OFFSET(XLEN) ((XLEN) + -4) -#define CSR_TDATA1_TYPE_LENGTH 4 -#define CSR_TDATA1_TYPE(XLEN) (0xf * (1ULL << ((XLEN) + -4))) +#define CSR_TDATA1_TYPE_OFFSET(XLEN) ((XLEN) + -4ULL) +#define CSR_TDATA1_TYPE_LENGTH 4ULL +#define CSR_TDATA1_TYPE(XLEN) (0xfULL * (1ULL << ((XLEN) + -4ULL))) /* * none: There is no trigger at this \RcsrTselect. */ @@ -535,9 +541,9 @@ /* * If \FcsrTdataOneType is 0, then this bit is hard-wired to 0. */ -#define CSR_TDATA1_DMODE_OFFSET(XLEN) ((XLEN) + -5) -#define CSR_TDATA1_DMODE_LENGTH 1 -#define CSR_TDATA1_DMODE(XLEN) (1ULL << ((XLEN) + -5)) +#define CSR_TDATA1_DMODE_OFFSET(XLEN) ((XLEN) + -5ULL) +#define CSR_TDATA1_DMODE_LENGTH 1ULL +#define CSR_TDATA1_DMODE(XLEN) (1ULL << ((XLEN) + -5ULL)) /* * both: Both Debug and M-mode can write the {\tt tdata} registers at the * selected \RcsrTselect. @@ -561,24 +567,24 @@ * * Trigger-specific data. */ -#define CSR_TDATA1_DATA_OFFSET 0 -#define CSR_TDATA1_DATA_LENGTH(XLEN) ((XLEN) + -5) -#define CSR_TDATA1_DATA(XLEN) ((1ULL << ((XLEN) + -5)) + -1) +#define CSR_TDATA1_DATA_OFFSET 0ULL +#define CSR_TDATA1_DATA_LENGTH(XLEN) ((XLEN) + -5ULL) +#define CSR_TDATA1_DATA(XLEN) ((1ULL << ((XLEN) + -5ULL)) + -1ULL) #define CSR_TDATA2 0x7a2 -#define CSR_TDATA2_DATA_OFFSET 0 +#define CSR_TDATA2_DATA_OFFSET 0ULL #define CSR_TDATA2_DATA_LENGTH(XLEN) (XLEN) -#define CSR_TDATA2_DATA(XLEN) ((1ULL << (XLEN)) + -1) +#define CSR_TDATA2_DATA(XLEN) ((1ULL << (XLEN)) + -1ULL) #define CSR_TDATA3 0x7a3 -#define CSR_TDATA3_DATA_OFFSET 0 +#define CSR_TDATA3_DATA_OFFSET 0ULL #define CSR_TDATA3_DATA_LENGTH(XLEN) (XLEN) -#define CSR_TDATA3_DATA(XLEN) ((1ULL << (XLEN)) + -1) +#define CSR_TDATA3_DATA(XLEN) ((1ULL << (XLEN)) + -1ULL) #define CSR_TINFO 0x7a4 /* * Contains the version of the Sdtrig extension implemented. */ -#define CSR_TINFO_VERSION_OFFSET 0x18 -#define CSR_TINFO_VERSION_LENGTH 8 -#define CSR_TINFO_VERSION 0xff000000U +#define CSR_TINFO_VERSION_OFFSET 0x18ULL +#define CSR_TINFO_VERSION_LENGTH 8ULL +#define CSR_TINFO_VERSION 0xff000000ULL /* * 0: Supports triggers as described in this spec at commit 5a5c078, * made on February 2, 2023. @@ -606,9 +612,9 @@ * If the currently selected trigger doesn't exist, this field * contains 1. */ -#define CSR_TINFO_INFO_OFFSET 0 -#define CSR_TINFO_INFO_LENGTH 0x10 -#define CSR_TINFO_INFO 0xffff +#define CSR_TINFO_INFO_OFFSET 0ULL +#define CSR_TINFO_INFO_LENGTH 0x10ULL +#define CSR_TINFO_INFO 0xffffULL #define CSR_TCONTROL 0x7a5 /* * M-mode previous trigger enable field. @@ -617,18 +623,18 @@ * regarding triggers with action=0 firing in M-mode trap handlers. See * Section~\ref{sec:nativetrigger} for more details. * - * When a breakpoint trap into M-mode is taken, \FcsrTcontrolMpte is set to the value of + * When any trap into M-mode is taken, \FcsrTcontrolMpte is set to the value of * \FcsrTcontrolMte. */ -#define CSR_TCONTROL_MPTE_OFFSET 7 -#define CSR_TCONTROL_MPTE_LENGTH 1 -#define CSR_TCONTROL_MPTE 0x80 +#define CSR_TCONTROL_MPTE_OFFSET 7ULL +#define CSR_TCONTROL_MPTE_LENGTH 1ULL +#define CSR_TCONTROL_MPTE 0x80ULL /* * M-mode trigger enable field. */ -#define CSR_TCONTROL_MTE_OFFSET 3 -#define CSR_TCONTROL_MTE_LENGTH 1 -#define CSR_TCONTROL_MTE 8 +#define CSR_TCONTROL_MTE_OFFSET 3ULL +#define CSR_TCONTROL_MTE_LENGTH 1ULL +#define CSR_TCONTROL_MTE 8ULL /* * disabled: Triggers with action=0 do not match/fire while the hart is in M-mode. */ @@ -638,25 +644,10 @@ */ #define CSR_TCONTROL_MTE_ENABLED 1 /* - * When a breakpoint trap into M-mode is taken, \FcsrTcontrolMte is set to 0. When {\tt + * When any trap into M-mode is taken, \FcsrTcontrolMte is set to 0. When {\tt * mret} is executed, \FcsrTcontrolMte is set to the value of \FcsrTcontrolMpte. */ #define CSR_HCONTEXT 0x6a8 -/* - * Hypervisor mode software can write a context number to this register, - * which can be used to set triggers that only fire in that specific - * context. - * - * An implementation may tie any number of upper bits in this field to - * 0. If the H extension is not implemented, it's recommended to implement - * no more than 6 bits on RV32 and 13 on RV64 (as visible through the - * \RcsrMcontext register). If the H extension is implemented, - * it's recommended to implement no more than 7 bits on RV32 - * and 14 on RV64. - */ -#define CSR_HCONTEXT_HCONTEXT_OFFSET 0 -#define CSR_HCONTEXT_HCONTEXT_LENGTH(XLEN) (XLEN) -#define CSR_HCONTEXT_HCONTEXT(XLEN) ((1ULL << (XLEN)) + -1) #define CSR_SCONTEXT 0x5a8 /* * Supervisor mode software can write a context number to this @@ -667,18 +658,33 @@ * 0. It's recommended to implement no more than 16 bits on RV32, and * 34 on RV64. */ -#define CSR_SCONTEXT_DATA_OFFSET 0 +#define CSR_SCONTEXT_DATA_OFFSET 0ULL #define CSR_SCONTEXT_DATA_LENGTH(XLEN) (XLEN) -#define CSR_SCONTEXT_DATA(XLEN) ((1ULL << (XLEN)) + -1) +#define CSR_SCONTEXT_DATA(XLEN) ((1ULL << (XLEN)) + -1ULL) #define CSR_MCONTEXT 0x7a8 +/* + * M-Mode or HS-Mode (using \RcsrHcontext) software can write a context + * number to this register, which can be used to set triggers that only + * fire in that specific context. + * + * An implementation may tie any number of upper bits in this field to + * 0. If the H extension is not implemented, it's recommended to implement + * no more than 6 bits on RV32 and 13 on RV64 (as visible through the + * \RcsrMcontext register). If the H extension is implemented, + * it's recommended to implement no more than 7 bits on RV32 + * and 14 on RV64. + */ +#define CSR_MCONTEXT_HCONTEXT_OFFSET 0ULL +#define CSR_MCONTEXT_HCONTEXT_LENGTH(XLEN) (XLEN) +#define CSR_MCONTEXT_HCONTEXT(XLEN) ((1ULL << (XLEN)) + -1ULL) #define CSR_MSCONTEXT 0x7aa #define CSR_MCONTROL 0x7a1 -#define CSR_MCONTROL_TYPE_OFFSET(XLEN) ((XLEN) + -4) -#define CSR_MCONTROL_TYPE_LENGTH 4 -#define CSR_MCONTROL_TYPE(XLEN) (0xf * (1ULL << ((XLEN) + -4))) -#define CSR_MCONTROL_DMODE_OFFSET(XLEN) ((XLEN) + -5) -#define CSR_MCONTROL_DMODE_LENGTH 1 -#define CSR_MCONTROL_DMODE(XLEN) (1ULL << ((XLEN) + -5)) +#define CSR_MCONTROL_TYPE_OFFSET(XLEN) ((XLEN) + -4ULL) +#define CSR_MCONTROL_TYPE_LENGTH 4ULL +#define CSR_MCONTROL_TYPE(XLEN) (0xfULL * (1ULL << ((XLEN) + -4ULL))) +#define CSR_MCONTROL_DMODE_OFFSET(XLEN) ((XLEN) + -5ULL) +#define CSR_MCONTROL_DMODE_LENGTH 1ULL +#define CSR_MCONTROL_DMODE(XLEN) (1ULL << ((XLEN) + -5ULL)) /* * Specifies the largest naturally aligned powers-of-two (NAPOT) range * supported by the hardware when \FcsrMcontrolMatch is 1. The value is the @@ -687,18 +693,18 @@ * A value of 63 corresponds to the maximum NAPOT range, which is * $2^{63}$ bytes in size. */ -#define CSR_MCONTROL_MASKMAX_OFFSET(XLEN) ((XLEN) + -0xb) -#define CSR_MCONTROL_MASKMAX_LENGTH 6 -#define CSR_MCONTROL_MASKMAX(XLEN) (0x3f * (1ULL << ((XLEN) + -0xb))) +#define CSR_MCONTROL_MASKMAX_OFFSET(XLEN) ((XLEN) + -0xbULL) +#define CSR_MCONTROL_MASKMAX_LENGTH 6ULL +#define CSR_MCONTROL_MASKMAX(XLEN) (0x3fULL * (1ULL << ((XLEN) + -0xbULL))) /* * This field only exists when XLEN is at least 64. * It contains the 2 high bits of the access size. The low bits * come from \FcsrMcontrolSizelo. See \FcsrMcontrolSizelo for how this * is used. */ -#define CSR_MCONTROL_SIZEHI_OFFSET 0x15 -#define CSR_MCONTROL_SIZEHI_LENGTH 2 -#define CSR_MCONTROL_SIZEHI 0x600000 +#define CSR_MCONTROL_SIZEHI_OFFSET 0x15ULL +#define CSR_MCONTROL_SIZEHI_LENGTH 2ULL +#define CSR_MCONTROL_SIZEHI 0x600000ULL /* * If this bit is implemented then it must become set when this * trigger fires and may become set when this trigger matches. @@ -707,15 +713,15 @@ * trigger(s) matched. If the bit is not implemented, it is always 0 * and writing it has no effect. */ -#define CSR_MCONTROL_HIT_OFFSET 0x14 -#define CSR_MCONTROL_HIT_LENGTH 1 -#define CSR_MCONTROL_HIT 0x100000 +#define CSR_MCONTROL_HIT_OFFSET 0x14ULL +#define CSR_MCONTROL_HIT_LENGTH 1ULL +#define CSR_MCONTROL_HIT 0x100000ULL /* * This bit determines the contents of the XLEN-bit compare values. */ -#define CSR_MCONTROL_SELECT_OFFSET 0x13 -#define CSR_MCONTROL_SELECT_LENGTH 1 -#define CSR_MCONTROL_SELECT 0x80000 +#define CSR_MCONTROL_SELECT_OFFSET 0x13ULL +#define CSR_MCONTROL_SELECT_LENGTH 1ULL +#define CSR_MCONTROL_SELECT 0x80000ULL /* * address: There is at least one compare value and it contains the lowest * virtual address of the access. @@ -731,9 +737,9 @@ * Any bits beyond the size of the data access will contain 0. */ #define CSR_MCONTROL_SELECT_DATA 1 -#define CSR_MCONTROL_TIMING_OFFSET 0x12 -#define CSR_MCONTROL_TIMING_LENGTH 1 -#define CSR_MCONTROL_TIMING 0x40000 +#define CSR_MCONTROL_TIMING_OFFSET 0x12ULL +#define CSR_MCONTROL_TIMING_LENGTH 1ULL +#define CSR_MCONTROL_TIMING 0x40000ULL /* * before: The action for this trigger will be taken just before the * instruction that triggered it is retired, but after all preceding @@ -747,6 +753,10 @@ * though the load will not update its destination register. Debuggers * should consider this when setting such breakpoints on, for example, * memory-mapped I/O addresses. + * + * If an instruction matches this trigger and the instruction performs + * multiple memory accesses, it is \unspecified which memory accesses + * have completed before the trigger fires. */ #define CSR_MCONTROL_TIMING_BEFORE 0 /* @@ -780,9 +790,9 @@ * This field contains the 2 low bits of the access size. The high bits come * from \FcsrMcontrolSizehi. The combined value is interpreted as follows: */ -#define CSR_MCONTROL_SIZELO_OFFSET 0x10 -#define CSR_MCONTROL_SIZELO_LENGTH 2 -#define CSR_MCONTROL_SIZELO 0x30000 +#define CSR_MCONTROL_SIZELO_OFFSET 0x10ULL +#define CSR_MCONTROL_SIZELO_LENGTH 2ULL +#define CSR_MCONTROL_SIZELO 0x30000ULL /* * any: The trigger will attempt to match against an access of any size. * The behavior is only well-defined if $|select|=0$, or if the access @@ -851,9 +861,9 @@ * The action to take when the trigger fires. The values are explained * in Table~\ref{tab:action}. */ -#define CSR_MCONTROL_ACTION_OFFSET 0xc -#define CSR_MCONTROL_ACTION_LENGTH 4 -#define CSR_MCONTROL_ACTION 0xf000 +#define CSR_MCONTROL_ACTION_OFFSET 0xcULL +#define CSR_MCONTROL_ACTION_LENGTH 4ULL +#define CSR_MCONTROL_ACTION 0xf000ULL /* * breakpoint: */ @@ -882,9 +892,9 @@ * external1: */ #define CSR_MCONTROL_ACTION_EXTERNAL1 9 -#define CSR_MCONTROL_CHAIN_OFFSET 0xb -#define CSR_MCONTROL_CHAIN_LENGTH 1 -#define CSR_MCONTROL_CHAIN 0x800 +#define CSR_MCONTROL_CHAIN_OFFSET 0xbULL +#define CSR_MCONTROL_CHAIN_LENGTH 1ULL +#define CSR_MCONTROL_CHAIN 0x800ULL /* * disabled: When this trigger matches, the configured action is taken. */ @@ -918,9 +928,9 @@ * chain (eg. to meet timing requirements) may do so by zeroing * \FcsrMcontrolChain in writes to \RcsrMcontrol that would make the chain too long. */ -#define CSR_MCONTROL_MATCH_OFFSET 7 -#define CSR_MCONTROL_MATCH_LENGTH 4 -#define CSR_MCONTROL_MATCH 0x780 +#define CSR_MCONTROL_MATCH_OFFSET 7ULL +#define CSR_MCONTROL_MATCH_LENGTH 4ULL +#define CSR_MCONTROL_MATCH 0x780ULL /* * equal: Matches when any compare value equals \RcsrTdataTwo. */ @@ -987,60 +997,60 @@ /* * When set, enable this trigger in M-mode. */ -#define CSR_MCONTROL_M_OFFSET 6 -#define CSR_MCONTROL_M_LENGTH 1 -#define CSR_MCONTROL_M 0x40 +#define CSR_MCONTROL_M_OFFSET 6ULL +#define CSR_MCONTROL_M_LENGTH 1ULL +#define CSR_MCONTROL_M 0x40ULL /* * When set, enable this trigger in S/HS-mode. * This bit is hard-wired to 0 if the hart does not support * S-mode. */ -#define CSR_MCONTROL_S_OFFSET 4 -#define CSR_MCONTROL_S_LENGTH 1 -#define CSR_MCONTROL_S 0x10 +#define CSR_MCONTROL_S_OFFSET 4ULL +#define CSR_MCONTROL_S_LENGTH 1ULL +#define CSR_MCONTROL_S 0x10ULL /* * When set, enable this trigger in U-mode. * This bit is hard-wired to 0 if the hart does not support * U-mode. */ -#define CSR_MCONTROL_U_OFFSET 3 -#define CSR_MCONTROL_U_LENGTH 1 -#define CSR_MCONTROL_U 8 +#define CSR_MCONTROL_U_OFFSET 3ULL +#define CSR_MCONTROL_U_LENGTH 1ULL +#define CSR_MCONTROL_U 8ULL /* * When set, the trigger fires on the virtual address or opcode of an * instruction that is executed. */ -#define CSR_MCONTROL_EXECUTE_OFFSET 2 -#define CSR_MCONTROL_EXECUTE_LENGTH 1 -#define CSR_MCONTROL_EXECUTE 4 +#define CSR_MCONTROL_EXECUTE_OFFSET 2ULL +#define CSR_MCONTROL_EXECUTE_LENGTH 1ULL +#define CSR_MCONTROL_EXECUTE 4ULL /* * When set, the trigger fires on the virtual address or data of any * store. */ -#define CSR_MCONTROL_STORE_OFFSET 1 -#define CSR_MCONTROL_STORE_LENGTH 1 -#define CSR_MCONTROL_STORE 2 +#define CSR_MCONTROL_STORE_OFFSET 1ULL +#define CSR_MCONTROL_STORE_LENGTH 1ULL +#define CSR_MCONTROL_STORE 2ULL /* * When set, the trigger fires on the virtual address or data of any * load. */ -#define CSR_MCONTROL_LOAD_OFFSET 0 -#define CSR_MCONTROL_LOAD_LENGTH 1 -#define CSR_MCONTROL_LOAD 1 +#define CSR_MCONTROL_LOAD_OFFSET 0ULL +#define CSR_MCONTROL_LOAD_LENGTH 1ULL +#define CSR_MCONTROL_LOAD 1ULL #define CSR_MCONTROL6 0x7a1 -#define CSR_MCONTROL6_TYPE_OFFSET(XLEN) ((XLEN) + -4) -#define CSR_MCONTROL6_TYPE_LENGTH 4 -#define CSR_MCONTROL6_TYPE(XLEN) (0xf * (1ULL << ((XLEN) + -4))) -#define CSR_MCONTROL6_DMODE_OFFSET(XLEN) ((XLEN) + -5) -#define CSR_MCONTROL6_DMODE_LENGTH 1 -#define CSR_MCONTROL6_DMODE(XLEN) (1ULL << ((XLEN) + -5)) +#define CSR_MCONTROL6_TYPE_OFFSET(XLEN) ((XLEN) + -4ULL) +#define CSR_MCONTROL6_TYPE_LENGTH 4ULL +#define CSR_MCONTROL6_TYPE(XLEN) (0xfULL * (1ULL << ((XLEN) + -4ULL))) +#define CSR_MCONTROL6_DMODE_OFFSET(XLEN) ((XLEN) + -5ULL) +#define CSR_MCONTROL6_DMODE_LENGTH 1ULL +#define CSR_MCONTROL6_DMODE(XLEN) (1ULL << ((XLEN) + -5ULL)) /* - * This bit should be updated every time that \FcsrMcontrolSixHitZero - * or \FcsrMcontrolSixHitOne is updated. + * If implemented, the TM updates this field every time the trigger + * fires. */ -#define CSR_MCONTROL6_UNCERTAIN_OFFSET 0x1a -#define CSR_MCONTROL6_UNCERTAIN_LENGTH 1 -#define CSR_MCONTROL6_UNCERTAIN 0x4000000 +#define CSR_MCONTROL6_UNCERTAIN_OFFSET 0x1aULL +#define CSR_MCONTROL6_UNCERTAIN_LENGTH 1ULL +#define CSR_MCONTROL6_UNCERTAIN 0x4000000ULL /* * certain: The trigger that fired satisfied the configured conditions, or * this bit is not implemented. @@ -1052,25 +1062,25 @@ * cannot be certain. */ #define CSR_MCONTROL6_UNCERTAIN_UNCERTAIN 1 -#define CSR_MCONTROL6_HIT1_OFFSET 0x19 -#define CSR_MCONTROL6_HIT1_LENGTH 1 -#define CSR_MCONTROL6_HIT1 0x2000000 +#define CSR_MCONTROL6_HIT1_OFFSET 0x19ULL +#define CSR_MCONTROL6_HIT1_LENGTH 1ULL +#define CSR_MCONTROL6_HIT1 0x2000000ULL /* * When set, enable this trigger in VS-mode. * This bit is hard-wired to 0 if the hart does not support * virtualization mode. */ -#define CSR_MCONTROL6_VS_OFFSET 0x18 -#define CSR_MCONTROL6_VS_LENGTH 1 -#define CSR_MCONTROL6_VS 0x1000000 +#define CSR_MCONTROL6_VS_OFFSET 0x18ULL +#define CSR_MCONTROL6_VS_LENGTH 1ULL +#define CSR_MCONTROL6_VS 0x1000000ULL /* * When set, enable this trigger in VU-mode. * This bit is hard-wired to 0 if the hart does not support * virtualization mode. */ -#define CSR_MCONTROL6_VU_OFFSET 0x17 -#define CSR_MCONTROL6_VU_LENGTH 1 -#define CSR_MCONTROL6_VU 0x800000 +#define CSR_MCONTROL6_VU_OFFSET 0x17ULL +#define CSR_MCONTROL6_VU_LENGTH 1ULL +#define CSR_MCONTROL6_VU 0x800000ULL /* * If they are implemented, \FcsrMcontrolSixHitOne (MSB) and * \FcsrMcontrolSixHitZero (LSB) combine into a single 2-bit field. @@ -1081,23 +1091,21 @@ * If either of the bits is not implemented, the unimplemented bits * will be read-only 0. */ -#define CSR_MCONTROL6_HIT0_OFFSET 0x16 -#define CSR_MCONTROL6_HIT0_LENGTH 1 -#define CSR_MCONTROL6_HIT0 0x400000 +#define CSR_MCONTROL6_HIT0_OFFSET 0x16ULL +#define CSR_MCONTROL6_HIT0_LENGTH 1ULL +#define CSR_MCONTROL6_HIT0 0x400000ULL /* * false: The trigger did not fire. */ #define CSR_MCONTROL6_HIT0_FALSE 0 /* - * before: The trigger fired just before the instruction that triggered it was - * retired, but after all preceding instructions are retired. + * before: The trigger fired before the instruction that matched it was + * retired, but after all preceding instructions are retired. This + * explicitly allows for instructions to be partially executed, as + * described in Section \ref{sec:multistate}. + * * \Rxepc or \RcsrDpc (depending on \FcsrMcontrolSixAction) must be set * to the virtual address of the instruction that matched. - * - * If a load operation matched and \FcsrMcontrolSixSelect=1 then a - * memory access has been performed (including any side effects of - * performing such an access) even though the load has not updated its - * destination register. */ #define CSR_MCONTROL6_HIT0_BEFORE 1 /* @@ -1114,14 +1122,17 @@ * \Rxepc or \RcsrDpc (depending on \FcsrMcontrolSixAction) must be set * to the virtual address of the next instruction that must be executed * to preserve the program flow. + * + * If the instruction performed multiple memory accesses, all of them + * have been completed. */ #define CSR_MCONTROL6_HIT0_IMMEDIATELY_AFTER 3 /* * This bit determines the contents of the XLEN-bit compare values. */ -#define CSR_MCONTROL6_SELECT_OFFSET 0x15 -#define CSR_MCONTROL6_SELECT_LENGTH 1 -#define CSR_MCONTROL6_SELECT 0x200000 +#define CSR_MCONTROL6_SELECT_OFFSET 0x15ULL +#define CSR_MCONTROL6_SELECT_LENGTH 1ULL +#define CSR_MCONTROL6_SELECT 0x200000ULL /* * address: There is at least one compare value and it contains the lowest * virtual address of the access. @@ -1137,9 +1148,9 @@ * Any bits beyond the size of the data access will contain 0. */ #define CSR_MCONTROL6_SELECT_DATA 1 -#define CSR_MCONTROL6_SIZE_OFFSET 0x10 -#define CSR_MCONTROL6_SIZE_LENGTH 3 -#define CSR_MCONTROL6_SIZE 0x70000 +#define CSR_MCONTROL6_SIZE_OFFSET 0x10ULL +#define CSR_MCONTROL6_SIZE_LENGTH 3ULL +#define CSR_MCONTROL6_SIZE 0x70000ULL /* * any: The trigger will attempt to match against an access of any size. * The behavior is only well-defined if $|select|=0$, or if the access @@ -1196,9 +1207,9 @@ * The action to take when the trigger fires. The values are explained * in Table~\ref{tab:action}. */ -#define CSR_MCONTROL6_ACTION_OFFSET 0xc -#define CSR_MCONTROL6_ACTION_LENGTH 4 -#define CSR_MCONTROL6_ACTION 0xf000 +#define CSR_MCONTROL6_ACTION_OFFSET 0xcULL +#define CSR_MCONTROL6_ACTION_LENGTH 4ULL +#define CSR_MCONTROL6_ACTION 0xf000ULL /* * breakpoint: */ @@ -1227,9 +1238,9 @@ * external1: */ #define CSR_MCONTROL6_ACTION_EXTERNAL1 9 -#define CSR_MCONTROL6_CHAIN_OFFSET 0xb -#define CSR_MCONTROL6_CHAIN_LENGTH 1 -#define CSR_MCONTROL6_CHAIN 0x800 +#define CSR_MCONTROL6_CHAIN_OFFSET 0xbULL +#define CSR_MCONTROL6_CHAIN_LENGTH 1ULL +#define CSR_MCONTROL6_CHAIN 0x800ULL /* * disabled: When this trigger matches, the configured action is taken. */ @@ -1263,9 +1274,9 @@ * chain (eg. to meet timing requirements) may do so by zeroing * \FcsrMcontrolSixChain in writes to \RcsrMcontrolSix that would make the chain too long. */ -#define CSR_MCONTROL6_MATCH_OFFSET 7 -#define CSR_MCONTROL6_MATCH_LENGTH 4 -#define CSR_MCONTROL6_MATCH 0x780 +#define CSR_MCONTROL6_MATCH_OFFSET 7ULL +#define CSR_MCONTROL6_MATCH_LENGTH 4ULL +#define CSR_MCONTROL6_MATCH 0x780ULL /* * equal: Matches when any compare value equals \RcsrTdataTwo. */ @@ -1334,12 +1345,12 @@ /* * When set, enable this trigger in M-mode. */ -#define CSR_MCONTROL6_M_OFFSET 6 -#define CSR_MCONTROL6_M_LENGTH 1 -#define CSR_MCONTROL6_M 0x40 -#define CSR_MCONTROL6_UNCERTAINEN_OFFSET 5 -#define CSR_MCONTROL6_UNCERTAINEN_LENGTH 1 -#define CSR_MCONTROL6_UNCERTAINEN 0x20 +#define CSR_MCONTROL6_M_OFFSET 6ULL +#define CSR_MCONTROL6_M_LENGTH 1ULL +#define CSR_MCONTROL6_M 0x40ULL +#define CSR_MCONTROL6_UNCERTAINEN_OFFSET 5ULL +#define CSR_MCONTROL6_UNCERTAINEN_LENGTH 1ULL +#define CSR_MCONTROL6_UNCERTAINEN 0x20ULL /* * disabled: This trigger will only match if the hardware can perfectly * evaluate it. @@ -1356,61 +1367,61 @@ * This bit is hard-wired to 0 if the hart does not support * S-mode. */ -#define CSR_MCONTROL6_S_OFFSET 4 -#define CSR_MCONTROL6_S_LENGTH 1 -#define CSR_MCONTROL6_S 0x10 +#define CSR_MCONTROL6_S_OFFSET 4ULL +#define CSR_MCONTROL6_S_LENGTH 1ULL +#define CSR_MCONTROL6_S 0x10ULL /* * When set, enable this trigger in U-mode. * This bit is hard-wired to 0 if the hart does not support * U-mode. */ -#define CSR_MCONTROL6_U_OFFSET 3 -#define CSR_MCONTROL6_U_LENGTH 1 -#define CSR_MCONTROL6_U 8 +#define CSR_MCONTROL6_U_OFFSET 3ULL +#define CSR_MCONTROL6_U_LENGTH 1ULL +#define CSR_MCONTROL6_U 8ULL /* * When set, the trigger fires on the virtual address or opcode of an * instruction that is executed. */ -#define CSR_MCONTROL6_EXECUTE_OFFSET 2 -#define CSR_MCONTROL6_EXECUTE_LENGTH 1 -#define CSR_MCONTROL6_EXECUTE 4 +#define CSR_MCONTROL6_EXECUTE_OFFSET 2ULL +#define CSR_MCONTROL6_EXECUTE_LENGTH 1ULL +#define CSR_MCONTROL6_EXECUTE 4ULL /* * When set, the trigger fires on the virtual address or data of any * store. */ -#define CSR_MCONTROL6_STORE_OFFSET 1 -#define CSR_MCONTROL6_STORE_LENGTH 1 -#define CSR_MCONTROL6_STORE 2 +#define CSR_MCONTROL6_STORE_OFFSET 1ULL +#define CSR_MCONTROL6_STORE_LENGTH 1ULL +#define CSR_MCONTROL6_STORE 2ULL /* * When set, the trigger fires on the virtual address or data of any * load. */ -#define CSR_MCONTROL6_LOAD_OFFSET 0 -#define CSR_MCONTROL6_LOAD_LENGTH 1 -#define CSR_MCONTROL6_LOAD 1 +#define CSR_MCONTROL6_LOAD_OFFSET 0ULL +#define CSR_MCONTROL6_LOAD_LENGTH 1ULL +#define CSR_MCONTROL6_LOAD 1ULL #define CSR_ICOUNT 0x7a1 -#define CSR_ICOUNT_TYPE_OFFSET(XLEN) ((XLEN) + -4) -#define CSR_ICOUNT_TYPE_LENGTH 4 -#define CSR_ICOUNT_TYPE(XLEN) (0xf * (1ULL << ((XLEN) + -4))) -#define CSR_ICOUNT_DMODE_OFFSET(XLEN) ((XLEN) + -5) -#define CSR_ICOUNT_DMODE_LENGTH 1 -#define CSR_ICOUNT_DMODE(XLEN) (1ULL << ((XLEN) + -5)) +#define CSR_ICOUNT_TYPE_OFFSET(XLEN) ((XLEN) + -4ULL) +#define CSR_ICOUNT_TYPE_LENGTH 4ULL +#define CSR_ICOUNT_TYPE(XLEN) (0xfULL * (1ULL << ((XLEN) + -4ULL))) +#define CSR_ICOUNT_DMODE_OFFSET(XLEN) ((XLEN) + -5ULL) +#define CSR_ICOUNT_DMODE_LENGTH 1ULL +#define CSR_ICOUNT_DMODE(XLEN) (1ULL << ((XLEN) + -5ULL)) /* * When set, enable this trigger in VS-mode. * This bit is hard-wired to 0 if the hart does not support * virtualization mode. */ -#define CSR_ICOUNT_VS_OFFSET 0x1a -#define CSR_ICOUNT_VS_LENGTH 1 -#define CSR_ICOUNT_VS 0x4000000 +#define CSR_ICOUNT_VS_OFFSET 0x1aULL +#define CSR_ICOUNT_VS_LENGTH 1ULL +#define CSR_ICOUNT_VS 0x4000000ULL /* * When set, enable this trigger in VU-mode. * This bit is hard-wired to 0 if the hart does not support * virtualization mode. */ -#define CSR_ICOUNT_VU_OFFSET 0x19 -#define CSR_ICOUNT_VU_LENGTH 1 -#define CSR_ICOUNT_VU 0x2000000 +#define CSR_ICOUNT_VU_OFFSET 0x19ULL +#define CSR_ICOUNT_VU_LENGTH 1ULL +#define CSR_ICOUNT_VU 0x2000000ULL /* * If this bit is implemented, the hardware sets it when this * trigger fires. The trigger's user can set or clear it at any @@ -1418,53 +1429,53 @@ * trigger(s) fires. If the bit is not implemented, it is always 0 * and writing it has no effect. */ -#define CSR_ICOUNT_HIT_OFFSET 0x18 -#define CSR_ICOUNT_HIT_LENGTH 1 -#define CSR_ICOUNT_HIT 0x1000000 +#define CSR_ICOUNT_HIT_OFFSET 0x18ULL +#define CSR_ICOUNT_HIT_LENGTH 1ULL +#define CSR_ICOUNT_HIT 0x1000000ULL /* * The trigger will generally fire after \FcsrIcountCount instructions * in enabled modes have been executed. See above for the precise behavior. */ -#define CSR_ICOUNT_COUNT_OFFSET 0xa -#define CSR_ICOUNT_COUNT_LENGTH 0xe -#define CSR_ICOUNT_COUNT 0xfffc00 +#define CSR_ICOUNT_COUNT_OFFSET 0xaULL +#define CSR_ICOUNT_COUNT_LENGTH 0xeULL +#define CSR_ICOUNT_COUNT 0xfffc00ULL /* * When set, enable this trigger in M-mode. */ -#define CSR_ICOUNT_M_OFFSET 9 -#define CSR_ICOUNT_M_LENGTH 1 -#define CSR_ICOUNT_M 0x200 +#define CSR_ICOUNT_M_OFFSET 9ULL +#define CSR_ICOUNT_M_LENGTH 1ULL +#define CSR_ICOUNT_M 0x200ULL /* * This bit becomes set when \FcsrIcountCount is decremented from 1 * to 0. It is cleared when the trigger fires, which will happen just * before executing the next instruction in one of the enabled modes. */ -#define CSR_ICOUNT_PENDING_OFFSET 8 -#define CSR_ICOUNT_PENDING_LENGTH 1 -#define CSR_ICOUNT_PENDING 0x100 +#define CSR_ICOUNT_PENDING_OFFSET 8ULL +#define CSR_ICOUNT_PENDING_LENGTH 1ULL +#define CSR_ICOUNT_PENDING 0x100ULL /* * When set, enable this trigger in S/HS-mode. * This bit is hard-wired to 0 if the hart does not support * S-mode. */ -#define CSR_ICOUNT_S_OFFSET 7 -#define CSR_ICOUNT_S_LENGTH 1 -#define CSR_ICOUNT_S 0x80 +#define CSR_ICOUNT_S_OFFSET 7ULL +#define CSR_ICOUNT_S_LENGTH 1ULL +#define CSR_ICOUNT_S 0x80ULL /* * When set, enable this trigger in U-mode. * This bit is hard-wired to 0 if the hart does not support * U-mode. */ -#define CSR_ICOUNT_U_OFFSET 6 -#define CSR_ICOUNT_U_LENGTH 1 -#define CSR_ICOUNT_U 0x40 +#define CSR_ICOUNT_U_OFFSET 6ULL +#define CSR_ICOUNT_U_LENGTH 1ULL +#define CSR_ICOUNT_U 0x40ULL /* * The action to take when the trigger fires. The values are explained * in Table~\ref{tab:action}. */ -#define CSR_ICOUNT_ACTION_OFFSET 0 -#define CSR_ICOUNT_ACTION_LENGTH 6 -#define CSR_ICOUNT_ACTION 0x3f +#define CSR_ICOUNT_ACTION_OFFSET 0ULL +#define CSR_ICOUNT_ACTION_LENGTH 6ULL +#define CSR_ICOUNT_ACTION 0x3fULL /* * breakpoint: */ @@ -1494,12 +1505,12 @@ */ #define CSR_ICOUNT_ACTION_EXTERNAL1 9 #define CSR_ITRIGGER 0x7a1 -#define CSR_ITRIGGER_TYPE_OFFSET(XLEN) ((XLEN) + -4) -#define CSR_ITRIGGER_TYPE_LENGTH 4 -#define CSR_ITRIGGER_TYPE(XLEN) (0xf * (1ULL << ((XLEN) + -4))) -#define CSR_ITRIGGER_DMODE_OFFSET(XLEN) ((XLEN) + -5) -#define CSR_ITRIGGER_DMODE_LENGTH 1 -#define CSR_ITRIGGER_DMODE(XLEN) (1ULL << ((XLEN) + -5)) +#define CSR_ITRIGGER_TYPE_OFFSET(XLEN) ((XLEN) + -4ULL) +#define CSR_ITRIGGER_TYPE_LENGTH 4ULL +#define CSR_ITRIGGER_TYPE(XLEN) (0xfULL * (1ULL << ((XLEN) + -4ULL))) +#define CSR_ITRIGGER_DMODE_OFFSET(XLEN) ((XLEN) + -5ULL) +#define CSR_ITRIGGER_DMODE_LENGTH 1ULL +#define CSR_ITRIGGER_DMODE(XLEN) (1ULL << ((XLEN) + -5ULL)) /* * If this bit is implemented, the hardware sets it when this * trigger matches. The trigger's user can set or clear it at any @@ -1507,66 +1518,66 @@ * trigger(s) matched. If the bit is not implemented, it is always 0 * and writing it has no effect. */ -#define CSR_ITRIGGER_HIT_OFFSET(XLEN) ((XLEN) + -6) -#define CSR_ITRIGGER_HIT_LENGTH 1 -#define CSR_ITRIGGER_HIT(XLEN) (1ULL << ((XLEN) + -6)) +#define CSR_ITRIGGER_HIT_OFFSET(XLEN) ((XLEN) + -6ULL) +#define CSR_ITRIGGER_HIT_LENGTH 1ULL +#define CSR_ITRIGGER_HIT(XLEN) (1ULL << ((XLEN) + -6ULL)) /* * When set, enable this trigger for interrupts that are taken from VS * mode. * This bit is hard-wired to 0 if the hart does not support * virtualization mode. */ -#define CSR_ITRIGGER_VS_OFFSET 0xc -#define CSR_ITRIGGER_VS_LENGTH 1 -#define CSR_ITRIGGER_VS 0x1000 +#define CSR_ITRIGGER_VS_OFFSET 0xcULL +#define CSR_ITRIGGER_VS_LENGTH 1ULL +#define CSR_ITRIGGER_VS 0x1000ULL /* * When set, enable this trigger for interrupts that are taken from VU * mode. * This bit is hard-wired to 0 if the hart does not support * virtualization mode. */ -#define CSR_ITRIGGER_VU_OFFSET 0xb -#define CSR_ITRIGGER_VU_LENGTH 1 -#define CSR_ITRIGGER_VU 0x800 +#define CSR_ITRIGGER_VU_OFFSET 0xbULL +#define CSR_ITRIGGER_VU_LENGTH 1ULL +#define CSR_ITRIGGER_VU 0x800ULL /* * When set, non-maskable interrupts cause this * trigger to fire if the trigger is enabled for the current mode. */ -#define CSR_ITRIGGER_NMI_OFFSET 0xa -#define CSR_ITRIGGER_NMI_LENGTH 1 -#define CSR_ITRIGGER_NMI 0x400 +#define CSR_ITRIGGER_NMI_OFFSET 0xaULL +#define CSR_ITRIGGER_NMI_LENGTH 1ULL +#define CSR_ITRIGGER_NMI 0x400ULL /* * When set, enable this trigger for interrupts that are taken from M * mode. */ -#define CSR_ITRIGGER_M_OFFSET 9 -#define CSR_ITRIGGER_M_LENGTH 1 -#define CSR_ITRIGGER_M 0x200 +#define CSR_ITRIGGER_M_OFFSET 9ULL +#define CSR_ITRIGGER_M_LENGTH 1ULL +#define CSR_ITRIGGER_M 0x200ULL /* * When set, enable this trigger for interrupts that are taken from S/HS * mode. * This bit is hard-wired to 0 if the hart does not support * S-mode. */ -#define CSR_ITRIGGER_S_OFFSET 7 -#define CSR_ITRIGGER_S_LENGTH 1 -#define CSR_ITRIGGER_S 0x80 +#define CSR_ITRIGGER_S_OFFSET 7ULL +#define CSR_ITRIGGER_S_LENGTH 1ULL +#define CSR_ITRIGGER_S 0x80ULL /* * When set, enable this trigger for interrupts that are taken from U * mode. * This bit is hard-wired to 0 if the hart does not support * U-mode. */ -#define CSR_ITRIGGER_U_OFFSET 6 -#define CSR_ITRIGGER_U_LENGTH 1 -#define CSR_ITRIGGER_U 0x40 +#define CSR_ITRIGGER_U_OFFSET 6ULL +#define CSR_ITRIGGER_U_LENGTH 1ULL +#define CSR_ITRIGGER_U 0x40ULL /* * The action to take when the trigger fires. The values are explained * in Table~\ref{tab:action}. */ -#define CSR_ITRIGGER_ACTION_OFFSET 0 -#define CSR_ITRIGGER_ACTION_LENGTH 6 -#define CSR_ITRIGGER_ACTION 0x3f +#define CSR_ITRIGGER_ACTION_OFFSET 0ULL +#define CSR_ITRIGGER_ACTION_LENGTH 6ULL +#define CSR_ITRIGGER_ACTION 0x3fULL /* * breakpoint: */ @@ -1596,12 +1607,12 @@ */ #define CSR_ITRIGGER_ACTION_EXTERNAL1 9 #define CSR_ETRIGGER 0x7a1 -#define CSR_ETRIGGER_TYPE_OFFSET(XLEN) ((XLEN) + -4) -#define CSR_ETRIGGER_TYPE_LENGTH 4 -#define CSR_ETRIGGER_TYPE(XLEN) (0xf * (1ULL << ((XLEN) + -4))) -#define CSR_ETRIGGER_DMODE_OFFSET(XLEN) ((XLEN) + -5) -#define CSR_ETRIGGER_DMODE_LENGTH 1 -#define CSR_ETRIGGER_DMODE(XLEN) (1ULL << ((XLEN) + -5)) +#define CSR_ETRIGGER_TYPE_OFFSET(XLEN) ((XLEN) + -4ULL) +#define CSR_ETRIGGER_TYPE_LENGTH 4ULL +#define CSR_ETRIGGER_TYPE(XLEN) (0xfULL * (1ULL << ((XLEN) + -4ULL))) +#define CSR_ETRIGGER_DMODE_OFFSET(XLEN) ((XLEN) + -5ULL) +#define CSR_ETRIGGER_DMODE_LENGTH 1ULL +#define CSR_ETRIGGER_DMODE(XLEN) (1ULL << ((XLEN) + -5ULL)) /* * If this bit is implemented, the hardware sets it when this * trigger matches. The trigger's user can set or clear it at any @@ -1609,59 +1620,59 @@ * trigger(s) matched. If the bit is not implemented, it is always 0 * and writing it has no effect. */ -#define CSR_ETRIGGER_HIT_OFFSET(XLEN) ((XLEN) + -6) -#define CSR_ETRIGGER_HIT_LENGTH 1 -#define CSR_ETRIGGER_HIT(XLEN) (1ULL << ((XLEN) + -6)) +#define CSR_ETRIGGER_HIT_OFFSET(XLEN) ((XLEN) + -6ULL) +#define CSR_ETRIGGER_HIT_LENGTH 1ULL +#define CSR_ETRIGGER_HIT(XLEN) (1ULL << ((XLEN) + -6ULL)) /* * When set, enable this trigger for exceptions that are taken from VS * mode. * This bit is hard-wired to 0 if the hart does not support * virtualization mode. */ -#define CSR_ETRIGGER_VS_OFFSET 0xc -#define CSR_ETRIGGER_VS_LENGTH 1 -#define CSR_ETRIGGER_VS 0x1000 +#define CSR_ETRIGGER_VS_OFFSET 0xcULL +#define CSR_ETRIGGER_VS_LENGTH 1ULL +#define CSR_ETRIGGER_VS 0x1000ULL /* * When set, enable this trigger for exceptions that are taken from VU * mode. * This bit is hard-wired to 0 if the hart does not support * virtualization mode. */ -#define CSR_ETRIGGER_VU_OFFSET 0xb -#define CSR_ETRIGGER_VU_LENGTH 1 -#define CSR_ETRIGGER_VU 0x800 +#define CSR_ETRIGGER_VU_OFFSET 0xbULL +#define CSR_ETRIGGER_VU_LENGTH 1ULL +#define CSR_ETRIGGER_VU 0x800ULL /* * When set, enable this trigger for exceptions that are taken from M * mode. */ -#define CSR_ETRIGGER_M_OFFSET 9 -#define CSR_ETRIGGER_M_LENGTH 1 -#define CSR_ETRIGGER_M 0x200 +#define CSR_ETRIGGER_M_OFFSET 9ULL +#define CSR_ETRIGGER_M_LENGTH 1ULL +#define CSR_ETRIGGER_M 0x200ULL /* * When set, enable this trigger for exceptions that are taken from S/HS * mode. * This bit is hard-wired to 0 if the hart does not support * S-mode. */ -#define CSR_ETRIGGER_S_OFFSET 7 -#define CSR_ETRIGGER_S_LENGTH 1 -#define CSR_ETRIGGER_S 0x80 +#define CSR_ETRIGGER_S_OFFSET 7ULL +#define CSR_ETRIGGER_S_LENGTH 1ULL +#define CSR_ETRIGGER_S 0x80ULL /* * When set, enable this trigger for exceptions that are taken from U * mode. * This bit is hard-wired to 0 if the hart does not support * U-mode. */ -#define CSR_ETRIGGER_U_OFFSET 6 -#define CSR_ETRIGGER_U_LENGTH 1 -#define CSR_ETRIGGER_U 0x40 +#define CSR_ETRIGGER_U_OFFSET 6ULL +#define CSR_ETRIGGER_U_LENGTH 1ULL +#define CSR_ETRIGGER_U 0x40ULL /* * The action to take when the trigger fires. The values are explained * in Table~\ref{tab:action}. */ -#define CSR_ETRIGGER_ACTION_OFFSET 0 -#define CSR_ETRIGGER_ACTION_LENGTH 6 -#define CSR_ETRIGGER_ACTION 0x3f +#define CSR_ETRIGGER_ACTION_OFFSET 0ULL +#define CSR_ETRIGGER_ACTION_LENGTH 6ULL +#define CSR_ETRIGGER_ACTION 0x3fULL /* * breakpoint: */ @@ -1691,12 +1702,12 @@ */ #define CSR_ETRIGGER_ACTION_EXTERNAL1 9 #define CSR_TMEXTTRIGGER 0x7a1 -#define CSR_TMEXTTRIGGER_TYPE_OFFSET(XLEN) ((XLEN) + -4) -#define CSR_TMEXTTRIGGER_TYPE_LENGTH 4 -#define CSR_TMEXTTRIGGER_TYPE(XLEN) (0xf * (1ULL << ((XLEN) + -4))) -#define CSR_TMEXTTRIGGER_DMODE_OFFSET(XLEN) ((XLEN) + -5) -#define CSR_TMEXTTRIGGER_DMODE_LENGTH 1 -#define CSR_TMEXTTRIGGER_DMODE(XLEN) (1ULL << ((XLEN) + -5)) +#define CSR_TMEXTTRIGGER_TYPE_OFFSET(XLEN) ((XLEN) + -4ULL) +#define CSR_TMEXTTRIGGER_TYPE_LENGTH 4ULL +#define CSR_TMEXTTRIGGER_TYPE(XLEN) (0xfULL * (1ULL << ((XLEN) + -4ULL))) +#define CSR_TMEXTTRIGGER_DMODE_OFFSET(XLEN) ((XLEN) + -5ULL) +#define CSR_TMEXTTRIGGER_DMODE_LENGTH 1ULL +#define CSR_TMEXTTRIGGER_DMODE(XLEN) (1ULL << ((XLEN) + -5ULL)) /* * If this bit is implemented, the hardware sets it when this * trigger matches. The trigger's user can set or clear it at any @@ -1704,30 +1715,30 @@ * trigger(s) matched. If the bit is not implemented, it is always 0 * and writing it has no effect. */ -#define CSR_TMEXTTRIGGER_HIT_OFFSET(XLEN) ((XLEN) + -6) -#define CSR_TMEXTTRIGGER_HIT_LENGTH 1 -#define CSR_TMEXTTRIGGER_HIT(XLEN) (1ULL << ((XLEN) + -6)) +#define CSR_TMEXTTRIGGER_HIT_OFFSET(XLEN) ((XLEN) + -6ULL) +#define CSR_TMEXTTRIGGER_HIT_LENGTH 1ULL +#define CSR_TMEXTTRIGGER_HIT(XLEN) (1ULL << ((XLEN) + -6ULL)) /* * This optional bit, when set, causes this trigger to fire whenever an attached * interrupt controller signals a trigger. */ -#define CSR_TMEXTTRIGGER_INTCTL_OFFSET 0x16 -#define CSR_TMEXTTRIGGER_INTCTL_LENGTH 1 -#define CSR_TMEXTTRIGGER_INTCTL 0x400000 +#define CSR_TMEXTTRIGGER_INTCTL_OFFSET 0x16ULL +#define CSR_TMEXTTRIGGER_INTCTL_LENGTH 1ULL +#define CSR_TMEXTTRIGGER_INTCTL 0x400000ULL /* * Selects any combination of up to 16 TM external trigger inputs * that cause this trigger to fire. */ -#define CSR_TMEXTTRIGGER_SELECT_OFFSET 6 -#define CSR_TMEXTTRIGGER_SELECT_LENGTH 0x10 -#define CSR_TMEXTTRIGGER_SELECT 0x3fffc0 +#define CSR_TMEXTTRIGGER_SELECT_OFFSET 6ULL +#define CSR_TMEXTTRIGGER_SELECT_LENGTH 0x10ULL +#define CSR_TMEXTTRIGGER_SELECT 0x3fffc0ULL /* * The action to take when the trigger fires. The values are explained * in Table~\ref{tab:action}. */ -#define CSR_TMEXTTRIGGER_ACTION_OFFSET 0 -#define CSR_TMEXTTRIGGER_ACTION_LENGTH 6 -#define CSR_TMEXTTRIGGER_ACTION 0x3f +#define CSR_TMEXTTRIGGER_ACTION_OFFSET 0ULL +#define CSR_TMEXTTRIGGER_ACTION_LENGTH 6ULL +#define CSR_TMEXTTRIGGER_ACTION 0x3fULL /* * breakpoint: */ @@ -1760,12 +1771,12 @@ /* * Data used together with \FcsrTextraThirtytwoMhselect. */ -#define CSR_TEXTRA32_MHVALUE_OFFSET 0x1a -#define CSR_TEXTRA32_MHVALUE_LENGTH 6 -#define CSR_TEXTRA32_MHVALUE 0xfc000000U -#define CSR_TEXTRA32_MHSELECT_OFFSET 0x17 -#define CSR_TEXTRA32_MHSELECT_LENGTH 3 -#define CSR_TEXTRA32_MHSELECT 0x3800000 +#define CSR_TEXTRA32_MHVALUE_OFFSET 0x1aULL +#define CSR_TEXTRA32_MHVALUE_LENGTH 6ULL +#define CSR_TEXTRA32_MHVALUE 0xfc000000ULL +#define CSR_TEXTRA32_MHSELECT_OFFSET 0x17ULL +#define CSR_TEXTRA32_MHSELECT_LENGTH 3ULL +#define CSR_TEXTRA32_MHSELECT 0x3800000ULL /* * ignore: Ignore \FcsrTextraThirtytwoMhvalue. */ @@ -1794,20 +1805,20 @@ * When the next most significant bit of this field is 1, it causes bits 15:8 * to be ignored in the comparison, when \FcsrTextraThirtytwoSselect=1. */ -#define CSR_TEXTRA32_SBYTEMASK_OFFSET 0x12 -#define CSR_TEXTRA32_SBYTEMASK_LENGTH 2 -#define CSR_TEXTRA32_SBYTEMASK 0xc0000 +#define CSR_TEXTRA32_SBYTEMASK_OFFSET 0x12ULL +#define CSR_TEXTRA32_SBYTEMASK_LENGTH 2ULL +#define CSR_TEXTRA32_SBYTEMASK 0xc0000ULL /* * Data used together with \FcsrTextraThirtytwoSselect. * * This field should be tied to 0 when S-mode is not supported. */ -#define CSR_TEXTRA32_SVALUE_OFFSET 2 -#define CSR_TEXTRA32_SVALUE_LENGTH 0x10 -#define CSR_TEXTRA32_SVALUE 0x3fffc -#define CSR_TEXTRA32_SSELECT_OFFSET 0 -#define CSR_TEXTRA32_SSELECT_LENGTH 2 -#define CSR_TEXTRA32_SSELECT 3 +#define CSR_TEXTRA32_SVALUE_OFFSET 2ULL +#define CSR_TEXTRA32_SVALUE_LENGTH 0x10ULL +#define CSR_TEXTRA32_SVALUE 0x3fffcULL +#define CSR_TEXTRA32_SSELECT_OFFSET 0ULL +#define CSR_TEXTRA32_SSELECT_LENGTH 2ULL +#define CSR_TEXTRA32_SSELECT 3ULL /* * ignore: Ignore \FcsrTextraThirtytwoSvalue. */ @@ -1833,11 +1844,11 @@ * This field should be tied to 0 when S-mode is not supported. */ #define CSR_TEXTRA64 0x7a3 -#define CSR_TEXTRA64_MHVALUE_OFFSET 0x33 -#define CSR_TEXTRA64_MHVALUE_LENGTH 0xd +#define CSR_TEXTRA64_MHVALUE_OFFSET 0x33ULL +#define CSR_TEXTRA64_MHVALUE_LENGTH 0xdULL #define CSR_TEXTRA64_MHVALUE 0xfff8000000000000ULL -#define CSR_TEXTRA64_MHSELECT_OFFSET 0x30 -#define CSR_TEXTRA64_MHSELECT_LENGTH 3 +#define CSR_TEXTRA64_MHSELECT_OFFSET 0x30ULL +#define CSR_TEXTRA64_MHSELECT_LENGTH 3ULL #define CSR_TEXTRA64_MHSELECT 0x7000000000000ULL /* * When the least significant bit of this field is 1, it causes bits 7:0 @@ -1847,19 +1858,19 @@ * fourth bit controls the comparison of bits 31:24, and * fifth bit controls the comparison of bits 33:32. */ -#define CSR_TEXTRA64_SBYTEMASK_OFFSET 0x24 -#define CSR_TEXTRA64_SBYTEMASK_LENGTH 5 +#define CSR_TEXTRA64_SBYTEMASK_OFFSET 0x24ULL +#define CSR_TEXTRA64_SBYTEMASK_LENGTH 5ULL #define CSR_TEXTRA64_SBYTEMASK 0x1f000000000ULL -#define CSR_TEXTRA64_SVALUE_OFFSET 2 -#define CSR_TEXTRA64_SVALUE_LENGTH 0x22 +#define CSR_TEXTRA64_SVALUE_OFFSET 2ULL +#define CSR_TEXTRA64_SVALUE_LENGTH 0x22ULL #define CSR_TEXTRA64_SVALUE 0xffffffffcULL -#define CSR_TEXTRA64_SSELECT_OFFSET 0 -#define CSR_TEXTRA64_SSELECT_LENGTH 2 -#define CSR_TEXTRA64_SSELECT 3 +#define CSR_TEXTRA64_SSELECT_OFFSET 0ULL +#define CSR_TEXTRA64_SSELECT_LENGTH 2ULL +#define CSR_TEXTRA64_SSELECT 3ULL #define DM_DMSTATUS 0x11 -#define DM_DMSTATUS_NDMRESETPENDING_OFFSET 0x18 -#define DM_DMSTATUS_NDMRESETPENDING_LENGTH 1 -#define DM_DMSTATUS_NDMRESETPENDING 0x1000000 +#define DM_DMSTATUS_NDMRESETPENDING_OFFSET 0x18ULL +#define DM_DMSTATUS_NDMRESETPENDING_LENGTH 1ULL +#define DM_DMSTATUS_NDMRESETPENDING 0x1000000ULL /* * false: Unimplemented, or \FdmDmcontrolNdmreset is zero and no ndmreset is currently * in progress. @@ -1869,9 +1880,9 @@ * true: \FdmDmcontrolNdmreset is currently nonzero, or there is an ndmreset in progress. */ #define DM_DMSTATUS_NDMRESETPENDING_TRUE 1 -#define DM_DMSTATUS_STICKYUNAVAIL_OFFSET 0x17 -#define DM_DMSTATUS_STICKYUNAVAIL_LENGTH 1 -#define DM_DMSTATUS_STICKYUNAVAIL 0x800000 +#define DM_DMSTATUS_STICKYUNAVAIL_OFFSET 0x17ULL +#define DM_DMSTATUS_STICKYUNAVAIL_LENGTH 1ULL +#define DM_DMSTATUS_STICKYUNAVAIL 0x800000ULL /* * current: The per-hart {\tt unavail} bits reflect the current state of the hart. */ @@ -1889,94 +1900,94 @@ * * This must be 1 when \FdmAbstractcsProgbufsize is 1. */ -#define DM_DMSTATUS_IMPEBREAK_OFFSET 0x16 -#define DM_DMSTATUS_IMPEBREAK_LENGTH 1 -#define DM_DMSTATUS_IMPEBREAK 0x400000 +#define DM_DMSTATUS_IMPEBREAK_OFFSET 0x16ULL +#define DM_DMSTATUS_IMPEBREAK_LENGTH 1ULL +#define DM_DMSTATUS_IMPEBREAK 0x400000ULL /* * This field is 1 when all currently selected harts have been reset * and reset has not been acknowledged for any of them. */ -#define DM_DMSTATUS_ALLHAVERESET_OFFSET 0x13 -#define DM_DMSTATUS_ALLHAVERESET_LENGTH 1 -#define DM_DMSTATUS_ALLHAVERESET 0x80000 +#define DM_DMSTATUS_ALLHAVERESET_OFFSET 0x13ULL +#define DM_DMSTATUS_ALLHAVERESET_LENGTH 1ULL +#define DM_DMSTATUS_ALLHAVERESET 0x80000ULL /* * This field is 1 when at least one currently selected hart has been * reset and reset has not been acknowledged for that hart. */ -#define DM_DMSTATUS_ANYHAVERESET_OFFSET 0x12 -#define DM_DMSTATUS_ANYHAVERESET_LENGTH 1 -#define DM_DMSTATUS_ANYHAVERESET 0x40000 +#define DM_DMSTATUS_ANYHAVERESET_OFFSET 0x12ULL +#define DM_DMSTATUS_ANYHAVERESET_LENGTH 1ULL +#define DM_DMSTATUS_ANYHAVERESET 0x40000ULL /* * This field is 1 when all currently selected harts have their * resume ack bit\index{resume ack bit} set. */ -#define DM_DMSTATUS_ALLRESUMEACK_OFFSET 0x11 -#define DM_DMSTATUS_ALLRESUMEACK_LENGTH 1 -#define DM_DMSTATUS_ALLRESUMEACK 0x20000 +#define DM_DMSTATUS_ALLRESUMEACK_OFFSET 0x11ULL +#define DM_DMSTATUS_ALLRESUMEACK_LENGTH 1ULL +#define DM_DMSTATUS_ALLRESUMEACK 0x20000ULL /* * This field is 1 when any currently selected hart has its * resume ack bit\index{resume ack bit} set. */ -#define DM_DMSTATUS_ANYRESUMEACK_OFFSET 0x10 -#define DM_DMSTATUS_ANYRESUMEACK_LENGTH 1 -#define DM_DMSTATUS_ANYRESUMEACK 0x10000 +#define DM_DMSTATUS_ANYRESUMEACK_OFFSET 0x10ULL +#define DM_DMSTATUS_ANYRESUMEACK_LENGTH 1ULL +#define DM_DMSTATUS_ANYRESUMEACK 0x10000ULL /* * This field is 1 when all currently selected harts do not exist in * this hardware platform. */ -#define DM_DMSTATUS_ALLNONEXISTENT_OFFSET 0xf -#define DM_DMSTATUS_ALLNONEXISTENT_LENGTH 1 -#define DM_DMSTATUS_ALLNONEXISTENT 0x8000 +#define DM_DMSTATUS_ALLNONEXISTENT_OFFSET 0xfULL +#define DM_DMSTATUS_ALLNONEXISTENT_LENGTH 1ULL +#define DM_DMSTATUS_ALLNONEXISTENT 0x8000ULL /* * This field is 1 when any currently selected hart does not exist in * this hardware platform. */ -#define DM_DMSTATUS_ANYNONEXISTENT_OFFSET 0xe -#define DM_DMSTATUS_ANYNONEXISTENT_LENGTH 1 -#define DM_DMSTATUS_ANYNONEXISTENT 0x4000 +#define DM_DMSTATUS_ANYNONEXISTENT_OFFSET 0xeULL +#define DM_DMSTATUS_ANYNONEXISTENT_LENGTH 1ULL +#define DM_DMSTATUS_ANYNONEXISTENT 0x4000ULL /* * This field is 1 when all currently selected harts are * unavailable, or (if \FdmDmstatusStickyunavail is 1) were * unavailable without that being acknowledged. */ -#define DM_DMSTATUS_ALLUNAVAIL_OFFSET 0xd -#define DM_DMSTATUS_ALLUNAVAIL_LENGTH 1 -#define DM_DMSTATUS_ALLUNAVAIL 0x2000 +#define DM_DMSTATUS_ALLUNAVAIL_OFFSET 0xdULL +#define DM_DMSTATUS_ALLUNAVAIL_LENGTH 1ULL +#define DM_DMSTATUS_ALLUNAVAIL 0x2000ULL /* * This field is 1 when any currently selected hart is unavailable, * or (if \FdmDmstatusStickyunavail is 1) was unavailable without * that being acknowledged. */ -#define DM_DMSTATUS_ANYUNAVAIL_OFFSET 0xc -#define DM_DMSTATUS_ANYUNAVAIL_LENGTH 1 -#define DM_DMSTATUS_ANYUNAVAIL 0x1000 +#define DM_DMSTATUS_ANYUNAVAIL_OFFSET 0xcULL +#define DM_DMSTATUS_ANYUNAVAIL_LENGTH 1ULL +#define DM_DMSTATUS_ANYUNAVAIL 0x1000ULL /* * This field is 1 when all currently selected harts are running. */ -#define DM_DMSTATUS_ALLRUNNING_OFFSET 0xb -#define DM_DMSTATUS_ALLRUNNING_LENGTH 1 -#define DM_DMSTATUS_ALLRUNNING 0x800 +#define DM_DMSTATUS_ALLRUNNING_OFFSET 0xbULL +#define DM_DMSTATUS_ALLRUNNING_LENGTH 1ULL +#define DM_DMSTATUS_ALLRUNNING 0x800ULL /* * This field is 1 when any currently selected hart is running. */ -#define DM_DMSTATUS_ANYRUNNING_OFFSET 0xa -#define DM_DMSTATUS_ANYRUNNING_LENGTH 1 -#define DM_DMSTATUS_ANYRUNNING 0x400 +#define DM_DMSTATUS_ANYRUNNING_OFFSET 0xaULL +#define DM_DMSTATUS_ANYRUNNING_LENGTH 1ULL +#define DM_DMSTATUS_ANYRUNNING 0x400ULL /* * This field is 1 when all currently selected harts are halted. */ -#define DM_DMSTATUS_ALLHALTED_OFFSET 9 -#define DM_DMSTATUS_ALLHALTED_LENGTH 1 -#define DM_DMSTATUS_ALLHALTED 0x200 +#define DM_DMSTATUS_ALLHALTED_OFFSET 9ULL +#define DM_DMSTATUS_ALLHALTED_LENGTH 1ULL +#define DM_DMSTATUS_ALLHALTED 0x200ULL /* * This field is 1 when any currently selected hart is halted. */ -#define DM_DMSTATUS_ANYHALTED_OFFSET 8 -#define DM_DMSTATUS_ANYHALTED_LENGTH 1 -#define DM_DMSTATUS_ANYHALTED 0x100 -#define DM_DMSTATUS_AUTHENTICATED_OFFSET 7 -#define DM_DMSTATUS_AUTHENTICATED_LENGTH 1 -#define DM_DMSTATUS_AUTHENTICATED 0x80 +#define DM_DMSTATUS_ANYHALTED_OFFSET 8ULL +#define DM_DMSTATUS_ANYHALTED_LENGTH 1ULL +#define DM_DMSTATUS_ANYHALTED 0x100ULL +#define DM_DMSTATUS_AUTHENTICATED_OFFSET 7ULL +#define DM_DMSTATUS_AUTHENTICATED_LENGTH 1ULL +#define DM_DMSTATUS_AUTHENTICATED 0x80ULL /* * false: Authentication is required before using the DM. */ @@ -1989,9 +2000,9 @@ * On components that don't implement authentication, this bit must be * preset as 1. */ -#define DM_DMSTATUS_AUTHBUSY_OFFSET 6 -#define DM_DMSTATUS_AUTHBUSY_LENGTH 1 -#define DM_DMSTATUS_AUTHBUSY 0x40 +#define DM_DMSTATUS_AUTHBUSY_OFFSET 6ULL +#define DM_DMSTATUS_AUTHBUSY_LENGTH 1ULL +#define DM_DMSTATUS_AUTHBUSY 0x40ULL /* * ready: The authentication module is ready to process the next * read/write to \RdmAuthdata. @@ -2011,12 +2022,12 @@ * controllable by the \FdmDmcontrolSetresethaltreq and \FdmDmcontrolClrresethaltreq bits. * 0 otherwise. */ -#define DM_DMSTATUS_HASRESETHALTREQ_OFFSET 5 -#define DM_DMSTATUS_HASRESETHALTREQ_LENGTH 1 -#define DM_DMSTATUS_HASRESETHALTREQ 0x20 -#define DM_DMSTATUS_CONFSTRPTRVALID_OFFSET 4 -#define DM_DMSTATUS_CONFSTRPTRVALID_LENGTH 1 -#define DM_DMSTATUS_CONFSTRPTRVALID 0x10 +#define DM_DMSTATUS_HASRESETHALTREQ_OFFSET 5ULL +#define DM_DMSTATUS_HASRESETHALTREQ_LENGTH 1ULL +#define DM_DMSTATUS_HASRESETHALTREQ 0x20ULL +#define DM_DMSTATUS_CONFSTRPTRVALID_OFFSET 4ULL +#define DM_DMSTATUS_CONFSTRPTRVALID_LENGTH 1ULL +#define DM_DMSTATUS_CONFSTRPTRVALID 0x10ULL /* * invalid: \RdmConfstrptrZero--\RdmConfstrptrThree hold information which * is not relevant to the configuration structure. @@ -2027,9 +2038,9 @@ * configuration structure. */ #define DM_DMSTATUS_CONFSTRPTRVALID_VALID 1 -#define DM_DMSTATUS_VERSION_OFFSET 0 -#define DM_DMSTATUS_VERSION_LENGTH 4 -#define DM_DMSTATUS_VERSION 0xf +#define DM_DMSTATUS_VERSION_OFFSET 0ULL +#define DM_DMSTATUS_VERSION_LENGTH 4ULL +#define DM_DMSTATUS_VERSION 0xfULL /* * none: There is no Debug Module present. */ @@ -2065,9 +2076,9 @@ * * Writes apply to the new value of \Fhartsel and \FdmDmcontrolHasel. */ -#define DM_DMCONTROL_HALTREQ_OFFSET 0x1f -#define DM_DMCONTROL_HALTREQ_LENGTH 1 -#define DM_DMCONTROL_HALTREQ 0x80000000U +#define DM_DMCONTROL_HALTREQ_OFFSET 0x1fULL +#define DM_DMCONTROL_HALTREQ_LENGTH 1ULL +#define DM_DMCONTROL_HALTREQ 0x80000000ULL /* * Writing 1 causes the currently selected harts to resume once, if * they are halted when the write occurs. It also clears the resume @@ -2077,9 +2088,9 @@ * * Writes apply to the new value of \Fhartsel and \FdmDmcontrolHasel. */ -#define DM_DMCONTROL_RESUMEREQ_OFFSET 0x1e -#define DM_DMCONTROL_RESUMEREQ_LENGTH 1 -#define DM_DMCONTROL_RESUMEREQ 0x40000000 +#define DM_DMCONTROL_RESUMEREQ_OFFSET 0x1eULL +#define DM_DMCONTROL_RESUMEREQ_LENGTH 1ULL +#define DM_DMCONTROL_RESUMEREQ 0x40000000ULL /* * This optional field writes the reset bit for all the currently * selected harts. To perform a reset the debugger writes 1, and then @@ -2094,12 +2105,12 @@ * * Writes apply to the new value of \Fhartsel and \FdmDmcontrolHasel. */ -#define DM_DMCONTROL_HARTRESET_OFFSET 0x1d -#define DM_DMCONTROL_HARTRESET_LENGTH 1 -#define DM_DMCONTROL_HARTRESET 0x20000000 -#define DM_DMCONTROL_ACKHAVERESET_OFFSET 0x1c -#define DM_DMCONTROL_ACKHAVERESET_LENGTH 1 -#define DM_DMCONTROL_ACKHAVERESET 0x10000000 +#define DM_DMCONTROL_HARTRESET_OFFSET 0x1dULL +#define DM_DMCONTROL_HARTRESET_LENGTH 1ULL +#define DM_DMCONTROL_HARTRESET 0x20000000ULL +#define DM_DMCONTROL_ACKHAVERESET_OFFSET 0x1cULL +#define DM_DMCONTROL_ACKHAVERESET_LENGTH 1ULL +#define DM_DMCONTROL_ACKHAVERESET 0x10000000ULL /* * nop: No effect. */ @@ -2111,9 +2122,9 @@ /* * Writes apply to the new value of \Fhartsel and \FdmDmcontrolHasel. */ -#define DM_DMCONTROL_ACKUNAVAIL_OFFSET 0x1b -#define DM_DMCONTROL_ACKUNAVAIL_LENGTH 1 -#define DM_DMCONTROL_ACKUNAVAIL 0x8000000 +#define DM_DMCONTROL_ACKUNAVAIL_OFFSET 0x1bULL +#define DM_DMCONTROL_ACKUNAVAIL_LENGTH 1ULL +#define DM_DMCONTROL_ACKUNAVAIL 0x8000000ULL /* * nop: No effect. */ @@ -2128,9 +2139,9 @@ /* * Selects the definition of currently selected harts. */ -#define DM_DMCONTROL_HASEL_OFFSET 0x1a -#define DM_DMCONTROL_HASEL_LENGTH 1 -#define DM_DMCONTROL_HASEL 0x4000000 +#define DM_DMCONTROL_HASEL_OFFSET 0x1aULL +#define DM_DMCONTROL_HASEL_LENGTH 1ULL +#define DM_DMCONTROL_HASEL 0x4000000ULL /* * single: There is a single currently selected hart, that is selected by \Fhartsel. */ @@ -2151,16 +2162,16 @@ * The low 10 bits of \Fhartsel: the DM-specific index of the hart to * select. This hart is always part of the currently selected harts. */ -#define DM_DMCONTROL_HARTSELLO_OFFSET 0x10 -#define DM_DMCONTROL_HARTSELLO_LENGTH 0xa -#define DM_DMCONTROL_HARTSELLO 0x3ff0000 +#define DM_DMCONTROL_HARTSELLO_OFFSET 0x10ULL +#define DM_DMCONTROL_HARTSELLO_LENGTH 0xaULL +#define DM_DMCONTROL_HARTSELLO 0x3ff0000ULL /* * The high 10 bits of \Fhartsel: the DM-specific index of the hart to * select. This hart is always part of the currently selected harts. */ -#define DM_DMCONTROL_HARTSELHI_OFFSET 6 -#define DM_DMCONTROL_HARTSELHI_LENGTH 0xa -#define DM_DMCONTROL_HARTSELHI 0xffc0 +#define DM_DMCONTROL_HARTSELHI_OFFSET 6ULL +#define DM_DMCONTROL_HARTSELHI_LENGTH 0xaULL +#define DM_DMCONTROL_HARTSELHI 0xffc0ULL /* * This optional field sets \Fkeepalive for all currently selected * harts, unless \FdmDmcontrolClrkeepalive is simultaneously set to @@ -2168,18 +2179,18 @@ * * Writes apply to the new value of \Fhartsel and \FdmDmcontrolHasel. */ -#define DM_DMCONTROL_SETKEEPALIVE_OFFSET 5 -#define DM_DMCONTROL_SETKEEPALIVE_LENGTH 1 -#define DM_DMCONTROL_SETKEEPALIVE 0x20 +#define DM_DMCONTROL_SETKEEPALIVE_OFFSET 5ULL +#define DM_DMCONTROL_SETKEEPALIVE_LENGTH 1ULL +#define DM_DMCONTROL_SETKEEPALIVE 0x20ULL /* * This optional field clears \Fkeepalive for all currently selected * harts. * * Writes apply to the new value of \Fhartsel and \FdmDmcontrolHasel. */ -#define DM_DMCONTROL_CLRKEEPALIVE_OFFSET 4 -#define DM_DMCONTROL_CLRKEEPALIVE_LENGTH 1 -#define DM_DMCONTROL_CLRKEEPALIVE 0x10 +#define DM_DMCONTROL_CLRKEEPALIVE_OFFSET 4ULL +#define DM_DMCONTROL_CLRKEEPALIVE_LENGTH 1ULL +#define DM_DMCONTROL_CLRKEEPALIVE 0x10ULL /* * This optional field writes the halt-on-reset request bit for all * currently selected harts, unless \FdmDmcontrolClrresethaltreq is @@ -2192,18 +2203,18 @@ * * If \FdmDmstatusHasresethaltreq is 0, this field is not implemented. */ -#define DM_DMCONTROL_SETRESETHALTREQ_OFFSET 3 -#define DM_DMCONTROL_SETRESETHALTREQ_LENGTH 1 -#define DM_DMCONTROL_SETRESETHALTREQ 8 +#define DM_DMCONTROL_SETRESETHALTREQ_OFFSET 3ULL +#define DM_DMCONTROL_SETRESETHALTREQ_LENGTH 1ULL +#define DM_DMCONTROL_SETRESETHALTREQ 8ULL /* * This optional field clears the halt-on-reset request bit for all * currently selected harts. * * Writes apply to the new value of \Fhartsel and \FdmDmcontrolHasel. */ -#define DM_DMCONTROL_CLRRESETHALTREQ_OFFSET 2 -#define DM_DMCONTROL_CLRRESETHALTREQ_LENGTH 1 -#define DM_DMCONTROL_CLRRESETHALTREQ 4 +#define DM_DMCONTROL_CLRRESETHALTREQ_OFFSET 2ULL +#define DM_DMCONTROL_CLRRESETHALTREQ_LENGTH 1ULL +#define DM_DMCONTROL_CLRRESETHALTREQ 4ULL /* * This bit controls the reset signal from the DM to the rest of the * hardware platform. The signal should reset every part of the hardware platform, including @@ -2213,9 +2224,9 @@ * and then writes 0 * to deassert the reset. */ -#define DM_DMCONTROL_NDMRESET_OFFSET 1 -#define DM_DMCONTROL_NDMRESET_LENGTH 1 -#define DM_DMCONTROL_NDMRESET 2 +#define DM_DMCONTROL_NDMRESET_OFFSET 1ULL +#define DM_DMCONTROL_NDMRESET_LENGTH 1ULL +#define DM_DMCONTROL_NDMRESET 2ULL /* * This bit serves as a reset signal for the Debug Module itself. * After changing the value of this bit, the debugger must poll @@ -2225,9 +2236,9 @@ * take an arbitrarily long time to complete activation or deactivation and will * indicate completion by setting \FdmDmcontrolDmactive to the requested value. */ -#define DM_DMCONTROL_DMACTIVE_OFFSET 0 -#define DM_DMCONTROL_DMACTIVE_LENGTH 1 -#define DM_DMCONTROL_DMACTIVE 1 +#define DM_DMCONTROL_DMACTIVE_OFFSET 0ULL +#define DM_DMCONTROL_DMACTIVE_LENGTH 1ULL +#define DM_DMCONTROL_DMACTIVE 1ULL /* * inactive: The module's state, including authentication mechanism, * takes its reset values (the \FdmDmcontrolDmactive bit is the only bit which can @@ -2259,12 +2270,12 @@ * The debugger can make no assumptions about the contents of these * registers between commands. */ -#define DM_HARTINFO_NSCRATCH_OFFSET 0x14 -#define DM_HARTINFO_NSCRATCH_LENGTH 4 -#define DM_HARTINFO_NSCRATCH 0xf00000 -#define DM_HARTINFO_DATAACCESS_OFFSET 0x10 -#define DM_HARTINFO_DATAACCESS_LENGTH 1 -#define DM_HARTINFO_DATAACCESS 0x10000 +#define DM_HARTINFO_NSCRATCH_OFFSET 0x14ULL +#define DM_HARTINFO_NSCRATCH_LENGTH 4ULL +#define DM_HARTINFO_NSCRATCH 0xf00000ULL +#define DM_HARTINFO_DATAACCESS_OFFSET 0x10ULL +#define DM_HARTINFO_DATAACCESS_LENGTH 1ULL +#define DM_HARTINFO_DATAACCESS 0x10000ULL /* * csr: The {\tt data} registers are shadowed in the hart by CSRs. * Each CSR is DXLEN bits in size, and corresponds @@ -2283,15 +2294,12 @@ * If \FdmHartinfoDataaccess is 1: Number of 32-bit words in the memory map * dedicated to shadowing the {\tt data} registers. * - * If this value is non-zero, then the {tt data} registers must be - * traditional registers and not MRs. - * * Since there are at most 12 {\tt data} registers, the value in this * register must be 12 or smaller. */ -#define DM_HARTINFO_DATASIZE_OFFSET 0xc -#define DM_HARTINFO_DATASIZE_LENGTH 4 -#define DM_HARTINFO_DATASIZE 0xf000 +#define DM_HARTINFO_DATASIZE_OFFSET 0xcULL +#define DM_HARTINFO_DATASIZE_LENGTH 4ULL +#define DM_HARTINFO_DATASIZE 0xf000ULL /* * If \FdmHartinfoDataaccess is 0: The number of the first CSR dedicated to * shadowing the {\tt data} registers. @@ -2301,32 +2309,32 @@ * range of -2048 to 2047, easily addressed with a load or store using * \Xzero as the address register. */ -#define DM_HARTINFO_DATAADDR_OFFSET 0 -#define DM_HARTINFO_DATAADDR_LENGTH 0xc -#define DM_HARTINFO_DATAADDR 0xfff +#define DM_HARTINFO_DATAADDR_OFFSET 0ULL +#define DM_HARTINFO_DATAADDR_LENGTH 0xcULL +#define DM_HARTINFO_DATAADDR 0xfffULL #define DM_HAWINDOWSEL 0x14 /* * The high bits of this field may be tied to 0, depending on how large * the array mask register is. E.g.\ on a hardware platform with 48 harts only bit 0 * of this field may actually be writable. */ -#define DM_HAWINDOWSEL_HAWINDOWSEL_OFFSET 0 -#define DM_HAWINDOWSEL_HAWINDOWSEL_LENGTH 0xf -#define DM_HAWINDOWSEL_HAWINDOWSEL 0x7fff +#define DM_HAWINDOWSEL_HAWINDOWSEL_OFFSET 0ULL +#define DM_HAWINDOWSEL_HAWINDOWSEL_LENGTH 0xfULL +#define DM_HAWINDOWSEL_HAWINDOWSEL 0x7fffULL #define DM_HAWINDOW 0x15 -#define DM_HAWINDOW_MASKDATA_OFFSET 0 -#define DM_HAWINDOW_MASKDATA_LENGTH 0x20 -#define DM_HAWINDOW_MASKDATA 0xffffffffU +#define DM_HAWINDOW_MASKDATA_OFFSET 0ULL +#define DM_HAWINDOW_MASKDATA_LENGTH 0x20ULL +#define DM_HAWINDOW_MASKDATA 0xffffffffULL #define DM_ABSTRACTCS 0x16 /* * Size of the Program Buffer, in 32-bit words. Valid sizes are 0 - 16. */ -#define DM_ABSTRACTCS_PROGBUFSIZE_OFFSET 0x18 -#define DM_ABSTRACTCS_PROGBUFSIZE_LENGTH 5 -#define DM_ABSTRACTCS_PROGBUFSIZE 0x1f000000 -#define DM_ABSTRACTCS_BUSY_OFFSET 0xc -#define DM_ABSTRACTCS_BUSY_LENGTH 1 -#define DM_ABSTRACTCS_BUSY 0x1000 +#define DM_ABSTRACTCS_PROGBUFSIZE_OFFSET 0x18ULL +#define DM_ABSTRACTCS_PROGBUFSIZE_LENGTH 5ULL +#define DM_ABSTRACTCS_PROGBUFSIZE 0x1f000000ULL +#define DM_ABSTRACTCS_BUSY_OFFSET 0xcULL +#define DM_ABSTRACTCS_BUSY_LENGTH 1ULL +#define DM_ABSTRACTCS_BUSY 0x1000ULL /* * ready: There is no abstract command currently being executed. */ @@ -2347,9 +2355,9 @@ * permission checks (e.g. PMP restrictions are ignored). The * details of the latter are implementation-specific. */ -#define DM_ABSTRACTCS_RELAXEDPRIV_OFFSET 0xb -#define DM_ABSTRACTCS_RELAXEDPRIV_LENGTH 1 -#define DM_ABSTRACTCS_RELAXEDPRIV 0x800 +#define DM_ABSTRACTCS_RELAXEDPRIV_OFFSET 0xbULL +#define DM_ABSTRACTCS_RELAXEDPRIV_LENGTH 1ULL +#define DM_ABSTRACTCS_RELAXEDPRIV 0x800ULL /* * full checks: Full permission checks apply. */ @@ -2365,9 +2373,9 @@ * * This field only contains a valid value if \FdmAbstractcsBusy is 0. */ -#define DM_ABSTRACTCS_CMDERR_OFFSET 8 -#define DM_ABSTRACTCS_CMDERR_LENGTH 3 -#define DM_ABSTRACTCS_CMDERR 0x700 +#define DM_ABSTRACTCS_CMDERR_OFFSET 8ULL +#define DM_ABSTRACTCS_CMDERR_LENGTH 3ULL +#define DM_ABSTRACTCS_CMDERR 0x700ULL /* * none: No error. */ @@ -2413,24 +2421,24 @@ * Number of {\tt data} registers that are implemented as part of the * abstract command interface. Valid sizes are 1 -- 12. */ -#define DM_ABSTRACTCS_DATACOUNT_OFFSET 0 -#define DM_ABSTRACTCS_DATACOUNT_LENGTH 4 -#define DM_ABSTRACTCS_DATACOUNT 0xf +#define DM_ABSTRACTCS_DATACOUNT_OFFSET 0ULL +#define DM_ABSTRACTCS_DATACOUNT_LENGTH 4ULL +#define DM_ABSTRACTCS_DATACOUNT 0xfULL #define DM_COMMAND 0x17 /* * The type determines the overall functionality of this * abstract command. */ -#define DM_COMMAND_CMDTYPE_OFFSET 0x18 -#define DM_COMMAND_CMDTYPE_LENGTH 8 -#define DM_COMMAND_CMDTYPE 0xff000000U +#define DM_COMMAND_CMDTYPE_OFFSET 0x18ULL +#define DM_COMMAND_CMDTYPE_LENGTH 8ULL +#define DM_COMMAND_CMDTYPE 0xff000000ULL /* * This field is interpreted in a command-specific manner, * described for each abstract command. */ -#define DM_COMMAND_CONTROL_OFFSET 0 -#define DM_COMMAND_CONTROL_LENGTH 0x18 -#define DM_COMMAND_CONTROL 0xffffff +#define DM_COMMAND_CONTROL_OFFSET 0ULL +#define DM_COMMAND_CONTROL_LENGTH 0x18ULL +#define DM_COMMAND_CONTROL 0xffffffULL #define DM_ABSTRACTAUTO 0x18 /* * When a bit in this field is 1, read or write accesses to the @@ -2438,42 +2446,42 @@ * current value in \RdmCommand was written there again after the * access to {\tt progbuf} completes. */ -#define DM_ABSTRACTAUTO_AUTOEXECPROGBUF_OFFSET 0x10 -#define DM_ABSTRACTAUTO_AUTOEXECPROGBUF_LENGTH 0x10 -#define DM_ABSTRACTAUTO_AUTOEXECPROGBUF 0xffff0000U +#define DM_ABSTRACTAUTO_AUTOEXECPROGBUF_OFFSET 0x10ULL +#define DM_ABSTRACTAUTO_AUTOEXECPROGBUF_LENGTH 0x10ULL +#define DM_ABSTRACTAUTO_AUTOEXECPROGBUF 0xffff0000ULL /* * When a bit in this field is 1, read or write accesses to the * corresponding {\tt data} word cause the DM to act as if the current * value in \RdmCommand was written there again after the * access to {\tt data} completes. */ -#define DM_ABSTRACTAUTO_AUTOEXECDATA_OFFSET 0 -#define DM_ABSTRACTAUTO_AUTOEXECDATA_LENGTH 0xc -#define DM_ABSTRACTAUTO_AUTOEXECDATA 0xfff +#define DM_ABSTRACTAUTO_AUTOEXECDATA_OFFSET 0ULL +#define DM_ABSTRACTAUTO_AUTOEXECDATA_LENGTH 0xcULL +#define DM_ABSTRACTAUTO_AUTOEXECDATA 0xfffULL #define DM_CONFSTRPTR0 0x19 -#define DM_CONFSTRPTR0_ADDR_OFFSET 0 -#define DM_CONFSTRPTR0_ADDR_LENGTH 0x20 -#define DM_CONFSTRPTR0_ADDR 0xffffffffU +#define DM_CONFSTRPTR0_ADDR_OFFSET 0ULL +#define DM_CONFSTRPTR0_ADDR_LENGTH 0x20ULL +#define DM_CONFSTRPTR0_ADDR 0xffffffffULL #define DM_CONFSTRPTR1 0x1a -#define DM_CONFSTRPTR1_ADDR_OFFSET 0 -#define DM_CONFSTRPTR1_ADDR_LENGTH 0x20 -#define DM_CONFSTRPTR1_ADDR 0xffffffffU +#define DM_CONFSTRPTR1_ADDR_OFFSET 0ULL +#define DM_CONFSTRPTR1_ADDR_LENGTH 0x20ULL +#define DM_CONFSTRPTR1_ADDR 0xffffffffULL #define DM_CONFSTRPTR2 0x1b -#define DM_CONFSTRPTR2_ADDR_OFFSET 0 -#define DM_CONFSTRPTR2_ADDR_LENGTH 0x20 -#define DM_CONFSTRPTR2_ADDR 0xffffffffU +#define DM_CONFSTRPTR2_ADDR_OFFSET 0ULL +#define DM_CONFSTRPTR2_ADDR_LENGTH 0x20ULL +#define DM_CONFSTRPTR2_ADDR 0xffffffffULL #define DM_CONFSTRPTR3 0x1c -#define DM_CONFSTRPTR3_ADDR_OFFSET 0 -#define DM_CONFSTRPTR3_ADDR_LENGTH 0x20 -#define DM_CONFSTRPTR3_ADDR 0xffffffffU +#define DM_CONFSTRPTR3_ADDR_OFFSET 0ULL +#define DM_CONFSTRPTR3_ADDR_LENGTH 0x20ULL +#define DM_CONFSTRPTR3_ADDR 0xffffffffULL #define DM_NEXTDM 0x1d -#define DM_NEXTDM_ADDR_OFFSET 0 -#define DM_NEXTDM_ADDR_LENGTH 0x20 -#define DM_NEXTDM_ADDR 0xffffffffU +#define DM_NEXTDM_ADDR_OFFSET 0ULL +#define DM_NEXTDM_ADDR_LENGTH 0x20ULL +#define DM_NEXTDM_ADDR 0xffffffffULL #define DM_DATA0 0x04 -#define DM_DATA0_DATA_OFFSET 0 -#define DM_DATA0_DATA_LENGTH 0x20 -#define DM_DATA0_DATA 0xffffffffU +#define DM_DATA0_DATA_OFFSET 0ULL +#define DM_DATA0_DATA_LENGTH 0x20ULL +#define DM_DATA0_DATA 0xffffffffULL #define DM_DATA1 0x05 #define DM_DATA2 0x06 #define DM_DATA3 0x07 @@ -2486,9 +2494,9 @@ #define DM_DATA10 0x0e #define DM_DATA11 0x0f #define DM_PROGBUF0 0x20 -#define DM_PROGBUF0_DATA_OFFSET 0 -#define DM_PROGBUF0_DATA_LENGTH 0x20 -#define DM_PROGBUF0_DATA 0xffffffffU +#define DM_PROGBUF0_DATA_OFFSET 0ULL +#define DM_PROGBUF0_DATA_LENGTH 0x20ULL +#define DM_PROGBUF0_DATA 0xffffffffULL #define DM_PROGBUF1 0x21 #define DM_PROGBUF2 0x22 #define DM_PROGBUF3 0x23 @@ -2505,13 +2513,13 @@ #define DM_PROGBUF14 0x2e #define DM_PROGBUF15 0x2f #define DM_AUTHDATA 0x30 -#define DM_AUTHDATA_DATA_OFFSET 0 -#define DM_AUTHDATA_DATA_LENGTH 0x20 -#define DM_AUTHDATA_DATA 0xffffffffU +#define DM_AUTHDATA_DATA_OFFSET 0ULL +#define DM_AUTHDATA_DATA_LENGTH 0x20ULL +#define DM_AUTHDATA_DATA 0xffffffffULL #define DM_DMCS2 0x32 -#define DM_DMCS2_GROUPTYPE_OFFSET 0xb -#define DM_DMCS2_GROUPTYPE_LENGTH 1 -#define DM_DMCS2_GROUPTYPE 0x800 +#define DM_DMCS2_GROUPTYPE_OFFSET 0xbULL +#define DM_DMCS2_GROUPTYPE_LENGTH 1ULL +#define DM_DMCS2_GROUPTYPE 0x800ULL /* * halt: The remaining fields in this register configure halt groups. */ @@ -2526,9 +2534,9 @@ * If a non-existent trigger value is written here, the hardware will * change it to a valid one or 0 if no DM external triggers exist. */ -#define DM_DMCS2_DMEXTTRIGGER_OFFSET 7 -#define DM_DMCS2_DMEXTTRIGGER_LENGTH 4 -#define DM_DMCS2_DMEXTTRIGGER 0x780 +#define DM_DMCS2_DMEXTTRIGGER_OFFSET 7ULL +#define DM_DMCS2_DMEXTTRIGGER_LENGTH 4ULL +#define DM_DMCS2_DMEXTTRIGGER 0x780ULL /* * When \FdmDmcsTwoHgselect is 0, contains the group of the hart * specified by \Fhartsel. @@ -2546,9 +2554,9 @@ * * If groups aren't implemented, then this entire field is 0. */ -#define DM_DMCS2_GROUP_OFFSET 2 -#define DM_DMCS2_GROUP_LENGTH 5 -#define DM_DMCS2_GROUP 0x7c +#define DM_DMCS2_GROUP_OFFSET 2ULL +#define DM_DMCS2_GROUP_LENGTH 5ULL +#define DM_DMCS2_GROUP 0x7cULL /* * When 1 is written and \FdmDmcsTwoHgselect is 0, for every selected * hart the DM will change its group to the value written to \FdmDmcsTwoGroup, @@ -2564,12 +2572,12 @@ * * Writing 0 has no effect. */ -#define DM_DMCS2_HGWRITE_OFFSET 1 -#define DM_DMCS2_HGWRITE_LENGTH 1 -#define DM_DMCS2_HGWRITE 2 -#define DM_DMCS2_HGSELECT_OFFSET 0 -#define DM_DMCS2_HGSELECT_LENGTH 1 -#define DM_DMCS2_HGSELECT 1 +#define DM_DMCS2_HGWRITE_OFFSET 1ULL +#define DM_DMCS2_HGWRITE_LENGTH 1ULL +#define DM_DMCS2_HGWRITE 2ULL +#define DM_DMCS2_HGSELECT_OFFSET 0ULL +#define DM_DMCS2_HGSELECT_LENGTH 1ULL +#define DM_DMCS2_HGSELECT 1ULL /* * harts: Operate on harts. */ @@ -2582,25 +2590,25 @@ * If there are no DM external triggers, this field must be tied to 0. */ #define DM_HALTSUM0 0x40 -#define DM_HALTSUM0_HALTSUM0_OFFSET 0 -#define DM_HALTSUM0_HALTSUM0_LENGTH 0x20 -#define DM_HALTSUM0_HALTSUM0 0xffffffffU +#define DM_HALTSUM0_HALTSUM0_OFFSET 0ULL +#define DM_HALTSUM0_HALTSUM0_LENGTH 0x20ULL +#define DM_HALTSUM0_HALTSUM0 0xffffffffULL #define DM_HALTSUM1 0x13 -#define DM_HALTSUM1_HALTSUM1_OFFSET 0 -#define DM_HALTSUM1_HALTSUM1_LENGTH 0x20 -#define DM_HALTSUM1_HALTSUM1 0xffffffffU +#define DM_HALTSUM1_HALTSUM1_OFFSET 0ULL +#define DM_HALTSUM1_HALTSUM1_LENGTH 0x20ULL +#define DM_HALTSUM1_HALTSUM1 0xffffffffULL #define DM_HALTSUM2 0x34 -#define DM_HALTSUM2_HALTSUM2_OFFSET 0 -#define DM_HALTSUM2_HALTSUM2_LENGTH 0x20 -#define DM_HALTSUM2_HALTSUM2 0xffffffffU +#define DM_HALTSUM2_HALTSUM2_OFFSET 0ULL +#define DM_HALTSUM2_HALTSUM2_LENGTH 0x20ULL +#define DM_HALTSUM2_HALTSUM2 0xffffffffULL #define DM_HALTSUM3 0x35 -#define DM_HALTSUM3_HALTSUM3_OFFSET 0 -#define DM_HALTSUM3_HALTSUM3_LENGTH 0x20 -#define DM_HALTSUM3_HALTSUM3 0xffffffffU +#define DM_HALTSUM3_HALTSUM3_OFFSET 0ULL +#define DM_HALTSUM3_HALTSUM3_LENGTH 0x20ULL +#define DM_HALTSUM3_HALTSUM3 0xffffffffULL #define DM_SBCS 0x38 -#define DM_SBCS_SBVERSION_OFFSET 0x1d -#define DM_SBCS_SBVERSION_LENGTH 3 -#define DM_SBCS_SBVERSION 0xe0000000U +#define DM_SBCS_SBVERSION_OFFSET 0x1dULL +#define DM_SBCS_SBVERSION_LENGTH 3ULL +#define DM_SBCS_SBVERSION 0xe0000000ULL /* * legacy: The System Bus interface conforms to mainline drafts of this * spec older than 1 January, 2018. @@ -2622,9 +2630,9 @@ * While this field is set, no more system bus accesses can be * initiated by the Debug Module. */ -#define DM_SBCS_SBBUSYERROR_OFFSET 0x16 -#define DM_SBCS_SBBUSYERROR_LENGTH 1 -#define DM_SBCS_SBBUSYERROR 0x400000 +#define DM_SBCS_SBBUSYERROR_OFFSET 0x16ULL +#define DM_SBCS_SBBUSYERROR_LENGTH 1ULL +#define DM_SBCS_SBBUSYERROR 0x400000ULL /* * When 1, indicates the system bus manager is busy. (Whether the * system bus itself is busy is related, but not the same thing.) This @@ -2635,22 +2643,22 @@ * behavior. A debugger must not write to \RdmSbcs until it reads * \FdmSbcsSbbusy as 0. */ -#define DM_SBCS_SBBUSY_OFFSET 0x15 -#define DM_SBCS_SBBUSY_LENGTH 1 -#define DM_SBCS_SBBUSY 0x200000 +#define DM_SBCS_SBBUSY_OFFSET 0x15ULL +#define DM_SBCS_SBBUSY_LENGTH 1ULL +#define DM_SBCS_SBBUSY 0x200000ULL /* * When 1, every write to \RdmSbaddressZero automatically triggers a * system bus read at the new address. */ -#define DM_SBCS_SBREADONADDR_OFFSET 0x14 -#define DM_SBCS_SBREADONADDR_LENGTH 1 -#define DM_SBCS_SBREADONADDR 0x100000 +#define DM_SBCS_SBREADONADDR_OFFSET 0x14ULL +#define DM_SBCS_SBREADONADDR_LENGTH 1ULL +#define DM_SBCS_SBREADONADDR 0x100000ULL /* * Select the access size to use for system bus accesses. */ -#define DM_SBCS_SBACCESS_OFFSET 0x11 -#define DM_SBCS_SBACCESS_LENGTH 3 -#define DM_SBCS_SBACCESS 0xe0000 +#define DM_SBCS_SBACCESS_OFFSET 0x11ULL +#define DM_SBCS_SBACCESS_LENGTH 3ULL +#define DM_SBCS_SBACCESS 0xe0000ULL /* * 8bit: 8-bit */ @@ -2679,16 +2687,16 @@ * When 1, {\tt sbaddress} is incremented by the access size (in * bytes) selected in \FdmSbcsSbaccess after every system bus access. */ -#define DM_SBCS_SBAUTOINCREMENT_OFFSET 0x10 -#define DM_SBCS_SBAUTOINCREMENT_LENGTH 1 -#define DM_SBCS_SBAUTOINCREMENT 0x10000 +#define DM_SBCS_SBAUTOINCREMENT_OFFSET 0x10ULL +#define DM_SBCS_SBAUTOINCREMENT_LENGTH 1ULL +#define DM_SBCS_SBAUTOINCREMENT 0x10000ULL /* * When 1, every read from \RdmSbdataZero automatically triggers a * system bus read at the (possibly auto-incremented) address. */ -#define DM_SBCS_SBREADONDATA_OFFSET 0xf -#define DM_SBCS_SBREADONDATA_LENGTH 1 -#define DM_SBCS_SBREADONDATA 0x8000 +#define DM_SBCS_SBREADONDATA_OFFSET 0xfULL +#define DM_SBCS_SBREADONDATA_LENGTH 1ULL +#define DM_SBCS_SBREADONDATA 0x8000ULL /* * When the Debug Module's system bus * manager encounters an error, this field gets set. The bits in this @@ -2698,9 +2706,9 @@ * * An implementation may report ``Other'' (7) for any error condition. */ -#define DM_SBCS_SBERROR_OFFSET 0xc -#define DM_SBCS_SBERROR_LENGTH 3 -#define DM_SBCS_SBERROR 0x7000 +#define DM_SBCS_SBERROR_OFFSET 0xcULL +#define DM_SBCS_SBERROR_LENGTH 3ULL +#define DM_SBCS_SBERROR 0x7000ULL /* * none: There was no bus error. */ @@ -2729,101 +2737,101 @@ * Width of system bus addresses in bits. (0 indicates there is no bus * access support.) */ -#define DM_SBCS_SBASIZE_OFFSET 5 -#define DM_SBCS_SBASIZE_LENGTH 7 -#define DM_SBCS_SBASIZE 0xfe0 +#define DM_SBCS_SBASIZE_OFFSET 5ULL +#define DM_SBCS_SBASIZE_LENGTH 7ULL +#define DM_SBCS_SBASIZE 0xfe0ULL /* * 1 when 128-bit system bus accesses are supported. */ -#define DM_SBCS_SBACCESS128_OFFSET 4 -#define DM_SBCS_SBACCESS128_LENGTH 1 -#define DM_SBCS_SBACCESS128 0x10 +#define DM_SBCS_SBACCESS128_OFFSET 4ULL +#define DM_SBCS_SBACCESS128_LENGTH 1ULL +#define DM_SBCS_SBACCESS128 0x10ULL /* * 1 when 64-bit system bus accesses are supported. */ -#define DM_SBCS_SBACCESS64_OFFSET 3 -#define DM_SBCS_SBACCESS64_LENGTH 1 -#define DM_SBCS_SBACCESS64 8 +#define DM_SBCS_SBACCESS64_OFFSET 3ULL +#define DM_SBCS_SBACCESS64_LENGTH 1ULL +#define DM_SBCS_SBACCESS64 8ULL /* * 1 when 32-bit system bus accesses are supported. */ -#define DM_SBCS_SBACCESS32_OFFSET 2 -#define DM_SBCS_SBACCESS32_LENGTH 1 -#define DM_SBCS_SBACCESS32 4 +#define DM_SBCS_SBACCESS32_OFFSET 2ULL +#define DM_SBCS_SBACCESS32_LENGTH 1ULL +#define DM_SBCS_SBACCESS32 4ULL /* * 1 when 16-bit system bus accesses are supported. */ -#define DM_SBCS_SBACCESS16_OFFSET 1 -#define DM_SBCS_SBACCESS16_LENGTH 1 -#define DM_SBCS_SBACCESS16 2 +#define DM_SBCS_SBACCESS16_OFFSET 1ULL +#define DM_SBCS_SBACCESS16_LENGTH 1ULL +#define DM_SBCS_SBACCESS16 2ULL /* * 1 when 8-bit system bus accesses are supported. */ -#define DM_SBCS_SBACCESS8_OFFSET 0 -#define DM_SBCS_SBACCESS8_LENGTH 1 -#define DM_SBCS_SBACCESS8 1 +#define DM_SBCS_SBACCESS8_OFFSET 0ULL +#define DM_SBCS_SBACCESS8_LENGTH 1ULL +#define DM_SBCS_SBACCESS8 1ULL #define DM_SBADDRESS0 0x39 /* * Accesses bits 31:0 of the physical address in {\tt sbaddress}. */ -#define DM_SBADDRESS0_ADDRESS_OFFSET 0 -#define DM_SBADDRESS0_ADDRESS_LENGTH 0x20 -#define DM_SBADDRESS0_ADDRESS 0xffffffffU +#define DM_SBADDRESS0_ADDRESS_OFFSET 0ULL +#define DM_SBADDRESS0_ADDRESS_LENGTH 0x20ULL +#define DM_SBADDRESS0_ADDRESS 0xffffffffULL #define DM_SBADDRESS1 0x3a /* * Accesses bits 63:32 of the physical address in {\tt sbaddress} (if * the system address bus is that wide). */ -#define DM_SBADDRESS1_ADDRESS_OFFSET 0 -#define DM_SBADDRESS1_ADDRESS_LENGTH 0x20 -#define DM_SBADDRESS1_ADDRESS 0xffffffffU +#define DM_SBADDRESS1_ADDRESS_OFFSET 0ULL +#define DM_SBADDRESS1_ADDRESS_LENGTH 0x20ULL +#define DM_SBADDRESS1_ADDRESS 0xffffffffULL #define DM_SBADDRESS2 0x3b /* * Accesses bits 95:64 of the physical address in {\tt sbaddress} (if * the system address bus is that wide). */ -#define DM_SBADDRESS2_ADDRESS_OFFSET 0 -#define DM_SBADDRESS2_ADDRESS_LENGTH 0x20 -#define DM_SBADDRESS2_ADDRESS 0xffffffffU +#define DM_SBADDRESS2_ADDRESS_OFFSET 0ULL +#define DM_SBADDRESS2_ADDRESS_LENGTH 0x20ULL +#define DM_SBADDRESS2_ADDRESS 0xffffffffULL #define DM_SBADDRESS3 0x37 /* * Accesses bits 127:96 of the physical address in {\tt sbaddress} (if * the system address bus is that wide). */ -#define DM_SBADDRESS3_ADDRESS_OFFSET 0 -#define DM_SBADDRESS3_ADDRESS_LENGTH 0x20 -#define DM_SBADDRESS3_ADDRESS 0xffffffffU +#define DM_SBADDRESS3_ADDRESS_OFFSET 0ULL +#define DM_SBADDRESS3_ADDRESS_LENGTH 0x20ULL +#define DM_SBADDRESS3_ADDRESS 0xffffffffULL #define DM_SBDATA0 0x3c /* * Accesses bits 31:0 of {\tt sbdata}. */ -#define DM_SBDATA0_DATA_OFFSET 0 -#define DM_SBDATA0_DATA_LENGTH 0x20 -#define DM_SBDATA0_DATA 0xffffffffU +#define DM_SBDATA0_DATA_OFFSET 0ULL +#define DM_SBDATA0_DATA_LENGTH 0x20ULL +#define DM_SBDATA0_DATA 0xffffffffULL #define DM_SBDATA1 0x3d /* * Accesses bits 63:32 of {\tt sbdata} (if the system bus is that * wide). */ -#define DM_SBDATA1_DATA_OFFSET 0 -#define DM_SBDATA1_DATA_LENGTH 0x20 -#define DM_SBDATA1_DATA 0xffffffffU +#define DM_SBDATA1_DATA_OFFSET 0ULL +#define DM_SBDATA1_DATA_LENGTH 0x20ULL +#define DM_SBDATA1_DATA 0xffffffffULL #define DM_SBDATA2 0x3e /* * Accesses bits 95:64 of {\tt sbdata} (if the system bus is that * wide). */ -#define DM_SBDATA2_DATA_OFFSET 0 -#define DM_SBDATA2_DATA_LENGTH 0x20 -#define DM_SBDATA2_DATA 0xffffffffU +#define DM_SBDATA2_DATA_OFFSET 0ULL +#define DM_SBDATA2_DATA_LENGTH 0x20ULL +#define DM_SBDATA2_DATA 0xffffffffULL #define DM_SBDATA3 0x3f /* * Accesses bits 127:96 of {\tt sbdata} (if the system bus is that * wide). */ -#define DM_SBDATA3_DATA_OFFSET 0 -#define DM_SBDATA3_DATA_LENGTH 0x20 -#define DM_SBDATA3_DATA 0xffffffffU +#define DM_SBDATA3_DATA_OFFSET 0ULL +#define DM_SBDATA3_DATA_LENGTH 0x20ULL +#define DM_SBDATA3_DATA 0xffffffffULL #define DM_CUSTOM 0x1f #define DM_CUSTOM0 0x70 #define DM_CUSTOM1 0x71 @@ -2845,18 +2853,18 @@ /* * Description of what this field is used for. */ -#define SHORTNAME_FIELD_OFFSET 0 -#define SHORTNAME_FIELD_LENGTH 8 -#define SHORTNAME_FIELD 0xff +#define SHORTNAME_FIELD_OFFSET 0ULL +#define SHORTNAME_FIELD_LENGTH 8ULL +#define SHORTNAME_FIELD 0xffULL /* * This is 0 to indicate Access Register Command. */ -#define AC_ACCESS_REGISTER_CMDTYPE_OFFSET 0x18 -#define AC_ACCESS_REGISTER_CMDTYPE_LENGTH 8 -#define AC_ACCESS_REGISTER_CMDTYPE 0xff000000U -#define AC_ACCESS_REGISTER_AARSIZE_OFFSET 0x14 -#define AC_ACCESS_REGISTER_AARSIZE_LENGTH 3 -#define AC_ACCESS_REGISTER_AARSIZE 0x700000 +#define AC_ACCESS_REGISTER_CMDTYPE_OFFSET 0x18ULL +#define AC_ACCESS_REGISTER_CMDTYPE_LENGTH 8ULL +#define AC_ACCESS_REGISTER_CMDTYPE 0xff000000ULL +#define AC_ACCESS_REGISTER_AARSIZE_OFFSET 0x14ULL +#define AC_ACCESS_REGISTER_AARSIZE_LENGTH 3ULL +#define AC_ACCESS_REGISTER_AARSIZE 0x700000ULL /* * 32bit: Access the lowest 32 bits of the register. */ @@ -2879,9 +2887,9 @@ * This field controls the Argument Width as referenced in * Table~\ref{tab:datareg}. */ -#define AC_ACCESS_REGISTER_AARPOSTINCREMENT_OFFSET 0x13 -#define AC_ACCESS_REGISTER_AARPOSTINCREMENT_LENGTH 1 -#define AC_ACCESS_REGISTER_AARPOSTINCREMENT 0x80000 +#define AC_ACCESS_REGISTER_AARPOSTINCREMENT_OFFSET 0x13ULL +#define AC_ACCESS_REGISTER_AARPOSTINCREMENT_LENGTH 1ULL +#define AC_ACCESS_REGISTER_AARPOSTINCREMENT 0x80000ULL /* * disabled: No effect. This variant must be supported. */ @@ -2894,9 +2902,9 @@ * happens when \FacAccessregisterTransfer is 0. */ #define AC_ACCESS_REGISTER_AARPOSTINCREMENT_ENABLED 1 -#define AC_ACCESS_REGISTER_POSTEXEC_OFFSET 0x12 -#define AC_ACCESS_REGISTER_POSTEXEC_LENGTH 1 -#define AC_ACCESS_REGISTER_POSTEXEC 0x40000 +#define AC_ACCESS_REGISTER_POSTEXEC_OFFSET 0x12ULL +#define AC_ACCESS_REGISTER_POSTEXEC_LENGTH 1ULL +#define AC_ACCESS_REGISTER_POSTEXEC 0x40000ULL /* * disabled: No effect. This variant must be supported, and is the only * supported one if \FdmAbstractcsProgbufsize is 0. @@ -2908,9 +2916,9 @@ * optional. */ #define AC_ACCESS_REGISTER_POSTEXEC_ENABLED 1 -#define AC_ACCESS_REGISTER_TRANSFER_OFFSET 0x11 -#define AC_ACCESS_REGISTER_TRANSFER_LENGTH 1 -#define AC_ACCESS_REGISTER_TRANSFER 0x20000 +#define AC_ACCESS_REGISTER_TRANSFER_OFFSET 0x11ULL +#define AC_ACCESS_REGISTER_TRANSFER_LENGTH 1ULL +#define AC_ACCESS_REGISTER_TRANSFER 0x20000ULL /* * disabled: Don't do the operation specified by \FacAccessregisterWrite. */ @@ -2926,9 +2934,9 @@ /* * When \FacAccessregisterTransfer is set: */ -#define AC_ACCESS_REGISTER_WRITE_OFFSET 0x10 -#define AC_ACCESS_REGISTER_WRITE_LENGTH 1 -#define AC_ACCESS_REGISTER_WRITE 0x10000 +#define AC_ACCESS_REGISTER_WRITE_OFFSET 0x10ULL +#define AC_ACCESS_REGISTER_WRITE_LENGTH 1ULL +#define AC_ACCESS_REGISTER_WRITE 0x10000ULL /* * arg0: Copy data from the specified register into {\tt arg0} portion * of {\tt data}. @@ -2945,29 +2953,29 @@ * \RcsrDpc may be used as an alias for PC if this command is * supported on a non-halted hart. */ -#define AC_ACCESS_REGISTER_REGNO_OFFSET 0 -#define AC_ACCESS_REGISTER_REGNO_LENGTH 0x10 -#define AC_ACCESS_REGISTER_REGNO 0xffff +#define AC_ACCESS_REGISTER_REGNO_OFFSET 0ULL +#define AC_ACCESS_REGISTER_REGNO_LENGTH 0x10ULL +#define AC_ACCESS_REGISTER_REGNO 0xffffULL /* * This is 1 to indicate Quick Access command. */ -#define AC_QUICK_ACCESS_CMDTYPE_OFFSET 0x18 -#define AC_QUICK_ACCESS_CMDTYPE_LENGTH 8 -#define AC_QUICK_ACCESS_CMDTYPE 0xff000000U +#define AC_QUICK_ACCESS_CMDTYPE_OFFSET 0x18ULL +#define AC_QUICK_ACCESS_CMDTYPE_LENGTH 8ULL +#define AC_QUICK_ACCESS_CMDTYPE 0xff000000ULL /* * This is 2 to indicate Access Memory Command. */ -#define AC_ACCESS_MEMORY_CMDTYPE_OFFSET 0x18 -#define AC_ACCESS_MEMORY_CMDTYPE_LENGTH 8 -#define AC_ACCESS_MEMORY_CMDTYPE 0xff000000U +#define AC_ACCESS_MEMORY_CMDTYPE_OFFSET 0x18ULL +#define AC_ACCESS_MEMORY_CMDTYPE_LENGTH 8ULL +#define AC_ACCESS_MEMORY_CMDTYPE 0xff000000ULL /* * An implementation does not have to implement both virtual and * physical accesses, but it must fail accesses that it doesn't * support. */ -#define AC_ACCESS_MEMORY_AAMVIRTUAL_OFFSET 0x17 -#define AC_ACCESS_MEMORY_AAMVIRTUAL_LENGTH 1 -#define AC_ACCESS_MEMORY_AAMVIRTUAL 0x800000 +#define AC_ACCESS_MEMORY_AAMVIRTUAL_OFFSET 0x17ULL +#define AC_ACCESS_MEMORY_AAMVIRTUAL_LENGTH 1ULL +#define AC_ACCESS_MEMORY_AAMVIRTUAL 0x800000ULL /* * physical: Addresses are physical (to the hart they are performed on). */ @@ -2982,9 +2990,9 @@ * may optionally allow \FacAccessmemoryAamvirtual set to 1, which would produce the same result as * that same abstract command with \FacAccessmemoryAamvirtual cleared. */ -#define AC_ACCESS_MEMORY_AAMSIZE_OFFSET 0x14 -#define AC_ACCESS_MEMORY_AAMSIZE_LENGTH 3 -#define AC_ACCESS_MEMORY_AAMSIZE 0x700000 +#define AC_ACCESS_MEMORY_AAMSIZE_OFFSET 0x14ULL +#define AC_ACCESS_MEMORY_AAMSIZE_LENGTH 3ULL +#define AC_ACCESS_MEMORY_AAMSIZE 0x700000ULL /* * 8bit: Access the lowest 8 bits of the memory location. */ @@ -3010,19 +3018,15 @@ * {\tt arg1} (which contains the address used) by the number of bytes * encoded in \FacAccessmemoryAamsize. * - * Implementations that allow this bit to be 1 must implement the - * relevant {\tt data} registers as traditional registers instead of - * MRs. - * * Supporting this variant is optional, but highly recommended for * performance reasons. */ -#define AC_ACCESS_MEMORY_AAMPOSTINCREMENT_OFFSET 0x13 -#define AC_ACCESS_MEMORY_AAMPOSTINCREMENT_LENGTH 1 -#define AC_ACCESS_MEMORY_AAMPOSTINCREMENT 0x80000 -#define AC_ACCESS_MEMORY_WRITE_OFFSET 0x10 -#define AC_ACCESS_MEMORY_WRITE_LENGTH 1 -#define AC_ACCESS_MEMORY_WRITE 0x10000 +#define AC_ACCESS_MEMORY_AAMPOSTINCREMENT_OFFSET 0x13ULL +#define AC_ACCESS_MEMORY_AAMPOSTINCREMENT_LENGTH 1ULL +#define AC_ACCESS_MEMORY_AAMPOSTINCREMENT 0x80000ULL +#define AC_ACCESS_MEMORY_WRITE_OFFSET 0x10ULL +#define AC_ACCESS_MEMORY_WRITE_LENGTH 1ULL +#define AC_ACCESS_MEMORY_WRITE 0x10000ULL /* * arg0: Copy data from the memory location specified in {\tt arg1} into * the low bits of {\tt arg0}. The value of the remaining bits of @@ -3037,9 +3041,9 @@ /* * These bits are reserved for target-specific uses. */ -#define AC_ACCESS_MEMORY_TARGET_SPECIFIC_OFFSET 0xe -#define AC_ACCESS_MEMORY_TARGET_SPECIFIC_LENGTH 2 -#define AC_ACCESS_MEMORY_TARGET_SPECIFIC 0xc000 +#define AC_ACCESS_MEMORY_TARGET_SPECIFIC_OFFSET 0xeULL +#define AC_ACCESS_MEMORY_TARGET_SPECIFIC_LENGTH 2ULL +#define AC_ACCESS_MEMORY_TARGET_SPECIFIC 0xc000ULL #define VIRT_PRIV virtual /* * Contains the virtualization mode the hart was operating in when Debug @@ -3048,9 +3052,9 @@ * A user can write this value to change the hart's virtualization mode * when exiting Debug Mode. */ -#define VIRT_PRIV_V_OFFSET 2 -#define VIRT_PRIV_V_LENGTH 1 -#define VIRT_PRIV_V 4 +#define VIRT_PRIV_V_OFFSET 2ULL +#define VIRT_PRIV_V_LENGTH 1ULL +#define VIRT_PRIV_V 4ULL /* * Contains the privilege mode the hart was operating in when Debug * Mode was entered. The encoding is described in Table @@ -3058,113 +3062,9 @@ * the Privileged Spec. A user can write this * value to change the hart's privilege mode when exiting Debug Mode. */ -#define VIRT_PRIV_PRV_OFFSET 0 -#define VIRT_PRIV_PRV_LENGTH 2 -#define VIRT_PRIV_PRV 3 -#define DMI_SERCS 0x34 -/* - * Number of supported serial ports. - */ -#define DMI_SERCS_SERIALCOUNT_OFFSET 0x1c -#define DMI_SERCS_SERIALCOUNT_LENGTH 4 -#define DMI_SERCS_SERIALCOUNT 0xf0000000U -/* - * Select which serial port is accessed by \RdmiSerrx and \RdmiSertx. - */ -#define DMI_SERCS_SERIAL_OFFSET 0x18 -#define DMI_SERCS_SERIAL_LENGTH 3 -#define DMI_SERCS_SERIAL 0x7000000 -#define DMI_SERCS_ERROR7_OFFSET 0x17 -#define DMI_SERCS_ERROR7_LENGTH 1 -#define DMI_SERCS_ERROR7 0x800000 -#define DMI_SERCS_VALID7_OFFSET 0x16 -#define DMI_SERCS_VALID7_LENGTH 1 -#define DMI_SERCS_VALID7 0x400000 -#define DMI_SERCS_FULL7_OFFSET 0x15 -#define DMI_SERCS_FULL7_LENGTH 1 -#define DMI_SERCS_FULL7 0x200000 -#define DMI_SERCS_ERROR6_OFFSET 0x14 -#define DMI_SERCS_ERROR6_LENGTH 1 -#define DMI_SERCS_ERROR6 0x100000 -#define DMI_SERCS_VALID6_OFFSET 0x13 -#define DMI_SERCS_VALID6_LENGTH 1 -#define DMI_SERCS_VALID6 0x80000 -#define DMI_SERCS_FULL6_OFFSET 0x12 -#define DMI_SERCS_FULL6_LENGTH 1 -#define DMI_SERCS_FULL6 0x40000 -#define DMI_SERCS_ERROR5_OFFSET 0x11 -#define DMI_SERCS_ERROR5_LENGTH 1 -#define DMI_SERCS_ERROR5 0x20000 -#define DMI_SERCS_VALID5_OFFSET 0x10 -#define DMI_SERCS_VALID5_LENGTH 1 -#define DMI_SERCS_VALID5 0x10000 -#define DMI_SERCS_FULL5_OFFSET 0xf -#define DMI_SERCS_FULL5_LENGTH 1 -#define DMI_SERCS_FULL5 0x8000 -#define DMI_SERCS_ERROR4_OFFSET 0xe -#define DMI_SERCS_ERROR4_LENGTH 1 -#define DMI_SERCS_ERROR4 0x4000 -#define DMI_SERCS_VALID4_OFFSET 0xd -#define DMI_SERCS_VALID4_LENGTH 1 -#define DMI_SERCS_VALID4 0x2000 -#define DMI_SERCS_FULL4_OFFSET 0xc -#define DMI_SERCS_FULL4_LENGTH 1 -#define DMI_SERCS_FULL4 0x1000 -#define DMI_SERCS_ERROR3_OFFSET 0xb -#define DMI_SERCS_ERROR3_LENGTH 1 -#define DMI_SERCS_ERROR3 0x800 -#define DMI_SERCS_VALID3_OFFSET 0xa -#define DMI_SERCS_VALID3_LENGTH 1 -#define DMI_SERCS_VALID3 0x400 -#define DMI_SERCS_FULL3_OFFSET 9 -#define DMI_SERCS_FULL3_LENGTH 1 -#define DMI_SERCS_FULL3 0x200 -#define DMI_SERCS_ERROR2_OFFSET 8 -#define DMI_SERCS_ERROR2_LENGTH 1 -#define DMI_SERCS_ERROR2 0x100 -#define DMI_SERCS_VALID2_OFFSET 7 -#define DMI_SERCS_VALID2_LENGTH 1 -#define DMI_SERCS_VALID2 0x80 -#define DMI_SERCS_FULL2_OFFSET 6 -#define DMI_SERCS_FULL2_LENGTH 1 -#define DMI_SERCS_FULL2 0x40 -#define DMI_SERCS_ERROR1_OFFSET 5 -#define DMI_SERCS_ERROR1_LENGTH 1 -#define DMI_SERCS_ERROR1 0x20 -#define DMI_SERCS_VALID1_OFFSET 4 -#define DMI_SERCS_VALID1_LENGTH 1 -#define DMI_SERCS_VALID1 0x10 -#define DMI_SERCS_FULL1_OFFSET 3 -#define DMI_SERCS_FULL1_LENGTH 1 -#define DMI_SERCS_FULL1 8 -/* - * 1 when the debugger-to-core queue for serial port 0 has - * over or underflowed. This bit will remain set until it is reset by - * writing 1 to this bit. - */ -#define DMI_SERCS_ERROR0_OFFSET 2 -#define DMI_SERCS_ERROR0_LENGTH 1 -#define DMI_SERCS_ERROR0 4 -/* - * 1 when the core-to-debugger queue for serial port 0 is not empty. - */ -#define DMI_SERCS_VALID0_OFFSET 1 -#define DMI_SERCS_VALID0_LENGTH 1 -#define DMI_SERCS_VALID0 2 -/* - * 1 when the debugger-to-core queue for serial port 0 is full. - */ -#define DMI_SERCS_FULL0_OFFSET 0 -#define DMI_SERCS_FULL0_LENGTH 1 -#define DMI_SERCS_FULL0 1 -#define DMI_SERTX 0x35 -#define DMI_SERTX_DATA_OFFSET 0 -#define DMI_SERTX_DATA_LENGTH 0x20 -#define DMI_SERTX_DATA 0xffffffffU -#define DMI_SERRX 0x36 -#define DMI_SERRX_DATA_OFFSET 0 -#define DMI_SERRX_DATA_LENGTH 0x20 -#define DMI_SERRX_DATA 0xffffffffU +#define VIRT_PRIV_PRV_OFFSET 0ULL +#define VIRT_PRIV_PRV_LENGTH 2ULL +#define VIRT_PRIV_PRV 3ULL enum riscv_debug_reg_ordinal { DTM_IDCODE_ORDINAL, DTM_DTMCS_ORDINAL, @@ -3172,14 +3072,16 @@ enum riscv_debug_reg_ordinal { DTM_BYPASS_ORDINAL, CSR_DCSR_ORDINAL, CSR_DPC_ORDINAL, + CSR_DSCRATCH0_ORDINAL, + CSR_DSCRATCH1_ORDINAL, CSR_TSELECT_ORDINAL, CSR_TDATA1_ORDINAL, CSR_TDATA2_ORDINAL, CSR_TDATA3_ORDINAL, CSR_TINFO_ORDINAL, CSR_TCONTROL_ORDINAL, - CSR_HCONTEXT_ORDINAL, CSR_SCONTEXT_ORDINAL, + CSR_MCONTEXT_ORDINAL, CSR_MCONTROL_ORDINAL, CSR_MCONTROL6_ORDINAL, CSR_ICOUNT_ORDINAL, @@ -3222,10 +3124,7 @@ enum riscv_debug_reg_ordinal { AC_ACCESS_REGISTER_ORDINAL, AC_QUICK_ACCESS_ORDINAL, AC_ACCESS_MEMORY_ORDINAL, - VIRT_PRIV_ORDINAL, - DMI_SERCS_ORDINAL, - DMI_SERTX_ORDINAL, - DMI_SERRX_ORDINAL + VIRT_PRIV_ORDINAL }; typedef struct { struct { diff --git a/src/target/riscv/debug_reg_printer.c b/src/target/riscv/debug_reg_printer.c index 968c9833e..fc7dabd26 100644 --- a/src/target/riscv/debug_reg_printer.c +++ b/src/target/riscv/debug_reg_printer.c @@ -62,22 +62,35 @@ static uint64_t riscv_debug_reg_field_value(riscv_debug_reg_field_info_t field, static unsigned int riscv_debug_reg_fields_to_s(char *buf, unsigned int offset, struct riscv_debug_reg_field_list_t (*get_next)(riscv_debug_reg_ctx_t contex), - riscv_debug_reg_ctx_t context, uint64_t value) + riscv_debug_reg_ctx_t context, uint64_t value, + enum riscv_debug_reg_show show) { unsigned int curr = offset; - curr += get_len_or_sprintf(buf, curr, " { "); + curr += get_len_or_sprintf(buf, curr, " {"); + char *separator = ""; for (struct riscv_debug_reg_field_list_t list; get_next; get_next = list.get_next) { list = get_next(context); - curr += riscv_debug_reg_field_to_s(buf, curr, list.field, context, - riscv_debug_reg_field_value(list.field, value)); - curr += get_len_or_sprintf(buf, curr, ", "); + + uint64_t field_value = riscv_debug_reg_field_value(list.field, value); + + if (show == RISCV_DEBUG_REG_SHOW_ALL || + (show == RISCV_DEBUG_REG_HIDE_UNNAMED_0 && + (field_value != 0 || + (list.field.values && list.field.values[0]))) || + (show == RISCV_DEBUG_REG_HIDE_ALL_0 && field_value != 0)) { + curr += get_len_or_sprintf(buf, curr, separator); + curr += riscv_debug_reg_field_to_s(buf, curr, list.field, context, + field_value); + separator = " "; + } } curr += get_len_or_sprintf(buf, curr, "}"); return curr - offset; } unsigned int riscv_debug_reg_to_s(char *buf, enum riscv_debug_reg_ordinal reg_ordinal, - riscv_debug_reg_ctx_t context, uint64_t value) + riscv_debug_reg_ctx_t context, uint64_t value, + enum riscv_debug_reg_show show) { unsigned int length = 0; @@ -88,7 +101,7 @@ unsigned int riscv_debug_reg_to_s(char *buf, enum riscv_debug_reg_ordinal reg_or if (reg.get_fields_head) length += riscv_debug_reg_fields_to_s(buf, length, - reg.get_fields_head, context, value); + reg.get_fields_head, context, value, show); if (buf) buf[length] = '\0'; diff --git a/src/target/riscv/debug_reg_printer.h b/src/target/riscv/debug_reg_printer.h index 8b7a26176..98226b772 100644 --- a/src/target/riscv/debug_reg_printer.h +++ b/src/target/riscv/debug_reg_printer.h @@ -2,6 +2,12 @@ #include "debug_defines.h" +enum riscv_debug_reg_show { + RISCV_DEBUG_REG_SHOW_ALL, + RISCV_DEBUG_REG_HIDE_ALL_0, + RISCV_DEBUG_REG_HIDE_UNNAMED_0, +}; + /** * This function is used to fill a buffer with a decoded string representation * of register's value. @@ -25,4 +31,5 @@ * riscv_debug_reg_to_s(buf, DTM_DMI_ORDINAL, context, ); */ unsigned int riscv_debug_reg_to_s(char *buf, enum riscv_debug_reg_ordinal reg_ordinal, - riscv_debug_reg_ctx_t context, uint64_t value); + riscv_debug_reg_ctx_t context, uint64_t value, + enum riscv_debug_reg_show show); diff --git a/src/target/riscv/riscv-013.c b/src/target/riscv/riscv-013.c index d3da9fcff..928e7adf5 100644 --- a/src/target/riscv/riscv-013.c +++ b/src/target/riscv/riscv-013.c @@ -302,12 +302,12 @@ static void log_debug_reg(struct target *target, enum riscv_debug_reg_ordinal re if (debug_level < LOG_LVL_DEBUG) return; const riscv_debug_reg_ctx_t context = get_riscv_debug_reg_ctx(target); - char * const buf = malloc(riscv_debug_reg_to_s(NULL, reg, context, value) + 1); + char * const buf = malloc(riscv_debug_reg_to_s(NULL, reg, context, value, RISCV_DEBUG_REG_HIDE_UNNAMED_0) + 1); if (!buf) { LOG_ERROR("Unable to allocate memory."); return; } - riscv_debug_reg_to_s(buf, reg, context, value); + riscv_debug_reg_to_s(buf, reg, context, value, RISCV_DEBUG_REG_HIDE_UNNAMED_0); log_printf_lf(LOG_LVL_DEBUG, file, line, func, "[%s] %s", target_name(target), buf); free(buf); } @@ -356,7 +356,7 @@ static unsigned int decode_dm(char *text, unsigned int address, unsigned int dat .abits = { .value = 0, .is_set = false }, }; return riscv_debug_reg_to_s(text, description[i].ordinal, - context, data); + context, data, RISCV_DEBUG_REG_HIDE_ALL_0); } } if (text)