Propagate errors in more places
Change-Id: I5a7594d4b44c524537827f403348d0c10814546f
This commit is contained in:
parent
3ddbbd525d
commit
848062d0d1
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@ -39,7 +39,7 @@ static void riscv013_clear_abstract_error(struct target *target);
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static int riscv013_get_register(struct target *target,
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static int riscv013_get_register(struct target *target,
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riscv_reg_t *value, int hid, int rid);
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riscv_reg_t *value, int hid, int rid);
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static int riscv013_set_register(struct target *target, int hartid, int regid, uint64_t value);
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static int riscv013_set_register(struct target *target, int hartid, int regid, uint64_t value);
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static void riscv013_select_current_hart(struct target *target);
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static int riscv013_select_current_hart(struct target *target);
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static int riscv013_halt_current_hart(struct target *target);
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static int riscv013_halt_current_hart(struct target *target);
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static int riscv013_resume_current_hart(struct target *target);
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static int riscv013_resume_current_hart(struct target *target);
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static int riscv013_step_current_hart(struct target *target);
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static int riscv013_step_current_hart(struct target *target);
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@ -479,7 +479,8 @@ static dmi_status_t dmi_scan(struct target *target, uint32_t *address_in,
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return buf_get_u32(in, DTM_DMI_OP_OFFSET, DTM_DMI_OP_LENGTH);
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return buf_get_u32(in, DTM_DMI_OP_OFFSET, DTM_DMI_OP_LENGTH);
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}
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}
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static int dmi_read(struct target *target, uint32_t *value, uint32_t address)
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static int dmi_op(struct target *target, uint32_t *data_in, int dmi_op,
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uint32_t address, uint32_t data_out)
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{
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{
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select_dmi(target);
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select_dmi(target);
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@ -488,49 +489,66 @@ static int dmi_read(struct target *target, uint32_t *value, uint32_t address)
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unsigned i = 0;
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unsigned i = 0;
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/* This first loop ensures that the read request was actually sent
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const char *op_name;
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* to the target. Note that if for some reason this stays busy,
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switch (dmi_op) {
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* it is actually due to the previous dmi_read or dmi_write. */
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case DMI_OP_NOP:
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op_name = "nop";
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break;
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case DMI_OP_READ:
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op_name = "read";
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break;
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case DMI_OP_WRITE:
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op_name = "write";
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break;
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default:
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LOG_ERROR("Invalid DMI operation: %d", dmi_op);
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return ERROR_FAIL;
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}
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/* This first loop performs the request. Note that if for some reason this
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* stays busy, it is actually due to the previous access. */
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for (i = 0; i < 256; i++) {
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for (i = 0; i < 256; i++) {
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status = dmi_scan(target, NULL, NULL, DMI_OP_READ, address, 0,
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status = dmi_scan(target, NULL, NULL, dmi_op, address, data_out,
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false);
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false);
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if (status == DMI_STATUS_BUSY) {
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if (status == DMI_STATUS_BUSY) {
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increase_dmi_busy_delay(target);
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increase_dmi_busy_delay(target);
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} else if (status == DMI_STATUS_SUCCESS) {
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} else if (status == DMI_STATUS_SUCCESS) {
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break;
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break;
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} else {
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} else {
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LOG_ERROR("failed read from 0x%x, status=%d", address, status);
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LOG_ERROR("failed %s at 0x%x, status=%d", op_name, address, status);
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return ERROR_FAIL;
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return ERROR_FAIL;
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}
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}
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}
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}
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if (status != DMI_STATUS_SUCCESS) {
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if (status != DMI_STATUS_SUCCESS) {
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LOG_ERROR("Failed read from 0x%x; status=%d", address, status);
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LOG_ERROR("Failed %s at 0x%x; status=%d", op_name, address, status);
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return ERROR_FAIL;
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return ERROR_FAIL;
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}
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}
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/* This second loop ensures that we got the read
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/* This second loop ensures the request succeeded, and gets back data.
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* data back. Note that NOP can result in a 'busy' result as well, but
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* Note that NOP can result in a 'busy' result as well, but that would be
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* that would be noticed on the next DMI access we do. */
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* noticed on the next DMI access we do. */
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for (i = 0; i < 256; i++) {
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for (i = 0; i < 256; i++) {
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status = dmi_scan(target, &address_in, value, DMI_OP_NOP, address, 0,
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status = dmi_scan(target, &address_in, data_in, DMI_OP_NOP, address, 0,
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false);
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false);
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if (status == DMI_STATUS_BUSY) {
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if (status == DMI_STATUS_BUSY) {
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increase_dmi_busy_delay(target);
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increase_dmi_busy_delay(target);
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} else if (status == DMI_STATUS_SUCCESS) {
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} else if (status == DMI_STATUS_SUCCESS) {
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break;
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break;
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} else {
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} else {
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LOG_ERROR("failed read (NOP) at 0x%x, status=%d", address, status);
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LOG_ERROR("failed %s (NOP) at 0x%x, status=%d", op_name, address,
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status);
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return ERROR_FAIL;
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return ERROR_FAIL;
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}
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}
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}
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}
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if (status != DMI_STATUS_SUCCESS) {
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if (status != DMI_STATUS_SUCCESS) {
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if (status == DMI_STATUS_FAILED) {
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if (status == DMI_STATUS_FAILED || !data_in) {
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LOG_ERROR("Failed read (NOP) from 0x%x; status=%d", address, status);
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LOG_ERROR("Failed %s (NOP) at 0x%x; status=%d", op_name, address,
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status);
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} else {
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} else {
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LOG_ERROR("Failed read (NOP) from 0x%x; value=0x%x, status=%d",
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LOG_ERROR("Failed %s (NOP) at 0x%x; value=0x%x, status=%d",
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address, *value, status);
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op_name, address, *data_in, status);
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}
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}
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return ERROR_FAIL;
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return ERROR_FAIL;
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}
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}
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@ -538,53 +556,14 @@ static int dmi_read(struct target *target, uint32_t *value, uint32_t address)
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return ERROR_OK;
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return ERROR_OK;
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}
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}
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static int dmi_read(struct target *target, uint32_t *value, uint32_t address)
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{
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return dmi_op(target, value, DMI_OP_READ, address, 0);
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}
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static int dmi_write(struct target *target, uint32_t address, uint32_t value)
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static int dmi_write(struct target *target, uint32_t address, uint32_t value)
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{
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{
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select_dmi(target);
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return dmi_op(target, NULL, DMI_OP_WRITE, address, value);
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dmi_status_t status = DMI_STATUS_BUSY;
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unsigned i = 0;
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/* The first loop ensures that we successfully sent the write request. */
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for (i = 0; i < 256; i++) {
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status = dmi_scan(target, NULL, NULL, DMI_OP_WRITE, address, value,
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address == DMI_COMMAND);
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if (status == DMI_STATUS_BUSY) {
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increase_dmi_busy_delay(target);
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} else if (status == DMI_STATUS_SUCCESS) {
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break;
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} else {
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LOG_ERROR("failed write to 0x%x, status=%d", address, status);
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break;
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}
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}
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if (status != DMI_STATUS_SUCCESS) {
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LOG_ERROR("Failed write to 0x%x;, status=%d",
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address, status);
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return ERROR_FAIL;
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}
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/* The second loop isn't strictly necessary, but would ensure that the
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* write is complete/ has no non-busy errors before returning from this
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* function. */
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for (i = 0; i < 256; i++) {
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status = dmi_scan(target, NULL, NULL, DMI_OP_NOP, address, 0,
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false);
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if (status == DMI_STATUS_BUSY) {
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increase_dmi_busy_delay(target);
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} else if (status == DMI_STATUS_SUCCESS) {
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break;
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} else {
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LOG_ERROR("failed write (NOP) at 0x%x, status=%d", address, status);
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break;
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}
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}
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if (status != DMI_STATUS_SUCCESS) {
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LOG_ERROR("failed to write (NOP) 0x%x to 0x%x; status=%d", value, address, status);
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return ERROR_FAIL;
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}
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return ERROR_OK;
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}
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}
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int dmstatus_read(struct target *target, uint32_t *dmstatus,
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int dmstatus_read(struct target *target, uint32_t *dmstatus,
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@ -1352,7 +1331,8 @@ static int examine(struct target *target)
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continue;
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continue;
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r->current_hartid = i;
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r->current_hartid = i;
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riscv013_select_current_hart(target);
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if (riscv013_select_current_hart(target) != ERROR_OK)
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return ERROR_FAIL;
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uint32_t s;
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uint32_t s;
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if (dmstatus_read(target, &s, true) != ERROR_OK)
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if (dmstatus_read(target, &s, true) != ERROR_OK)
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@ -2480,14 +2460,15 @@ static int riscv013_set_register(struct target *target, int hid, int rid, uint64
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return ERROR_OK;
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return ERROR_OK;
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}
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}
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static void riscv013_select_current_hart(struct target *target)
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static int riscv013_select_current_hart(struct target *target)
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{
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{
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RISCV_INFO(r);
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RISCV_INFO(r);
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uint32_t dmcontrol;
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uint32_t dmcontrol;
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dmi_read(target, &dmcontrol, DMI_DMCONTROL);
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if (dmi_read(target, &dmcontrol, DMI_DMCONTROL) != ERROR_OK)
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return ERROR_FAIL;
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dmcontrol = set_field(dmcontrol, hartsel_mask(target), r->current_hartid);
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dmcontrol = set_field(dmcontrol, hartsel_mask(target), r->current_hartid);
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dmi_write(target, DMI_DMCONTROL, dmcontrol);
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return dmi_write(target, DMI_DMCONTROL, dmcontrol);
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}
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}
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static int riscv013_halt_current_hart(struct target *target)
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static int riscv013_halt_current_hart(struct target *target)
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@ -737,19 +737,20 @@ static int old_or_new_riscv_resume(
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return riscv_openocd_resume(target, current, address, handle_breakpoints, debug_execution);
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return riscv_openocd_resume(target, current, address, handle_breakpoints, debug_execution);
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}
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}
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static void riscv_select_current_hart(struct target *target)
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static int riscv_select_current_hart(struct target *target)
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{
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{
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RISCV_INFO(r);
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RISCV_INFO(r);
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if (r->rtos_hartid != -1 && riscv_rtos_enabled(target))
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if (r->rtos_hartid != -1 && riscv_rtos_enabled(target))
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riscv_set_current_hartid(target, r->rtos_hartid);
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return riscv_set_current_hartid(target, r->rtos_hartid);
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else
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else
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riscv_set_current_hartid(target, target->coreid);
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return riscv_set_current_hartid(target, target->coreid);
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}
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}
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static int riscv_read_memory(struct target *target, target_addr_t address,
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static int riscv_read_memory(struct target *target, target_addr_t address,
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uint32_t size, uint32_t count, uint8_t *buffer)
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uint32_t size, uint32_t count, uint8_t *buffer)
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{
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{
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riscv_select_current_hart(target);
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if (riscv_select_current_hart(target) != ERROR_OK)
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return ERROR_FAIL;
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struct target_type *tt = get_target_type(target);
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struct target_type *tt = get_target_type(target);
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return tt->read_memory(target, address, size, count, buffer);
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return tt->read_memory(target, address, size, count, buffer);
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}
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}
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@ -757,7 +758,8 @@ static int riscv_read_memory(struct target *target, target_addr_t address,
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static int riscv_write_memory(struct target *target, target_addr_t address,
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static int riscv_write_memory(struct target *target, target_addr_t address,
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uint32_t size, uint32_t count, const uint8_t *buffer)
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uint32_t size, uint32_t count, const uint8_t *buffer)
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{
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{
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riscv_select_current_hart(target);
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if (riscv_select_current_hart(target) != ERROR_OK)
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return ERROR_FAIL;
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struct target_type *tt = get_target_type(target);
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struct target_type *tt = get_target_type(target);
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return tt->write_memory(target, address, size, count, buffer);
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return tt->write_memory(target, address, size, count, buffer);
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}
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}
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@ -775,7 +777,8 @@ static int riscv_get_gdb_reg_list(struct target *target,
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return ERROR_FAIL;
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return ERROR_FAIL;
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}
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}
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riscv_select_current_hart(target);
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if (riscv_select_current_hart(target) != ERROR_OK)
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return ERROR_FAIL;
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switch (reg_class) {
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switch (reg_class) {
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case REG_CLASS_GENERAL:
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case REG_CLASS_GENERAL:
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@ -964,24 +967,29 @@ int riscv_blank_check_memory(struct target *target,
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/*** OpenOCD Helper Functions ***/
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/*** OpenOCD Helper Functions ***/
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/* 0 means nothing happened, 1 means the hart's state changed (and thus the
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enum riscv_poll_hart {
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* poll should terminate), and -1 means there was an error. */
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RPH_NO_CHANGE,
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static int riscv_poll_hart(struct target *target, int hartid)
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RPH_CHANGE,
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RPH_ERROR
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};
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static enum riscv_poll_hart riscv_poll_hart(struct target *target, int hartid)
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{
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{
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RISCV_INFO(r);
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RISCV_INFO(r);
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riscv_set_current_hartid(target, hartid);
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if (riscv_set_current_hartid(target, hartid) != ERROR_OK)
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return RPH_ERROR;
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LOG_DEBUG("polling hart %d, target->state=%d (TARGET_HALTED=%d)", hartid, target->state, TARGET_HALTED);
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LOG_DEBUG("polling hart %d, target->state=%d (TARGET_HALTED=%d)", hartid,
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target->state, TARGET_HALTED);
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/* If OpenOCD this we're running but this hart is halted then it's time
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/* If OpenOCD thinks we're running but this hart is halted then it's time
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* to raise an event. */
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* to raise an event. */
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if (target->state != TARGET_HALTED && riscv_is_halted(target)) {
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if (target->state != TARGET_HALTED && riscv_is_halted(target)) {
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LOG_DEBUG(" triggered a halt");
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LOG_DEBUG(" triggered a halt");
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r->on_halt(target);
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r->on_halt(target);
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return 1;
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return RPH_CHANGE;
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}
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}
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return 0;
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return RPH_NO_CHANGE;
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}
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}
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/*** OpenOCD Interface ***/
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/*** OpenOCD Interface ***/
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@ -992,14 +1000,14 @@ int riscv_openocd_poll(struct target *target)
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if (riscv_rtos_enabled(target)) {
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if (riscv_rtos_enabled(target)) {
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/* Check every hart for an event. */
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/* Check every hart for an event. */
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for (int i = 0; i < riscv_count_harts(target); ++i) {
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for (int i = 0; i < riscv_count_harts(target); ++i) {
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int out = riscv_poll_hart(target, i);
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enum riscv_poll_hart out = riscv_poll_hart(target, i);
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switch (out) {
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switch (out) {
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case 0:
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case RPH_NO_CHANGE:
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continue;
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continue;
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case 1:
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case RPH_CHANGE:
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triggered_hart = i;
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triggered_hart = i;
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break;
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break;
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case -1:
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case RPH_ERROR:
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return ERROR_FAIL;
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return ERROR_FAIL;
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}
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}
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}
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}
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@ -1018,8 +1026,12 @@ int riscv_openocd_poll(struct target *target)
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for (int i = 0; i < riscv_count_harts(target); ++i)
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for (int i = 0; i < riscv_count_harts(target); ++i)
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riscv_halt_one_hart(target, i);
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riscv_halt_one_hart(target, i);
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} else {
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} else {
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if (riscv_poll_hart(target, riscv_current_hartid(target)) == 0)
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enum riscv_poll_hart out = riscv_poll_hart(target,
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riscv_current_hartid(target));
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if (out == RPH_NO_CHANGE)
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return ERROR_OK;
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return ERROR_OK;
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else if (out == RPH_ERROR)
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return ERROR_FAIL;
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triggered_hart = riscv_current_hartid(target);
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triggered_hart = riscv_current_hartid(target);
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LOG_DEBUG(" hart %d halted", triggered_hart);
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LOG_DEBUG(" hart %d halted", triggered_hart);
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@ -1042,6 +1054,8 @@ int riscv_openocd_poll(struct target *target)
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case RISCV_HALT_UNKNOWN:
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case RISCV_HALT_UNKNOWN:
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target->debug_reason = DBG_REASON_UNDEFINED;
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target->debug_reason = DBG_REASON_UNDEFINED;
|
||||||
break;
|
break;
|
||||||
|
case RISCV_HALT_ERROR:
|
||||||
|
return ERROR_FAIL;
|
||||||
}
|
}
|
||||||
|
|
||||||
if (riscv_rtos_enabled(target)) {
|
if (riscv_rtos_enabled(target)) {
|
||||||
|
@ -1562,7 +1576,8 @@ int riscv_halt_one_hart(struct target *target, int hartid)
|
||||||
{
|
{
|
||||||
RISCV_INFO(r);
|
RISCV_INFO(r);
|
||||||
LOG_DEBUG("halting hart %d", hartid);
|
LOG_DEBUG("halting hart %d", hartid);
|
||||||
riscv_set_current_hartid(target, hartid);
|
if (riscv_set_current_hartid(target, hartid) != ERROR_OK)
|
||||||
|
return ERROR_FAIL;
|
||||||
if (riscv_is_halted(target)) {
|
if (riscv_is_halted(target)) {
|
||||||
LOG_DEBUG(" hart %d requested halt, but was already halted", hartid);
|
LOG_DEBUG(" hart %d requested halt, but was already halted", hartid);
|
||||||
return ERROR_OK;
|
return ERROR_OK;
|
||||||
|
@ -1588,7 +1603,8 @@ int riscv_resume_one_hart(struct target *target, int hartid)
|
||||||
{
|
{
|
||||||
RISCV_INFO(r);
|
RISCV_INFO(r);
|
||||||
LOG_DEBUG("resuming hart %d", hartid);
|
LOG_DEBUG("resuming hart %d", hartid);
|
||||||
riscv_set_current_hartid(target, hartid);
|
if (riscv_set_current_hartid(target, hartid) != ERROR_OK)
|
||||||
|
return ERROR_FAIL;
|
||||||
if (!riscv_is_halted(target)) {
|
if (!riscv_is_halted(target)) {
|
||||||
LOG_DEBUG(" hart %d requested resume, but was already resumed", hartid);
|
LOG_DEBUG(" hart %d requested resume, but was already resumed", hartid);
|
||||||
return ERROR_OK;
|
return ERROR_OK;
|
||||||
|
@ -1609,7 +1625,8 @@ int riscv_step_rtos_hart(struct target *target)
|
||||||
hartid = 0;
|
hartid = 0;
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
riscv_set_current_hartid(target, hartid);
|
if (riscv_set_current_hartid(target, hartid) != ERROR_OK)
|
||||||
|
return ERROR_FAIL;
|
||||||
LOG_DEBUG("stepping hart %d", hartid);
|
LOG_DEBUG("stepping hart %d", hartid);
|
||||||
|
|
||||||
if (!riscv_is_halted(target)) {
|
if (!riscv_is_halted(target)) {
|
||||||
|
@ -1659,33 +1676,35 @@ bool riscv_rtos_enabled(const struct target *target)
|
||||||
return target->rtos != NULL;
|
return target->rtos != NULL;
|
||||||
}
|
}
|
||||||
|
|
||||||
void riscv_set_current_hartid(struct target *target, int hartid)
|
int riscv_set_current_hartid(struct target *target, int hartid)
|
||||||
{
|
{
|
||||||
RISCV_INFO(r);
|
RISCV_INFO(r);
|
||||||
if (!r->select_current_hart)
|
if (!r->select_current_hart)
|
||||||
return;
|
return ERROR_FAIL;
|
||||||
|
|
||||||
int previous_hartid = riscv_current_hartid(target);
|
int previous_hartid = riscv_current_hartid(target);
|
||||||
r->current_hartid = hartid;
|
r->current_hartid = hartid;
|
||||||
assert(riscv_hart_enabled(target, hartid));
|
assert(riscv_hart_enabled(target, hartid));
|
||||||
LOG_DEBUG("setting hartid to %d, was %d", hartid, previous_hartid);
|
LOG_DEBUG("setting hartid to %d, was %d", hartid, previous_hartid);
|
||||||
r->select_current_hart(target);
|
if (r->select_current_hart(target) != ERROR_OK)
|
||||||
|
return ERROR_FAIL;
|
||||||
|
|
||||||
/* This might get called during init, in which case we shouldn't be
|
/* This might get called during init, in which case we shouldn't be
|
||||||
* setting up the register cache. */
|
* setting up the register cache. */
|
||||||
if (!target_was_examined(target))
|
if (!target_was_examined(target))
|
||||||
return;
|
return ERROR_OK;
|
||||||
|
|
||||||
/* Avoid invalidating the register cache all the time. */
|
/* Avoid invalidating the register cache all the time. */
|
||||||
if (r->registers_initialized
|
if (r->registers_initialized
|
||||||
&& (!riscv_rtos_enabled(target) || (previous_hartid == hartid))
|
&& (!riscv_rtos_enabled(target) || (previous_hartid == hartid))
|
||||||
&& target->reg_cache->reg_list[GDB_REGNO_ZERO].size == (unsigned)riscv_xlen(target)
|
&& target->reg_cache->reg_list[GDB_REGNO_ZERO].size == (unsigned)riscv_xlen(target)
|
||||||
&& (!riscv_rtos_enabled(target) || (r->rtos_hartid != -1))) {
|
&& (!riscv_rtos_enabled(target) || (r->rtos_hartid != -1))) {
|
||||||
return;
|
return ERROR_OK;
|
||||||
} else
|
} else
|
||||||
LOG_DEBUG("Initializing registers: xlen=%d", riscv_xlen(target));
|
LOG_DEBUG("Initializing registers: xlen=%d", riscv_xlen(target));
|
||||||
|
|
||||||
riscv_invalidate_register_cache(target);
|
riscv_invalidate_register_cache(target);
|
||||||
|
return ERROR_OK;
|
||||||
}
|
}
|
||||||
|
|
||||||
void riscv_invalidate_register_cache(struct target *target)
|
void riscv_invalidate_register_cache(struct target *target)
|
||||||
|
@ -1775,7 +1794,8 @@ bool riscv_is_halted(struct target *target)
|
||||||
enum riscv_halt_reason riscv_halt_reason(struct target *target, int hartid)
|
enum riscv_halt_reason riscv_halt_reason(struct target *target, int hartid)
|
||||||
{
|
{
|
||||||
RISCV_INFO(r);
|
RISCV_INFO(r);
|
||||||
riscv_set_current_hartid(target, hartid);
|
if (riscv_set_current_hartid(target, hartid) != ERROR_OK)
|
||||||
|
return RISCV_HALT_ERROR;
|
||||||
if (!riscv_is_halted(target)) {
|
if (!riscv_is_halted(target)) {
|
||||||
LOG_ERROR("Hart is not halted!");
|
LOG_ERROR("Hart is not halted!");
|
||||||
return RISCV_HALT_UNKNOWN;
|
return RISCV_HALT_UNKNOWN;
|
||||||
|
|
|
@ -31,7 +31,8 @@ enum riscv_halt_reason {
|
||||||
RISCV_HALT_BREAKPOINT,
|
RISCV_HALT_BREAKPOINT,
|
||||||
RISCV_HALT_SINGLESTEP,
|
RISCV_HALT_SINGLESTEP,
|
||||||
RISCV_HALT_TRIGGER,
|
RISCV_HALT_TRIGGER,
|
||||||
RISCV_HALT_UNKNOWN
|
RISCV_HALT_UNKNOWN,
|
||||||
|
RISCV_HALT_ERROR
|
||||||
};
|
};
|
||||||
|
|
||||||
typedef struct {
|
typedef struct {
|
||||||
|
@ -93,7 +94,7 @@ typedef struct {
|
||||||
riscv_reg_t *value, int hid, int rid);
|
riscv_reg_t *value, int hid, int rid);
|
||||||
int (*set_register)(struct target *, int hartid, int regid,
|
int (*set_register)(struct target *, int hartid, int regid,
|
||||||
uint64_t value);
|
uint64_t value);
|
||||||
void (*select_current_hart)(struct target *);
|
int (*select_current_hart)(struct target *);
|
||||||
bool (*is_halted)(struct target *target);
|
bool (*is_halted)(struct target *target);
|
||||||
int (*halt_current_hart)(struct target *);
|
int (*halt_current_hart)(struct target *);
|
||||||
int (*resume_current_hart)(struct target *target);
|
int (*resume_current_hart)(struct target *target);
|
||||||
|
@ -191,7 +192,7 @@ bool riscv_rtos_enabled(const struct target *target);
|
||||||
|
|
||||||
/* Sets the current hart, which is the hart that will actually be used when
|
/* Sets the current hart, which is the hart that will actually be used when
|
||||||
* issuing debug commands. */
|
* issuing debug commands. */
|
||||||
void riscv_set_current_hartid(struct target *target, int hartid);
|
int riscv_set_current_hartid(struct target *target, int hartid);
|
||||||
int riscv_current_hartid(const struct target *target);
|
int riscv_current_hartid(const struct target *target);
|
||||||
|
|
||||||
/*** Support functions for the RISC-V 'RTOS', which provides multihart support
|
/*** Support functions for the RISC-V 'RTOS', which provides multihart support
|
||||||
|
|
Loading…
Reference in New Issue