- set the T bit in the CPSR when the core was executing in Thumb state. Mask the T bit from the CPSR for all CPSR-writing operations
git-svn-id: svn://svn.berlios.de/openocd/trunk@97 b42882b7-edfa-0310-969c-e2dbd0fdcd60
This commit is contained in:
drath
parent
50141aebfb
commit
83eeaa6280
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@ -930,12 +930,16 @@ int arm7_9_debug_entry(target_t *target)
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if ((retval = jtag_execute_queue()) != ERROR_OK)
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return retval;
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/* if the core has been executing in Thumb state, set the T bit */
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if (armv4_5->core_state == ARMV4_5_STATE_THUMB)
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cpsr |= 0x20;
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buf_set_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32, cpsr);
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armv4_5->core_cache->reg_list[ARMV4_5_CPSR].dirty = 0;
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armv4_5->core_cache->reg_list[ARMV4_5_CPSR].valid = 1;
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armv4_5->core_mode = cpsr & 0x1f;
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DEBUG("target entered debug state in %s mode", armv4_5_mode_strings[armv4_5_mode_to_number(armv4_5->core_mode)]);
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if (armv4_5_mode_to_number(armv4_5->core_mode) == -1)
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{
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@ -943,6 +947,8 @@ int arm7_9_debug_entry(target_t *target)
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ERROR("cpsr contains invalid mode value - communication failure");
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return ERROR_TARGET_FAILURE;
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}
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DEBUG("target entered debug state in %s mode", armv4_5_mode_strings[armv4_5_mode_to_number(armv4_5->core_mode)]);
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if (armv4_5->core_state == ARMV4_5_STATE_THUMB)
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{
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@ -1040,9 +1046,10 @@ int arm7_9_full_context(target_t *target)
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{
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u32 tmp_cpsr;
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/* change processor mode */
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/* change processor mode (and mask T bit) */
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tmp_cpsr = buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8) & 0xE0;
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tmp_cpsr |= armv4_5_number_to_mode(i);
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tmp_cpsr &= ~0x20;
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arm7_9->write_xpsr_im8(target, tmp_cpsr & 0xff, 0, 0);
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for (j = 0; j < 15; j++)
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@ -1070,8 +1077,8 @@ int arm7_9_full_context(target_t *target)
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}
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}
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/* restore processor mode */
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arm7_9->write_xpsr_im8(target, buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8), 0, 0);
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/* restore processor mode (mask T bit) */
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arm7_9->write_xpsr_im8(target, buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8) & ~0x20, 0, 0);
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if ((retval = jtag_execute_queue()) != ERROR_OK)
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{
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@ -1150,9 +1157,10 @@ int arm7_9_restore_context(target_t *target)
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{
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u32 tmp_cpsr;
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/* change processor mode */
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/* change processor mode (mask T bit) */
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tmp_cpsr = buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8) & 0xE0;
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tmp_cpsr |= armv4_5_number_to_mode(i);
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tmp_cpsr &= ~0x20;
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arm7_9->write_xpsr_im8(target, tmp_cpsr & 0xff, 0, 0);
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current_mode = armv4_5_number_to_mode(i);
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}
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@ -1191,19 +1199,20 @@ int arm7_9_restore_context(target_t *target)
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if ((armv4_5->core_cache->reg_list[ARMV4_5_CPSR].dirty == 0) && (armv4_5->core_mode != current_mode))
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{
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/* restore processor mode */
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/* restore processor mode (mask T bit) */
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u32 tmp_cpsr;
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tmp_cpsr = buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8) & 0xE0;
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tmp_cpsr |= armv4_5_number_to_mode(i);
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tmp_cpsr &= ~0x20;
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DEBUG("writing lower 8 bit of cpsr with value 0x%2.2x", tmp_cpsr);
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arm7_9->write_xpsr_im8(target, tmp_cpsr & 0xff, 0, 0);
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}
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else if (armv4_5->core_cache->reg_list[ARMV4_5_CPSR].dirty == 1)
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{
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/* CPSR has been changed, full restore necessary */
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/* CPSR has been changed, full restore necessary (mask T bit) */
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DEBUG("writing cpsr with value 0x%8.8x", buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32));
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arm7_9->write_xpsr(target, buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32), 0);
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arm7_9->write_xpsr(target, buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32) & ~0x20, 0);
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armv4_5->core_cache->reg_list[ARMV4_5_CPSR].dirty = 0;
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armv4_5->core_cache->reg_list[ARMV4_5_CPSR].valid = 1;
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}
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@ -1514,9 +1523,10 @@ int arm7_9_read_core_reg(struct target_s *target, int num, enum armv4_5_mode mod
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{
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u32 tmp_cpsr;
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/* change processor mode */
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/* change processor mode (mask T bit) */
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tmp_cpsr = buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8) & 0xE0;
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tmp_cpsr |= mode;
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tmp_cpsr &= ~0x20;
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arm7_9->write_xpsr_im8(target, tmp_cpsr & 0xff, 0, 0);
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}
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@ -1544,8 +1554,8 @@ int arm7_9_read_core_reg(struct target_s *target, int num, enum armv4_5_mode mod
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if ((mode != ARMV4_5_MODE_ANY)
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&& (mode != armv4_5->core_mode)
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&& (reg_mode != ARMV4_5_MODE_ANY)) {
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/* restore processor mode */
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arm7_9->write_xpsr_im8(target, buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8), 0, 0);
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/* restore processor mode (mask T bit) */
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arm7_9->write_xpsr_im8(target, buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8) & ~0x20, 0, 0);
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}
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if ((retval = jtag_execute_queue()) != ERROR_OK)
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@ -1574,9 +1584,10 @@ int arm7_9_write_core_reg(struct target_s *target, int num, enum armv4_5_mode mo
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&& (reg_mode != ARMV4_5_MODE_ANY)) {
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u32 tmp_cpsr;
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/* change processor mode */
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/* change processor mode (mask T bit) */
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tmp_cpsr = buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8) & 0xE0;
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tmp_cpsr |= mode;
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tmp_cpsr &= ~0x20;
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arm7_9->write_xpsr_im8(target, tmp_cpsr & 0xff, 0, 0);
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}
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@ -1595,6 +1606,10 @@ int arm7_9_write_core_reg(struct target_s *target, int num, enum armv4_5_mode mo
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armv4_5_core_reg_t *arch_info = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, mode, num).arch_info;
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int spsr = (arch_info->mode == ARMV4_5_MODE_ANY) ? 0 : 1;
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/* if we're writing the CPSR, mask the T bit */
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if (!spsr)
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value &= ~0x20;
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arm7_9->write_xpsr(target, value, spsr);
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}
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@ -1604,8 +1619,8 @@ int arm7_9_write_core_reg(struct target_s *target, int num, enum armv4_5_mode mo
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if ((mode != ARMV4_5_MODE_ANY)
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&& (mode != armv4_5->core_mode)
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&& (reg_mode != ARMV4_5_MODE_ANY)) {
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/* restore processor mode */
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arm7_9->write_xpsr_im8(target, buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8), 0, 0);
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/* restore processor mode (mask T bit) */
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arm7_9->write_xpsr_im8(target, buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8) & ~0x20, 0, 0);
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}
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if ((retval = jtag_execute_queue()) != ERROR_OK)
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@ -1755,7 +1770,7 @@ int arm7_9_read_memory(struct target_s *target, u32 address, u32 size, u32 count
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{
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ERROR("memory read caused data abort");
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arm7_9->write_xpsr_im8(target, buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8), 0, 0);
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arm7_9->write_xpsr_im8(target, buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8) & ~0x20, 0, 0);
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return ERROR_TARGET_DATA_ABORT;
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}
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@ -1920,7 +1935,7 @@ int arm7_9_write_memory(struct target_s *target, u32 address, u32 size, u32 coun
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{
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ERROR("memory write caused data abort");
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arm7_9->write_xpsr_im8(target, buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8), 0, 0);
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arm7_9->write_xpsr_im8(target, buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8) & ~0x20, 0, 0);
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return ERROR_TARGET_DATA_ABORT;
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}
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@ -2059,6 +2074,10 @@ int handle_arm7_9_write_xpsr_command(struct command_context_s *cmd_ctx, char *cm
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value = strtoul(args[0], NULL, 0);
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spsr = strtol(args[1], NULL, 0);
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/* if we're writing the CPSR, mask the T bit */
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if (!spsr)
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value &= ~0x20;
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arm7_9->write_xpsr(target, value, spsr);
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if ((retval = jtag_execute_queue()) != ERROR_OK)
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{
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@ -2100,7 +2119,7 @@ int handle_arm7_9_write_xpsr_im8_command(struct command_context_s *cmd_ctx, char
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value = strtoul(args[0], NULL, 0);
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rotate = strtol(args[1], NULL, 0);
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spsr = strtol(args[2], NULL, 0);
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arm7_9->write_xpsr_im8(target, value, rotate, spsr);
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if ((retval = jtag_execute_queue()) != ERROR_OK)
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{
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