target/riscv: use struct riscv_info instead of typedef riscv_info_t
Make the main RISC-V structure more compliant with OpenOCD coding style. Other typedefs remains as is. Change-Id: I5657ad28fea8108fd66ab27b2dfe1c868dc5805b Signed-off-by: Tomas Vanek <vanekt@fbl.cz> Reviewed-on: https://review.openocd.org/c/openocd/+/6998 Tested-by: jenkins Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-by: Tim Newsome <tim@sifive.com>
This commit is contained in:
Tomas Vanek
parent
2c6571b9b1
commit
82e76262a1
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@ -227,10 +227,10 @@ static int get_register(struct target *target, riscv_reg_t *value, int regid);
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static riscv011_info_t *get_info(const struct target *target)
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{
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riscv_info_t *info = (riscv_info_t *) target->arch_info;
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struct riscv_info *info = target->arch_info;
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assert(info);
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assert(info->version_specific);
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return (riscv011_info_t *) info->version_specific;
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return info->version_specific;
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}
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static unsigned int slot_offset(const struct target *target, slot_t slot)
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@ -1408,7 +1408,10 @@ static int halt(struct target *target)
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static void deinit_target(struct target *target)
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{
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LOG_DEBUG("riscv_deinit_target()");
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riscv_info_t *info = (riscv_info_t *) target->arch_info;
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struct riscv_info *info = target->arch_info;
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if (!info)
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return;
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free(info->version_specific);
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info->version_specific = NULL;
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}
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@ -1549,7 +1552,7 @@ static int examine(struct target *target)
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uint32_t word0 = cache_get32(target, 0);
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uint32_t word1 = cache_get32(target, 1);
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riscv_info_t *generic_info = (riscv_info_t *) target->arch_info;
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struct riscv_info *generic_info = riscv_info(target);
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if (word0 == 1 && word1 == 0) {
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generic_info->xlen = 32;
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} else if (word0 == 0xffffffff && word1 == 3) {
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@ -34,7 +34,7 @@ static int riscv013_step_or_resume_current_hart(struct target *target,
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bool step, bool use_hasel);
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static void riscv013_clear_abstract_error(struct target *target);
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/* Implementations of the functions in riscv_info_t. */
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/* Implementations of the functions in struct riscv_info. */
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static int riscv013_get_register(struct target *target,
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riscv_reg_t *value, int rid);
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static int riscv013_set_register(struct target *target, int regid, uint64_t value);
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@ -225,10 +225,10 @@ LIST_HEAD(dm_list);
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static riscv013_info_t *get_info(const struct target *target)
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{
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riscv_info_t *info = (riscv_info_t *) target->arch_info;
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struct riscv_info *info = target->arch_info;
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assert(info);
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assert(info->version_specific);
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return (riscv013_info_t *) info->version_specific;
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return info->version_specific;
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}
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/**
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@ -1524,7 +1524,10 @@ static int wait_for_authbusy(struct target *target, uint32_t *dmstatus)
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static void deinit_target(struct target *target)
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{
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LOG_DEBUG("riscv_deinit_target()");
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riscv_info_t *info = (riscv_info_t *) target->arch_info;
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struct riscv_info *info = target->arch_info;
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if (!info)
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return;
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free(info->version_specific);
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/* TODO: free register arch_info */
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info->version_specific = NULL;
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@ -4173,7 +4176,7 @@ static int select_prepped_harts(struct target *target, bool *use_hasel)
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unsigned total_selected = 0;
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list_for_each_entry(entry, &dm->target_list, list) {
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struct target *t = entry->target;
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riscv_info_t *r = riscv_info(t);
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struct riscv_info *r = riscv_info(t);
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riscv013_info_t *info = get_info(t);
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unsigned index = info->index;
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LOG_DEBUG("index=%d, coreid=%d, prepped=%d", index, t->coreid, r->prepped);
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@ -405,13 +405,12 @@ static uint32_t dtmcontrol_scan(struct target *target, uint32_t out)
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static struct target_type *get_target_type(struct target *target)
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{
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riscv_info_t *info = (riscv_info_t *) target->arch_info;
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if (!info) {
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if (!target->arch_info) {
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LOG_ERROR("Target has not been initialized");
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return NULL;
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}
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RISCV_INFO(info);
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switch (info->dtm_version) {
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case 0:
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return &riscv011_target;
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@ -426,7 +425,7 @@ static struct target_type *get_target_type(struct target *target)
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static int riscv_create_target(struct target *target, Jim_Interp *interp)
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{
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LOG_DEBUG("riscv_create_target()");
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target->arch_info = calloc(1, sizeof(riscv_info_t));
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target->arch_info = calloc(1, sizeof(struct riscv_info));
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if (!target->arch_info) {
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LOG_ERROR("Failed to allocate RISC-V target structure.");
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return ERROR_FAIL;
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@ -489,14 +488,17 @@ static void riscv_deinit_target(struct target *target)
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{
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LOG_DEBUG("riscv_deinit_target()");
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riscv_info_t *info = target->arch_info;
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struct riscv_info *info = target->arch_info;
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struct target_type *tt = get_target_type(target);
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if (tt && info->version_specific)
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if (tt && info && info->version_specific)
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tt->deinit_target(target);
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riscv_free_registers(target);
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if (!info)
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return;
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range_list_t *entry, *tmp;
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list_for_each_entry_safe(entry, tmp, &info->expose_csr, list) {
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free(entry->name);
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@ -1200,7 +1202,7 @@ int riscv_halt_go_all_harts(struct target *target)
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int halt_go(struct target *target)
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{
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riscv_info_t *r = riscv_info(target);
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RISCV_INFO(r);
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int result;
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if (!r->is_halted) {
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struct target_type *tt = get_target_type(target);
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@ -1242,7 +1244,7 @@ int riscv_halt(struct target *target)
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foreach_smp_target(tlist, target->smp_targets) {
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struct target *t = tlist->target;
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riscv_info_t *i = riscv_info(t);
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struct riscv_info *i = riscv_info(t);
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if (i->prepped) {
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if (halt_go(t) != ERROR_OK)
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result = ERROR_FAIL;
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@ -1434,7 +1436,7 @@ static int resume_prep(struct target *target, int current,
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static int resume_go(struct target *target, int current,
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target_addr_t address, int handle_breakpoints, int debug_execution)
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{
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riscv_info_t *r = riscv_info(target);
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RISCV_INFO(r);
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int result;
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if (!r->is_halted) {
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struct target_type *tt = get_target_type(target);
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@ -1483,7 +1485,7 @@ int riscv_resume(
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foreach_smp_target_direction(resume_order == RO_NORMAL,
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tlist, target->smp_targets) {
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struct target *t = tlist->target;
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riscv_info_t *i = riscv_info(t);
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struct riscv_info *i = riscv_info(t);
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if (i->prepped) {
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if (resume_go(t, current, address, handle_breakpoints,
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debug_execution) != ERROR_OK)
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@ -2189,7 +2191,7 @@ int riscv_openocd_poll(struct target *target)
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struct target_list *list;
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foreach_smp_target(list, target->smp_targets) {
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struct target *t = list->target;
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riscv_info_t *r = riscv_info(t);
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struct riscv_info *r = riscv_info(t);
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enum riscv_poll_hart out = riscv_poll_hart(t, r->current_hartid);
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switch (out) {
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case RPH_NO_CHANGE:
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@ -3197,7 +3199,7 @@ struct target_type riscv_target = {
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/*** RISC-V Interface ***/
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void riscv_info_init(struct target *target, riscv_info_t *r)
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void riscv_info_init(struct target *target, struct riscv_info *r)
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{
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memset(r, 0, sizeof(*r));
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r->dtm_version = 1;
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@ -85,7 +85,7 @@ typedef struct {
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char *name;
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} range_list_t;
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typedef struct {
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struct riscv_info {
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unsigned dtm_version;
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struct command_context *cmd_ctx;
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@ -225,7 +225,7 @@ typedef struct {
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riscv_sample_config_t sample_config;
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struct riscv_sample_buf sample_buf;
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} riscv_info_t;
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};
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COMMAND_HELPER(riscv_print_info_line, const char *section, const char *key,
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unsigned int value);
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@ -261,13 +261,13 @@ extern bool riscv_ebreaku;
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/* Everything needs the RISC-V specific info structure, so here's a nice macro
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* that provides that. */
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static inline riscv_info_t *riscv_info(const struct target *target) __attribute__((unused));
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static inline riscv_info_t *riscv_info(const struct target *target)
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static inline struct riscv_info *riscv_info(const struct target *target) __attribute__((unused));
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static inline struct riscv_info *riscv_info(const struct target *target)
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{
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assert(target->arch_info);
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return target->arch_info;
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}
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#define RISCV_INFO(R) riscv_info_t *R = riscv_info(target);
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#define RISCV_INFO(R) struct riscv_info *R = riscv_info(target);
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extern uint8_t ir_dtmcontrol[4];
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extern struct scan_field select_dtmcontrol;
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@ -313,7 +313,7 @@ int riscv_openocd_deassert_reset(struct target *target);
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/*** RISC-V Interface ***/
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/* Initializes the shared RISC-V structure. */
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void riscv_info_init(struct target *target, riscv_info_t *r);
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void riscv_info_init(struct target *target, struct riscv_info *r);
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/* Steps the hart that's currently selected in the RTOS, or if there is no RTOS
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* then the only hart. */
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