interesting
/
riscv-openocd
1
0
Fork 0
Code Issues Pull Requests Projects Releases Wiki Activity

arm926ejs: fix gaffe when converting from arm926ejs cp15 to mcr 

the first arg is the register number 15 = cp15.

Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
This commit is contained in:
Øyvind Harboe 2009-11-23 18:23:10 +01:00
parent eeb4276deb
commit 828d006a9d
3 changed files with 3 additions and 3 deletions

2
tcl/board/dm355evm.cfg
View File

@ -182,7 +182,7 @@ proc dm355evm_init {} {
######################## ########################
# turn on icache - set I bit in cp15 register c1 # turn on icache - set I bit in cp15 register c1
mcr 0 0 1 0 0x00051078 mcr 15 0 0 1 0 0x00051078
} }
# NAND -- socket has two chipselects, MT29F16G08FAA puts 1GByte on each one. # NAND -- socket has two chipselects, MT29F16G08FAA puts 1GByte on each one.

2
tcl/board/openrd.cfg
View File

@ -29,7 +29,7 @@ proc openrd_init { } {
jtag_reset 0 0 jtag_reset 0 0
wait_halt wait_halt
mcr 0 0 1 0 0x00052078 mcr 15 0 0 1 0 0x00052078
mww 0xD0001400 0x43000C30 # DDR SDRAM Configuration Register mww 0xD0001400 0x43000C30 # DDR SDRAM Configuration Register
mww 0xD0001404 0x37543000 # Dunit Control Low Register mww 0xD0001404 0x37543000 # Dunit Control Low Register

2
tcl/board/sheevaplug.cfg
View File

@ -29,7 +29,7 @@ proc sheevaplug_init { } {
jtag_reset 0 0 jtag_reset 0 0
wait_halt wait_halt
mcr 0 0 1 0 0x00052078 mcr 15 0 0 1 0 0x00052078
mww 0xD0001400 0x43000C30 # DDR SDRAM Configuration Register mww 0xD0001400 0x43000C30 # DDR SDRAM Configuration Register
mww 0xD0001404 0x39543000 # Dunit Control Low Register mww 0xD0001404 0x39543000 # Dunit Control Low Register