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Add opcodes for load/store registers words immediate post-indexed 

Signed-off-by: Luca Ellero <lroluk@gmail.com>
This commit is contained in:
Luca Ellero 2011-04-13 18:55:18 +00:00 committed by Øyvind Harboe
parent 041953f3b1
commit 81f238f522
1 changed files with 12 additions and 0 deletions
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12
src/target/arm_opcodes.h Normal file → Executable file
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@ -86,6 +86,12 @@
#define ARMV4_5_MSR_IM(Im, Rotate, Field, R) \ #define ARMV4_5_MSR_IM(Im, Rotate, Field, R) \
(0xe320f000 | (Im) | ((Rotate) << 8) | ((Field) << 16) | ((R) << 22)) (0xe320f000 | (Im) | ((Rotate) << 8) | ((Field) << 16) | ((R) << 22))
/* Load Register Word Immediate Post-Index
* Rd: register to load
* Rn: base register
*/
#define ARMV4_5_LDRW_IP(Rd, Rn) (0xe4900004 | ((Rd) << 12) | ((Rn) << 16))
/* Load Register Halfword Immediate Post-Index /* Load Register Halfword Immediate Post-Index
* Rd: register to load * Rd: register to load
* Rn: base register * Rn: base register
@ -98,6 +104,12 @@
*/ */
#define ARMV4_5_LDRB_IP(Rd, Rn) (0xe4d00001 | ((Rd) << 12) | ((Rn) << 16)) #define ARMV4_5_LDRB_IP(Rd, Rn) (0xe4d00001 | ((Rd) << 12) | ((Rn) << 16))
/* Store register Word Immediate Post-Index
* Rd: register to store
* Rn: base register
*/
#define ARMV4_5_STRW_IP(Rd, Rn) (0xe4800004 | ((Rd) << 12) | ((Rn) << 16))
/* Store register Halfword Immediate Post-Index /* Store register Halfword Immediate Post-Index
* Rd: register to store * Rd: register to store
* Rn: base register * Rn: base register