arm_adi_v5: reduce some CSW writes
MEM-AP access through banked data registers MEM_AP_REG_BD0..3 does not increment TAR regardless of the current autoincrement mode. mem_ap_read_u32() and mem_ap_write_u32() can keep the current autoincrement mode instead of switching autoincrement off. Change-Id: Ib7ec688d3e04f1da678363cd2819ce90e8910e58 Signed-off-by: Tomas Vanek <vanekt@fbl.cz> Reviewed-on: http://openocd.zylin.com/4163 Tested-by: jenkins Reviewed-by: Andreas Bolsch <hyphen0break@gmail.com> Reviewed-by: Christopher Head <chead@zaber.com> Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
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@ -221,7 +221,8 @@ int mem_ap_read_u32(struct adiv5_ap *ap, uint32_t address,
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/* Use banked addressing (REG_BDx) to avoid some link traffic
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/* Use banked addressing (REG_BDx) to avoid some link traffic
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* (updating TAR) when reading several consecutive addresses.
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* (updating TAR) when reading several consecutive addresses.
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*/
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*/
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retval = mem_ap_setup_transfer(ap, CSW_32BIT | CSW_ADDRINC_OFF,
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retval = mem_ap_setup_transfer(ap,
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CSW_32BIT | (ap->csw_value & CSW_ADDRINC_MASK),
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address & 0xFFFFFFF0);
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address & 0xFFFFFFF0);
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if (retval != ERROR_OK)
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if (retval != ERROR_OK)
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return retval;
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return retval;
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@ -272,7 +273,8 @@ int mem_ap_write_u32(struct adiv5_ap *ap, uint32_t address,
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/* Use banked addressing (REG_BDx) to avoid some link traffic
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/* Use banked addressing (REG_BDx) to avoid some link traffic
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* (updating TAR) when writing several consecutive addresses.
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* (updating TAR) when writing several consecutive addresses.
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*/
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*/
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retval = mem_ap_setup_transfer(ap, CSW_32BIT | CSW_ADDRINC_OFF,
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retval = mem_ap_setup_transfer(ap,
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CSW_32BIT | (ap->csw_value & CSW_ADDRINC_MASK),
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address & 0xFFFFFFF0);
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address & 0xFFFFFFF0);
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if (retval != ERROR_OK)
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if (retval != ERROR_OK)
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return retval;
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return retval;
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