Merge pull request #883 from zqb-all/update_macro
target/riscv: update some macro
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commit
8032b78775
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@ -10596,11 +10596,9 @@ addreg rtest 0x1234 org.gnu.gdb.or1k.group0 system
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@section RISC-V Architecture
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@uref{http://riscv.org/, RISC-V} is a free and open ISA. OpenOCD supports JTAG
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debug of RV32 and RV64 cores in heterogeneous multicore systems of up to 32
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harts. (It's possible to increase this limit to 1024 by changing
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RISCV_MAX_HARTS in riscv.h.) OpenOCD primarily supports 0.13 of the RISC-V
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Debug Specification, but there is also support for legacy targets that
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implement version 0.11.
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debug of RV32 and RV64 cores in heterogeneous multicore systems of up to 2^20
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harts. OpenOCD primarily supports 0.13 of the RISC-V Debug Specification,
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but there is also support for legacy targets that implement version 0.11.
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@subsection RISC-V Terminology
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@ -4448,9 +4448,9 @@ static int select_prepped_harts(struct target *target)
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assert(dm->hart_count);
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unsigned hawindow_count = (dm->hart_count + 31) / 32;
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uint32_t hawindow[hawindow_count];
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memset(hawindow, 0, sizeof(uint32_t) * hawindow_count);
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uint32_t *hawindow = calloc(hawindow_count, sizeof(uint32_t));
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if (!hawindow)
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return ERROR_FAIL;
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target_list_t *entry;
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unsigned total_selected = 0;
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@ -4472,22 +4472,31 @@ static int select_prepped_harts(struct target *target)
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if (total_selected == 0) {
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LOG_TARGET_ERROR(target, "No harts were prepped!");
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free(hawindow);
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return ERROR_FAIL;
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} else if (total_selected == 1) {
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/* Don't use hasel if we only need to talk to one hart. */
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free(hawindow);
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return dm013_select_hart(target, selected_index);
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}
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if (dm013_select_hart(target, HART_INDEX_MULTIPLE) != ERROR_OK)
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if (dm013_select_hart(target, HART_INDEX_MULTIPLE) != ERROR_OK) {
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free(hawindow);
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return ERROR_FAIL;
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for (unsigned i = 0; i < hawindow_count; i++) {
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if (dmi_write(target, DM_HAWINDOWSEL, i) != ERROR_OK)
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return ERROR_FAIL;
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if (dmi_write(target, DM_HAWINDOW, hawindow[i]) != ERROR_OK)
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return ERROR_FAIL;
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}
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for (unsigned i = 0; i < hawindow_count; i++) {
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if (dmi_write(target, DM_HAWINDOWSEL, i) != ERROR_OK) {
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free(hawindow);
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return ERROR_FAIL;
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}
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if (dmi_write(target, DM_HAWINDOW, hawindow[i]) != ERROR_OK) {
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free(hawindow);
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return ERROR_FAIL;
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}
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}
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free(hawindow);
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return ERROR_OK;
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}
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@ -12,12 +12,11 @@ struct riscv_program;
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#include "target/register.h"
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#include "target/semihosting_common.h"
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#include <helper/command.h>
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#include <helper/bits.h>
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#define RISCV_COMMON_MAGIC 0x52495356U
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/* The register cache is statically allocated. */
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#define RISCV_MAX_HARTS 1024
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#define RISCV_MAX_REGISTERS 5000
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#define RISCV_MAX_HARTS ((int)BIT(20))
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#define RISCV_MAX_TRIGGERS 32
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#define RISCV_MAX_HWBPS 16
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@ -30,7 +29,7 @@ struct riscv_program;
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#define RISCV_HGATP_PPN(xlen) ((xlen) == 32 ? HGATP32_PPN : HGATP64_PPN)
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#define RISCV_PGSHIFT 12
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# define PG_MAX_LEVEL 4
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#define PG_MAX_LEVEL 4
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#define RISCV_NUM_MEM_ACCESS_METHODS 3
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