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arm7_9_common_t -> struct arm7_9_common 

Remove misleading typedef and redundant suffix from struct arm7_9_common.
This commit is contained in:
Zachary T Welch 2009-11-13 08:40:03 -08:00
parent bcb18b2044
commit 8012b3963f
16 changed files with 138 additions and 138 deletions
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2
src/flash/ocl.c
View File

@ -48,7 +48,7 @@ FLASH_BANK_COMMAND_HANDLER(ocl_flash_bank_command)
{
int retval;
armv4_5_common_t *armv4_5;
arm7_9_common_t *arm7_9;
struct arm7_9_common *arm7_9;
struct ocl_priv *ocl;
if (argc < 6)

2
src/flash/str9xpec.c
View File

@ -239,7 +239,7 @@ FLASH_BANK_COMMAND_HANDLER(str9xpec_flash_bank_command)
{
struct str9xpec_flash_controller *str9xpec_info;
armv4_5_common_t *armv4_5 = NULL;
arm7_9_common_t *arm7_9 = NULL;
struct arm7_9_common *arm7_9 = NULL;
arm_jtag_t *jtag_info = NULL;
if (argc < 6)

2
src/target/arm720t.c
View File

@ -380,7 +380,7 @@ static int arm720t_init_arch_info(target_t *target,
struct arm720t_common *arm720t, struct jtag_tap *tap)
{
arm7tdmi_common_t *arm7tdmi = &arm720t->arm7tdmi_common;
arm7_9_common_t *arm7_9 = &arm7tdmi->arm7_9_common;
struct arm7_9_common *arm7_9 = &arm7tdmi->arm7_9_common;
arm7tdmi_init_arch_info(target, arm7tdmi, tap);

88
src/target/arm7_9_common.c
View File

@ -45,7 +45,7 @@ int arm7_9_debug_entry(target_t *target);
* @param arm7_9 Pointer to the common struct for an ARM7/9 target
* @return JTAG error status after executing queue
*/
static int arm7_9_clear_watchpoints(arm7_9_common_t *arm7_9)
static int arm7_9_clear_watchpoints(struct arm7_9_common *arm7_9)
{
LOG_DEBUG("-");
embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], 0x0);
@ -66,7 +66,7 @@ static int arm7_9_clear_watchpoints(arm7_9_common_t *arm7_9)
* @param arm7_9 Pointer to the common struct for an ARM7/9 target
* @param breakpoint Pointer to the breakpoint to be used as a watchpoint
*/
static void arm7_9_assign_wp(arm7_9_common_t *arm7_9, breakpoint_t *breakpoint)
static void arm7_9_assign_wp(struct arm7_9_common *arm7_9, breakpoint_t *breakpoint)
{
if (!arm7_9->wp0_used)
{
@ -97,7 +97,7 @@ static void arm7_9_assign_wp(arm7_9_common_t *arm7_9, breakpoint_t *breakpoint)
* @return Error codes if there is a problem finding a watchpoint or the result
* of executing the JTAG queue
*/
static int arm7_9_set_software_breakpoints(arm7_9_common_t *arm7_9)
static int arm7_9_set_software_breakpoints(struct arm7_9_common *arm7_9)
{
if (arm7_9->sw_breakpoints_added)
{
@ -161,7 +161,7 @@ static int arm7_9_set_software_breakpoints(arm7_9_common_t *arm7_9)
*/
int arm7_9_setup(target_t *target)
{
struct arm7_9_common_s *arm7_9 = target_to_arm7_9(target);
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
return arm7_9_clear_watchpoints(arm7_9);
}
@ -178,9 +178,9 @@ int arm7_9_setup(target_t *target)
* targets
* @return ERROR_OK if successful
*/
int arm7_9_get_arch_pointers(target_t *target, armv4_5_common_t **armv4_5_p, arm7_9_common_t **arm7_9_p)
int arm7_9_get_arch_pointers(target_t *target, armv4_5_common_t **armv4_5_p, struct arm7_9_common **arm7_9_p)
{
struct arm7_9_common_s *arm7_9 = target_to_arm7_9(target);
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
struct armv4_5_common_s *armv4_5 = &arm7_9->armv4_5_common;
/* FIXME stop using this routine; just target_to_arm7_9() and
@ -212,7 +212,7 @@ int arm7_9_get_arch_pointers(target_t *target, armv4_5_common_t **armv4_5_p, arm
*/
int arm7_9_set_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
{
struct arm7_9_common_s *arm7_9 = target_to_arm7_9(target);
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
int retval = ERROR_OK;
LOG_DEBUG("BPID: %d, Address: 0x%08" PRIx32 ", Type: %d" ,
@ -342,7 +342,7 @@ int arm7_9_set_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
int arm7_9_unset_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
{
int retval = ERROR_OK;
struct arm7_9_common_s *arm7_9 = target_to_arm7_9(target);
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
LOG_DEBUG("BPID: %d, Address: 0x%08" PRIx32,
breakpoint->unique_id,
@ -436,7 +436,7 @@ int arm7_9_unset_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
*/
int arm7_9_add_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
{
struct arm7_9_common_s *arm7_9 = target_to_arm7_9(target);
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
if (target->state != TARGET_HALTED)
{
@ -487,7 +487,7 @@ int arm7_9_add_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
int arm7_9_remove_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
{
int retval = ERROR_OK;
struct arm7_9_common_s *arm7_9 = target_to_arm7_9(target);
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
if ((retval = arm7_9_unset_breakpoint(target, breakpoint)) != ERROR_OK)
{
@ -523,7 +523,7 @@ int arm7_9_remove_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
int arm7_9_set_watchpoint(struct target_s *target, watchpoint_t *watchpoint)
{
int retval = ERROR_OK;
struct arm7_9_common_s *arm7_9 = target_to_arm7_9(target);
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
int rw_mask = 1;
uint32_t mask;
@ -594,7 +594,7 @@ int arm7_9_set_watchpoint(struct target_s *target, watchpoint_t *watchpoint)
int arm7_9_unset_watchpoint(struct target_s *target, watchpoint_t *watchpoint)
{
int retval = ERROR_OK;
struct arm7_9_common_s *arm7_9 = target_to_arm7_9(target);
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
if (target->state != TARGET_HALTED)
{
@ -641,7 +641,7 @@ int arm7_9_unset_watchpoint(struct target_s *target, watchpoint_t *watchpoint)
*/
int arm7_9_add_watchpoint(struct target_s *target, watchpoint_t *watchpoint)
{
struct arm7_9_common_s *arm7_9 = target_to_arm7_9(target);
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
if (target->state != TARGET_HALTED)
{
@ -675,7 +675,7 @@ int arm7_9_add_watchpoint(struct target_s *target, watchpoint_t *watchpoint)
int arm7_9_remove_watchpoint(struct target_s *target, watchpoint_t *watchpoint)
{
int retval = ERROR_OK;
struct arm7_9_common_s *arm7_9 = target_to_arm7_9(target);
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
if (watchpoint->set)
{
@ -702,7 +702,7 @@ int arm7_9_remove_watchpoint(struct target_s *target, watchpoint_t *watchpoint)
int arm7_9_execute_sys_speed(struct target_s *target)
{
int retval;
struct arm7_9_common_s *arm7_9 = target_to_arm7_9(target);
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
arm_jtag_t *jtag_info = &arm7_9->jtag_info;
reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
@ -755,7 +755,7 @@ int arm7_9_execute_fast_sys_speed(struct target_s *target)
static int set = 0;
static uint8_t check_value[4], check_mask[4];
struct arm7_9_common_s *arm7_9 = target_to_arm7_9(target);
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
arm_jtag_t *jtag_info = &arm7_9->jtag_info;
reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
@ -796,7 +796,7 @@ int arm7_9_execute_fast_sys_speed(struct target_s *target)
*/
int arm7_9_target_request_data(target_t *target, uint32_t size, uint8_t *buffer)
{
struct arm7_9_common_s *arm7_9 = target_to_arm7_9(target);
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
arm_jtag_t *jtag_info = &arm7_9->jtag_info;
uint32_t *data;
int retval = ERROR_OK;
@ -832,7 +832,7 @@ int arm7_9_handle_target_request(void *priv)
target_t *target = priv;
if (!target_was_examined(target))
return ERROR_OK;
struct arm7_9_common_s *arm7_9 = target_to_arm7_9(target);
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
arm_jtag_t *jtag_info = &arm7_9->jtag_info;
reg_t *dcc_control = &arm7_9->eice_cache->reg_list[EICE_COMMS_CTRL];
@ -890,7 +890,7 @@ int arm7_9_handle_target_request(void *priv)
int arm7_9_poll(target_t *target)
{
int retval;
struct arm7_9_common_s *arm7_9 = target_to_arm7_9(target);
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
/* read debug status register */
@ -982,7 +982,7 @@ int arm7_9_poll(target_t *target)
*/
int arm7_9_assert_reset(target_t *target)
{
struct arm7_9_common_s *arm7_9 = target_to_arm7_9(target);
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
LOG_DEBUG("target->state: %s",
target_state_name(target));
@ -1114,7 +1114,7 @@ int arm7_9_deassert_reset(target_t *target)
*/
int arm7_9_clear_halt(target_t *target)
{
struct arm7_9_common_s *arm7_9 = target_to_arm7_9(target);
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
reg_t *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL];
/* we used DBGRQ only if we didn't come out of reset */
@ -1171,7 +1171,7 @@ int arm7_9_clear_halt(target_t *target)
*/
int arm7_9_soft_reset_halt(struct target_s *target)
{
struct arm7_9_common_s *arm7_9 = target_to_arm7_9(target);
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
struct armv4_5_common_s *armv4_5 = &arm7_9->armv4_5_common;
reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
reg_t *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL];
@ -1290,7 +1290,7 @@ int arm7_9_halt(target_t *target)
return ERROR_OK;
}
struct arm7_9_common_s *arm7_9 = target_to_arm7_9(target);
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
reg_t *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL];
LOG_DEBUG("target->state: %s",
@ -1352,7 +1352,7 @@ int arm7_9_debug_entry(target_t *target)
uint32_t r0_thumb, pc_thumb;
uint32_t cpsr;
int retval;
struct arm7_9_common_s *arm7_9 = target_to_arm7_9(target);
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
struct armv4_5_common_s *armv4_5 = &arm7_9->armv4_5_common;
reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
reg_t *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL];
@ -1506,7 +1506,7 @@ int arm7_9_full_context(target_t *target)
{
int i;
int retval;
struct arm7_9_common_s *arm7_9 = target_to_arm7_9(target);
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
struct armv4_5_common_s *armv4_5 = &arm7_9->armv4_5_common;
LOG_DEBUG("-");
@ -1597,7 +1597,7 @@ int arm7_9_full_context(target_t *target)
*/
int arm7_9_restore_context(target_t *target)
{
struct arm7_9_common_s *arm7_9 = target_to_arm7_9(target);
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
struct armv4_5_common_s *armv4_5 = &arm7_9->armv4_5_common;
reg_t *reg;
armv4_5_core_reg_t *reg_arch_info;
@ -1747,7 +1747,7 @@ int arm7_9_restore_context(target_t *target)
*/
int arm7_9_restart_core(struct target_s *target)
{
struct arm7_9_common_s *arm7_9 = target_to_arm7_9(target);
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
arm_jtag_t *jtag_info = &arm7_9->jtag_info;
/* set RESTART instruction */
@ -1800,7 +1800,7 @@ void arm7_9_enable_breakpoints(struct target_s *target)
int arm7_9_resume(struct target_s *target, int current, uint32_t address, int handle_breakpoints, int debug_execution)
{
struct arm7_9_common_s *arm7_9 = target_to_arm7_9(target);
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
struct armv4_5_common_s *armv4_5 = &arm7_9->armv4_5_common;
breakpoint_t *breakpoint = target->breakpoints;
reg_t *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL];
@ -1960,7 +1960,7 @@ int arm7_9_resume(struct target_s *target, int current, uint32_t address, int ha
void arm7_9_enable_eice_step(target_t *target, uint32_t next_pc)
{
struct arm7_9_common_s *arm7_9 = target_to_arm7_9(target);
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
struct armv4_5_common_s *armv4_5 = &arm7_9->armv4_5_common;
uint32_t current_pc;
current_pc = buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32);
@ -1997,7 +1997,7 @@ void arm7_9_enable_eice_step(target_t *target, uint32_t next_pc)
void arm7_9_disable_eice_step(target_t *target)
{
struct arm7_9_common_s *arm7_9 = target_to_arm7_9(target);
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_MASK]);
embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_MASK]);
@ -2012,7 +2012,7 @@ void arm7_9_disable_eice_step(target_t *target)
int arm7_9_step(struct target_s *target, int current, uint32_t address, int handle_breakpoints)
{
struct arm7_9_common_s *arm7_9 = target_to_arm7_9(target);
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
struct armv4_5_common_s *armv4_5 = &arm7_9->armv4_5_common;
breakpoint_t *breakpoint = NULL;
int err, retval;
@ -2108,7 +2108,7 @@ int arm7_9_read_core_reg(struct target_s *target, int num, enum armv4_5_mode mod
uint32_t* reg_p[16];
uint32_t value;
int retval;
struct arm7_9_common_s *arm7_9 = target_to_arm7_9(target);
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
struct armv4_5_common_s *armv4_5 = &arm7_9->armv4_5_common;
if (armv4_5_mode_to_number(armv4_5->core_mode)==-1)
@ -2172,7 +2172,7 @@ int arm7_9_read_core_reg(struct target_s *target, int num, enum armv4_5_mode mod
int arm7_9_write_core_reg(struct target_s *target, int num, enum armv4_5_mode mode, uint32_t value)
{
uint32_t reg[16];
struct arm7_9_common_s *arm7_9 = target_to_arm7_9(target);
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
struct armv4_5_common_s *armv4_5 = &arm7_9->armv4_5_common;
if (armv4_5_mode_to_number(armv4_5->core_mode)==-1)
@ -2232,7 +2232,7 @@ int arm7_9_write_core_reg(struct target_s *target, int num, enum armv4_5_mode mo
int arm7_9_read_memory(struct target_s *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer)
{
struct arm7_9_common_s *arm7_9 = target_to_arm7_9(target);
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
struct armv4_5_common_s *armv4_5 = &arm7_9->armv4_5_common;
uint32_t reg[16];
uint32_t num_accesses = 0;
@ -2407,7 +2407,7 @@ int arm7_9_read_memory(struct target_s *target, uint32_t address, uint32_t size,
int arm7_9_write_memory(struct target_s *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer)
{
struct arm7_9_common_s *arm7_9 = target_to_arm7_9(target);
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
struct armv4_5_common_s *armv4_5 = &arm7_9->armv4_5_common;
reg_t *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL];
@ -2594,7 +2594,7 @@ static uint8_t *dcc_buffer;
static int arm7_9_dcc_completion(struct target_s *target, uint32_t exit_point, int timeout_ms, void *arch_info)
{
int retval = ERROR_OK;
struct arm7_9_common_s *arm7_9 = target_to_arm7_9(target);
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
if ((retval = target_wait_state(target, TARGET_DEBUG_RUNNING, 500)) != ERROR_OK)
return retval;
@ -2659,7 +2659,7 @@ int armv4_5_run_algorithm_inner(struct target_s *target, int num_mem_params, str
int arm7_9_bulk_write_memory(target_t *target, uint32_t address, uint32_t count, uint8_t *buffer)
{
int retval;
struct arm7_9_common_s *arm7_9 = target_to_arm7_9(target);
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
int i;
if (!arm7_9->dcc_downloads)
@ -2878,7 +2878,7 @@ COMMAND_HANDLER(handle_arm7_9_write_xpsr_command)
int retval;
target_t *target = get_current_target(cmd_ctx);
armv4_5_common_t *armv4_5;
arm7_9_common_t *arm7_9;
struct arm7_9_common *arm7_9;
if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
{
@ -2923,7 +2923,7 @@ COMMAND_HANDLER(handle_arm7_9_write_xpsr_im8_command)
int retval;
target_t *target = get_current_target(cmd_ctx);
armv4_5_common_t *armv4_5;
arm7_9_common_t *arm7_9;
struct arm7_9_common *arm7_9;
if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
{
@ -2964,7 +2964,7 @@ COMMAND_HANDLER(handle_arm7_9_write_core_reg_command)
int num;
target_t *target = get_current_target(cmd_ctx);
armv4_5_common_t *armv4_5;
arm7_9_common_t *arm7_9;
struct arm7_9_common *arm7_9;
if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
{
@ -2995,7 +2995,7 @@ COMMAND_HANDLER(handle_arm7_9_dbgrq_command)
{
target_t *target = get_current_target(cmd_ctx);
armv4_5_common_t *armv4_5;
arm7_9_common_t *arm7_9;
struct arm7_9_common *arm7_9;
if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
{
@ -3028,7 +3028,7 @@ COMMAND_HANDLER(handle_arm7_9_fast_memory_access_command)
{
target_t *target = get_current_target(cmd_ctx);
armv4_5_common_t *armv4_5;
arm7_9_common_t *arm7_9;
struct arm7_9_common *arm7_9;
if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
{
@ -3061,7 +3061,7 @@ COMMAND_HANDLER(handle_arm7_9_dcc_downloads_command)
{
target_t *target = get_current_target(cmd_ctx);
armv4_5_common_t *armv4_5;
arm7_9_common_t *arm7_9;
struct arm7_9_common *arm7_9;
if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
{
@ -3090,7 +3090,7 @@ COMMAND_HANDLER(handle_arm7_9_dcc_downloads_command)
return ERROR_OK;
}
int arm7_9_init_arch_info(target_t *target, arm7_9_common_t *arm7_9)
int arm7_9_init_arch_info(target_t *target, struct arm7_9_common *arm7_9)
{
int retval = ERROR_OK;
armv4_5_common_t *armv4_5 = &arm7_9->armv4_5_common;

12
src/target/arm7_9_common.h
View File

@ -37,7 +37,7 @@
/**
* Structure for items that are common between both ARM7 and ARM9 targets.
*/
typedef struct arm7_9_common_s
struct arm7_9_common
{
struct arm armv4_5_common;
uint32_t common_magic;
@ -106,12 +106,12 @@ typedef struct arm7_9_common_s
void (*post_restore_context)(target_t *target); /**< Callback function called after restoring the processor context */
} arm7_9_common_t;
};
static inline struct arm7_9_common_s *
static inline struct arm7_9_common *
target_to_arm7_9(struct target_s *target)
{
return container_of(target->arch_info, struct arm7_9_common_s,
return container_of(target->arch_info, struct arm7_9_common,
armv4_5_common);
}
@ -153,7 +153,7 @@ void arm7_9_disable_eice_step(target_t *target);
int arm7_9_execute_sys_speed(struct target_s *target);
int arm7_9_init_arch_info(target_t *target, arm7_9_common_t *arm7_9);
int arm7_9_get_arch_pointers(target_t *target, armv4_5_common_t **armv4_5_p, arm7_9_common_t **arm7_9_p);
int arm7_9_init_arch_info(target_t *target, struct arm7_9_common *arm7_9);
int arm7_9_get_arch_pointers(target_t *target, armv4_5_common_t **armv4_5_p, struct arm7_9_common **arm7_9_p);
#endif /* ARM7_9_COMMON_H */

38
src/target/arm7tdmi.c
View File

@ -44,7 +44,7 @@
static int arm7tdmi_examine_debug_reason(target_t *target)
{
int retval = ERROR_OK;
struct arm7_9_common_s *arm7_9 = target_to_arm7_9(target);
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
/* only check the debug reason if we don't know it already */
if ((target->debug_reason != DBG_REASON_DBGRQ)
@ -266,7 +266,7 @@ static int arm7tdmi_clock_data_in_endianness(arm_jtag_t *jtag_info,
static void arm7tdmi_change_to_arm(target_t *target,
uint32_t *r0, uint32_t *pc)
{
struct arm7_9_common_s *arm7_9 = target_to_arm7_9(target);
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
arm_jtag_t *jtag_info = &arm7_9->jtag_info;
/* save r0 before using it and put system in ARM state
@ -323,7 +323,7 @@ static void arm7tdmi_read_core_regs(target_t *target,
uint32_t mask, uint32_t* core_regs[16])
{
int i;
struct arm7_9_common_s *arm7_9 = target_to_arm7_9(target);
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
arm_jtag_t *jtag_info = &arm7_9->jtag_info;
/* STMIA r0-15, [r0] at debug speed
@ -348,7 +348,7 @@ static void arm7tdmi_read_core_regs_target_buffer(target_t *target,
uint32_t mask, void* buffer, int size)
{
int i;
struct arm7_9_common_s *arm7_9 = target_to_arm7_9(target);
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
arm_jtag_t *jtag_info = &arm7_9->jtag_info;
int be = (target->endianness == TARGET_BIG_ENDIAN) ? 1 : 0;
uint32_t *buf_u32 = buffer;
@ -388,7 +388,7 @@ static void arm7tdmi_read_core_regs_target_buffer(target_t *target,
static void arm7tdmi_read_xpsr(target_t *target, uint32_t *xpsr, int spsr)
{
struct arm7_9_common_s *arm7_9 = target_to_arm7_9(target);
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
arm_jtag_t *jtag_info = &arm7_9->jtag_info;
/* MRS r0, cpsr */
@ -406,7 +406,7 @@ static void arm7tdmi_read_xpsr(target_t *target, uint32_t *xpsr, int spsr)
static void arm7tdmi_write_xpsr(target_t *target, uint32_t xpsr, int spsr)
{
struct arm7_9_common_s *arm7_9 = target_to_arm7_9(target);
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
arm_jtag_t *jtag_info = &arm7_9->jtag_info;
LOG_DEBUG("xpsr: %8.8" PRIx32 ", spsr: %i", xpsr, spsr);
@ -436,7 +436,7 @@ static void arm7tdmi_write_xpsr(target_t *target, uint32_t xpsr, int spsr)
static void arm7tdmi_write_xpsr_im8(target_t *target,
uint8_t xpsr_im, int rot, int spsr)
{
struct arm7_9_common_s *arm7_9 = target_to_arm7_9(target);
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
arm_jtag_t *jtag_info = &arm7_9->jtag_info;
LOG_DEBUG("xpsr_im: %2.2x, rot: %i, spsr: %i", xpsr_im, rot, spsr);
@ -455,7 +455,7 @@ static void arm7tdmi_write_core_regs(target_t *target,
uint32_t mask, uint32_t core_regs[16])
{
int i;
struct arm7_9_common_s *arm7_9 = target_to_arm7_9(target);
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
arm_jtag_t *jtag_info = &arm7_9->jtag_info;
/* LDMIA r0-15, [r0] at debug speed
@ -479,7 +479,7 @@ static void arm7tdmi_write_core_regs(target_t *target,
static void arm7tdmi_load_word_regs(target_t *target, uint32_t mask)
{
struct arm7_9_common_s *arm7_9 = target_to_arm7_9(target);
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
arm_jtag_t *jtag_info = &arm7_9->jtag_info;
/* put system-speed load-multiple into the pipeline */
@ -490,7 +490,7 @@ static void arm7tdmi_load_word_regs(target_t *target, uint32_t mask)
static void arm7tdmi_load_hword_reg(target_t *target, int num)
{
struct arm7_9_common_s *arm7_9 = target_to_arm7_9(target);
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
arm_jtag_t *jtag_info = &arm7_9->jtag_info;
/* put system-speed load half-word into the pipeline */
@ -501,7 +501,7 @@ static void arm7tdmi_load_hword_reg(target_t *target, int num)
static void arm7tdmi_load_byte_reg(target_t *target, int num)
{
struct arm7_9_common_s *arm7_9 = target_to_arm7_9(target);
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
arm_jtag_t *jtag_info = &arm7_9->jtag_info;
/* put system-speed load byte into the pipeline */
@ -512,7 +512,7 @@ static void arm7tdmi_load_byte_reg(target_t *target, int num)
static void arm7tdmi_store_word_regs(target_t *target, uint32_t mask)
{
struct arm7_9_common_s *arm7_9 = target_to_arm7_9(target);
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
arm_jtag_t *jtag_info = &arm7_9->jtag_info;
/* put system-speed store-multiple into the pipeline */
@ -523,7 +523,7 @@ static void arm7tdmi_store_word_regs(target_t *target, uint32_t mask)
static void arm7tdmi_store_hword_reg(target_t *target, int num)
{
struct arm7_9_common_s *arm7_9 = target_to_arm7_9(target);
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
arm_jtag_t *jtag_info = &arm7_9->jtag_info;
/* put system-speed store half-word into the pipeline */
@ -534,7 +534,7 @@ static void arm7tdmi_store_hword_reg(target_t *target, int num)
static void arm7tdmi_store_byte_reg(target_t *target, int num)
{
struct arm7_9_common_s *arm7_9 = target_to_arm7_9(target);
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
arm_jtag_t *jtag_info = &arm7_9->jtag_info;
/* put system-speed store byte into the pipeline */
@ -545,7 +545,7 @@ static void arm7tdmi_store_byte_reg(target_t *target, int num)
static void arm7tdmi_write_pc(target_t *target, uint32_t pc)
{
struct arm7_9_common_s *arm7_9 = target_to_arm7_9(target);
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
arm_jtag_t *jtag_info = &arm7_9->jtag_info;
/* LDMIA r0-15, [r0] at debug speed
@ -570,7 +570,7 @@ static void arm7tdmi_write_pc(target_t *target, uint32_t pc)
static void arm7tdmi_branch_resume(target_t *target)
{
struct arm7_9_common_s *arm7_9 = target_to_arm7_9(target);
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
arm_jtag_t *jtag_info = &arm7_9->jtag_info;
arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 1);
@ -579,7 +579,7 @@ static void arm7tdmi_branch_resume(target_t *target)
static void arm7tdmi_branch_resume_thumb(target_t *target)
{
struct arm7_9_common_s *arm7_9 = target_to_arm7_9(target);
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
struct armv4_5_common_s *armv4_5 = &arm7_9->armv4_5_common;
arm_jtag_t *jtag_info = &arm7_9->jtag_info;
reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
@ -648,7 +648,7 @@ static void arm7tdmi_build_reg_cache(target_t *target)
int arm7tdmi_examine(struct target_s *target)
{
struct arm7_9_common_s *arm7_9 = target_to_arm7_9(target);
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
int retval;
@ -693,7 +693,7 @@ int arm7tdmi_init_target(struct command_context_s *cmd_ctx, struct target_s *tar
int arm7tdmi_init_arch_info(target_t *target, arm7tdmi_common_t *arm7tdmi, struct jtag_tap *tap)
{
struct arm7_9_common_s *arm7_9 = &arm7tdmi->arm7_9_common;
struct arm7_9_common *arm7_9 = &arm7tdmi->arm7_9_common;
/* prepare JTAG information for the new target */
arm7_9->jtag_info.tap = tap;

2
src/target/arm7tdmi.h
View File

@ -30,7 +30,7 @@
*/
typedef struct arm7tdmi_common_s
{
arm7_9_common_t arm7_9_common;
struct arm7_9_common arm7_9_common;
} arm7tdmi_common_t;
int arm7tdmi_init_arch_info(target_t *target, arm7tdmi_common_t *arm7tdmi, struct jtag_tap *tap);

8
src/target/arm920t.c
View File

@ -553,7 +553,7 @@ int arm920t_soft_reset_halt(struct target_s *target)
{
int retval = ERROR_OK;
struct arm920t_common *arm920t = target_to_arm920(target);
struct arm7_9_common_s *arm7_9 = target_to_arm7_9(target);
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
struct armv4_5_common_s *armv4_5 = &arm7_9->armv4_5_common;
reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
@ -623,7 +623,7 @@ int arm920t_soft_reset_halt(struct target_s *target)
int arm920t_init_arch_info(target_t *target, struct arm920t_common *arm920t, struct jtag_tap *tap)
{
arm9tdmi_common_t *arm9tdmi = &arm920t->arm9tdmi_common;
arm7_9_common_t *arm7_9 = &arm9tdmi->arm7_9_common;
struct arm7_9_common *arm7_9 = &arm9tdmi->arm7_9_common;
/* initialize arm9tdmi specific info (including arm7_9 and armv4_5)
*/
@ -667,7 +667,7 @@ COMMAND_HANDLER(arm920t_handle_read_cache_command)
int retval = ERROR_OK;
target_t *target = get_current_target(cmd_ctx);
struct arm920t_common *arm920t = target_to_arm920(target);
struct arm7_9_common_s *arm7_9 = target_to_arm7_9(target);
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
struct armv4_5_common_s *armv4_5 = &arm7_9->armv4_5_common;
uint32_t cp15c15;
uint32_t cp15_ctrl, cp15_ctrl_saved;
@ -913,7 +913,7 @@ COMMAND_HANDLER(arm920t_handle_read_mmu_command)
int retval = ERROR_OK;
target_t *target = get_current_target(cmd_ctx);
struct arm920t_common *arm920t = target_to_arm920(target);
struct arm7_9_common_s *arm7_9 = target_to_arm7_9(target);
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
struct armv4_5_common_s *armv4_5 = &arm7_9->armv4_5_common;
uint32_t cp15c15;
uint32_t cp15_ctrl, cp15_ctrl_saved;

10
src/target/arm926ejs.c
View File

@ -51,7 +51,7 @@ static int arm926ejs_cp15_read(target_t *target, uint32_t op1, uint32_t op2,
uint32_t CRn, uint32_t CRm, uint32_t *value)
{
int retval = ERROR_OK;
struct arm7_9_common_s *arm7_9 = target_to_arm7_9(target);
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
arm_jtag_t *jtag_info = &arm7_9->jtag_info;
uint32_t address = ARM926EJS_CP15_ADDR(op1, op2, CRn, CRm);
struct scan_field fields[4];
@ -143,7 +143,7 @@ static int arm926ejs_cp15_write(target_t *target, uint32_t op1, uint32_t op2,
uint32_t CRn, uint32_t CRm, uint32_t value)
{
int retval = ERROR_OK;
struct arm7_9_common_s *arm7_9 = target_to_arm7_9(target);
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
arm_jtag_t *jtag_info = &arm7_9->jtag_info;
uint32_t address = ARM926EJS_CP15_ADDR(op1, op2, CRn, CRm);
struct scan_field fields[4];
@ -231,7 +231,7 @@ static int arm926ejs_mcr(target_t *target, int cpnum, uint32_t op1,
static int arm926ejs_examine_debug_reason(target_t *target)
{
struct arm7_9_common_s *arm7_9 = target_to_arm7_9(target);
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
int debug_reason;
int retval;
@ -522,7 +522,7 @@ int arm926ejs_soft_reset_halt(struct target_s *target)
{
int retval = ERROR_OK;
struct arm926ejs_common_s *arm926ejs = target_to_arm926(target);
struct arm7_9_common_s *arm7_9 = target_to_arm7_9(target);
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
struct armv4_5_common_s *armv4_5 = &arm7_9->armv4_5_common;
reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
@ -670,7 +670,7 @@ int arm926ejs_init_arch_info(target_t *target, arm926ejs_common_t *arm926ejs,
struct jtag_tap *tap)
{
arm9tdmi_common_t *arm9tdmi = &arm926ejs->arm9tdmi_common;
arm7_9_common_t *arm7_9 = &arm9tdmi->arm7_9_common;
struct arm7_9_common *arm7_9 = &arm9tdmi->arm7_9_common;
/* initialize arm9tdmi specific info (including arm7_9 and armv4_5)
*/

6
src/target/arm966e.c
View File

@ -35,7 +35,7 @@
int arm966e_init_arch_info(target_t *target, arm966e_common_t *arm966e, struct jtag_tap *tap)
{
arm9tdmi_common_t *arm9tdmi = &arm966e->arm9tdmi_common;
arm7_9_common_t *arm7_9 = &arm9tdmi->arm7_9_common;
struct arm7_9_common *arm7_9 = &arm9tdmi->arm7_9_common;
arm9tdmi_init_arch_info(target, arm9tdmi, tap);
@ -70,7 +70,7 @@ static int arm966e_verify_pointer(struct command_context_s *cmd_ctx,
static int arm966e_read_cp15(target_t *target, int reg_addr, uint32_t *value)
{
int retval = ERROR_OK;
struct arm7_9_common_s *arm7_9 = target_to_arm7_9(target);
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
arm_jtag_t *jtag_info = &arm7_9->jtag_info;
struct scan_field fields[3];
uint8_t reg_addr_buf = reg_addr & 0x3f;
@ -122,7 +122,7 @@ static int arm966e_read_cp15(target_t *target, int reg_addr, uint32_t *value)
int arm966e_write_cp15(target_t *target, int reg_addr, uint32_t value)
{
int retval = ERROR_OK;
struct arm7_9_common_s *arm7_9 = target_to_arm7_9(target);
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
arm_jtag_t *jtag_info = &arm7_9->jtag_info;
struct scan_field fields[3];
uint8_t reg_addr_buf = reg_addr & 0x3f;

44
src/target/arm9tdmi.c
View File

@ -60,7 +60,7 @@ static const arm9tdmi_vector_t arm9tdmi_vectors[] =
int arm9tdmi_examine_debug_reason(target_t *target)
{
int retval = ERROR_OK;
struct arm7_9_common_s *arm7_9 = target_to_arm7_9(target);
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
/* only check the debug reason if we don't know it already */
if ((target->debug_reason != DBG_REASON_DBGRQ)
@ -329,7 +329,7 @@ static void arm9tdmi_change_to_arm(target_t *target,
uint32_t *r0, uint32_t *pc)
{
int retval = ERROR_OK;
struct arm7_9_common_s *arm7_9 = target_to_arm7_9(target);
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
arm_jtag_t *jtag_info = &arm7_9->jtag_info;
/* save r0 before using it and put system in ARM state
@ -383,7 +383,7 @@ void arm9tdmi_read_core_regs(target_t *target,
uint32_t mask, uint32_t* core_regs[16])
{
int i;
struct arm7_9_common_s *arm7_9 = target_to_arm7_9(target);
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
arm_jtag_t *jtag_info = &arm7_9->jtag_info;
/* STMIA r0-15, [r0] at debug speed
@ -408,7 +408,7 @@ static void arm9tdmi_read_core_regs_target_buffer(target_t *target,
uint32_t mask, void* buffer, int size)
{
int i;
struct arm7_9_common_s *arm7_9 = target_to_arm7_9(target);
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
arm_jtag_t *jtag_info = &arm7_9->jtag_info;
int be = (target->endianness == TARGET_BIG_ENDIAN) ? 1 : 0;
uint32_t *buf_u32 = buffer;
@ -446,7 +446,7 @@ static void arm9tdmi_read_core_regs_target_buffer(target_t *target,
static void arm9tdmi_read_xpsr(target_t *target, uint32_t *xpsr, int spsr)
{
struct arm7_9_common_s *arm7_9 = target_to_arm7_9(target);
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
arm_jtag_t *jtag_info = &arm7_9->jtag_info;
/* MRS r0, cpsr */
@ -468,7 +468,7 @@ static void arm9tdmi_read_xpsr(target_t *target, uint32_t *xpsr, int spsr)
static void arm9tdmi_write_xpsr(target_t *target, uint32_t xpsr, int spsr)
{
struct arm7_9_common_s *arm7_9 = target_to_arm7_9(target);
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
arm_jtag_t *jtag_info = &arm7_9->jtag_info;
LOG_DEBUG("xpsr: %8.8" PRIx32 ", spsr: %i", xpsr, spsr);
@ -503,7 +503,7 @@ static void arm9tdmi_write_xpsr(target_t *target, uint32_t xpsr, int spsr)
static void arm9tdmi_write_xpsr_im8(target_t *target,
uint8_t xpsr_im, int rot, int spsr)
{
struct arm7_9_common_s *arm7_9 = target_to_arm7_9(target);
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
arm_jtag_t *jtag_info = &arm7_9->jtag_info;
LOG_DEBUG("xpsr_im: %2.2x, rot: %i, spsr: %i", xpsr_im, rot, spsr);
@ -529,7 +529,7 @@ void arm9tdmi_write_core_regs(target_t *target,
uint32_t mask, uint32_t core_regs[16])
{
int i;
struct arm7_9_common_s *arm7_9 = target_to_arm7_9(target);
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
arm_jtag_t *jtag_info = &arm7_9->jtag_info;
/* LDMIA r0-15, [r0] at debug speed
@ -553,7 +553,7 @@ void arm9tdmi_write_core_regs(target_t *target,
void arm9tdmi_load_word_regs(target_t *target, uint32_t mask)
{
struct arm7_9_common_s *arm7_9 = target_to_arm7_9(target);
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
arm_jtag_t *jtag_info = &arm7_9->jtag_info;
/* put system-speed load-multiple into the pipeline */
@ -563,7 +563,7 @@ void arm9tdmi_load_word_regs(target_t *target, uint32_t mask)
void arm9tdmi_load_hword_reg(target_t *target, int num)
{
struct arm7_9_common_s *arm7_9 = target_to_arm7_9(target);
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
arm_jtag_t *jtag_info = &arm7_9->jtag_info;
/* put system-speed load half-word into the pipeline */
@ -573,7 +573,7 @@ void arm9tdmi_load_hword_reg(target_t *target, int num)
void arm9tdmi_load_byte_reg(target_t *target, int num)
{
struct arm7_9_common_s *arm7_9 = target_to_arm7_9(target);
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
arm_jtag_t *jtag_info = &arm7_9->jtag_info;
/* put system-speed load byte into the pipeline */
@ -583,7 +583,7 @@ void arm9tdmi_load_byte_reg(target_t *target, int num)
void arm9tdmi_store_word_regs(target_t *target, uint32_t mask)
{
struct arm7_9_common_s *arm7_9 = target_to_arm7_9(target);
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
arm_jtag_t *jtag_info = &arm7_9->jtag_info;
/* put system-speed store-multiple into the pipeline */
@ -593,7 +593,7 @@ void arm9tdmi_store_word_regs(target_t *target, uint32_t mask)
void arm9tdmi_store_hword_reg(target_t *target, int num)
{
struct arm7_9_common_s *arm7_9 = target_to_arm7_9(target);
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
arm_jtag_t *jtag_info = &arm7_9->jtag_info;
/* put system-speed store half-word into the pipeline */
@ -603,7 +603,7 @@ void arm9tdmi_store_hword_reg(target_t *target, int num)
void arm9tdmi_store_byte_reg(target_t *target, int num)
{
struct arm7_9_common_s *arm7_9 = target_to_arm7_9(target);
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
arm_jtag_t *jtag_info = &arm7_9->jtag_info;
/* put system-speed store byte into the pipeline */
@ -613,7 +613,7 @@ void arm9tdmi_store_byte_reg(target_t *target, int num)
static void arm9tdmi_write_pc(target_t *target, uint32_t pc)
{
struct arm7_9_common_s *arm7_9 = target_to_arm7_9(target);
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
arm_jtag_t *jtag_info = &arm7_9->jtag_info;
/* LDMIA r0-15, [r0] at debug speed
@ -637,7 +637,7 @@ static void arm9tdmi_write_pc(target_t *target, uint32_t pc)
void arm9tdmi_branch_resume(target_t *target)
{
struct arm7_9_common_s *arm7_9 = target_to_arm7_9(target);
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
arm_jtag_t *jtag_info = &arm7_9->jtag_info;
arm9tdmi_clock_out(jtag_info, ARMV4_5_B(0xfffffc, 0), 0, NULL, 0);
@ -648,7 +648,7 @@ static void arm9tdmi_branch_resume_thumb(target_t *target)
{
LOG_DEBUG("-");
struct arm7_9_common_s *arm7_9 = target_to_arm7_9(target);
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
struct armv4_5_common_s *armv4_5 = &arm7_9->armv4_5_common;
arm_jtag_t *jtag_info = &arm7_9->jtag_info;
reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
@ -705,7 +705,7 @@ static void arm9tdmi_branch_resume_thumb(target_t *target)
void arm9tdmi_enable_single_step(target_t *target, uint32_t next_pc)
{
struct arm7_9_common_s *arm7_9 = target_to_arm7_9(target);
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
if (arm7_9->has_single_step)
{
@ -720,7 +720,7 @@ void arm9tdmi_enable_single_step(target_t *target, uint32_t next_pc)
void arm9tdmi_disable_single_step(target_t *target)
{
struct arm7_9_common_s *arm7_9 = target_to_arm7_9(target);
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
if (arm7_9->has_single_step)
{
@ -745,7 +745,7 @@ static void arm9tdmi_build_reg_cache(target_t *target)
int arm9tdmi_examine(struct target_s *target)
{
int retval;
struct arm7_9_common_s *arm7_9 = target_to_arm7_9(target);
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
if (!target_was_examined(target))
{
@ -789,7 +789,7 @@ int arm9tdmi_init_target(struct command_context_s *cmd_ctx,
int arm9tdmi_init_arch_info(target_t *target, arm9tdmi_common_t *arm9tdmi, struct jtag_tap *tap)
{
armv4_5_common_t *armv4_5;
arm7_9_common_t *arm7_9;
struct arm7_9_common *arm7_9;
arm7_9 = &arm9tdmi->arm7_9_common;
armv4_5 = &arm7_9->armv4_5_common;
@ -859,7 +859,7 @@ static int arm9tdmi_target_create(struct target_s *target, Jim_Interp *interp)
COMMAND_HANDLER(handle_arm9tdmi_catch_vectors_command)
{
target_t *target = get_current_target(cmd_ctx);
struct arm7_9_common_s *arm7_9 = target_to_arm7_9(target);
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
reg_t *vector_catch;
uint32_t vector_catch_value;

2
src/target/arm9tdmi.h
View File

@ -30,7 +30,7 @@
*/
typedef struct arm9tdmi_common_s
{
arm7_9_common_t arm7_9_common;
struct arm7_9_common arm7_9_common;
} arm9tdmi_common_t;
typedef struct arm9tdmi_vector_s

4
src/target/embeddedice.c
View File

@ -164,7 +164,7 @@ static int embeddedice_get_reg(reg_t *reg)
* hardware support for vector_catch, single stepping, and monitor mode.
*/
reg_cache_t *
embeddedice_build_reg_cache(target_t *target, arm7_9_common_t *arm7_9)
embeddedice_build_reg_cache(target_t *target, struct arm7_9_common *arm7_9)
{
int retval;
reg_cache_t *reg_cache = malloc(sizeof(reg_cache_t));
@ -303,7 +303,7 @@ embeddedice_build_reg_cache(target_t *target, arm7_9_common_t *arm7_9)
int embeddedice_setup(target_t *target)
{
int retval;
struct arm7_9_common_s *arm7_9 = target_to_arm7_9(target);
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
/* Explicitly disable monitor mode. For now we only support halting
* debug ... we don't know how to talk with a resident debug monitor

2
src/target/embeddedice.h
View File

@ -94,7 +94,7 @@ typedef struct embeddedice_reg_s
} embeddedice_reg_t;
reg_cache_t* embeddedice_build_reg_cache(target_t *target,
arm7_9_common_t *arm7_9);
struct arm7_9_common *arm7_9);
int embeddedice_setup(target_t *target);

18
src/target/fa526.c
View File

@ -43,7 +43,7 @@ static void fa526_read_core_regs(target_t *target,
uint32_t mask, uint32_t* core_regs[16])
{
int i;
struct arm7_9_common_s *arm7_9 = target_to_arm7_9(target);
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
arm_jtag_t *jtag_info = &arm7_9->jtag_info;
/* STMIA r0-15, [r0] at debug speed
@ -70,7 +70,7 @@ static void fa526_read_core_regs_target_buffer(target_t *target,
uint32_t mask, void* buffer, int size)
{
int i;
struct arm7_9_common_s *arm7_9 = target_to_arm7_9(target);
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
arm_jtag_t *jtag_info = &arm7_9->jtag_info;
int be = (target->endianness == TARGET_BIG_ENDIAN) ? 1 : 0;
uint32_t *buf_u32 = buffer;
@ -110,7 +110,7 @@ static void fa526_read_core_regs_target_buffer(target_t *target,
static void fa526_read_xpsr(target_t *target, uint32_t *xpsr, int spsr)
{
struct arm7_9_common_s *arm7_9 = target_to_arm7_9(target);
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
arm_jtag_t *jtag_info = &arm7_9->jtag_info;
/* MRS r0, cpsr */
@ -135,7 +135,7 @@ static void fa526_read_xpsr(target_t *target, uint32_t *xpsr, int spsr)
static void fa526_write_xpsr(target_t *target, uint32_t xpsr, int spsr)
{
struct arm7_9_common_s *arm7_9 = target_to_arm7_9(target);
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
arm_jtag_t *jtag_info = &arm7_9->jtag_info;
LOG_DEBUG("xpsr: %8.8" PRIx32 ", spsr: %i", xpsr, spsr);
@ -172,7 +172,7 @@ static void fa526_write_xpsr(target_t *target, uint32_t xpsr, int spsr)
static void fa526_write_xpsr_im8(target_t *target,
uint8_t xpsr_im, int rot, int spsr)
{
struct arm7_9_common_s *arm7_9 = target_to_arm7_9(target);
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
arm_jtag_t *jtag_info = &arm7_9->jtag_info;
LOG_DEBUG("xpsr_im: %2.2x, rot: %i, spsr: %i", xpsr_im, rot, spsr);
@ -200,7 +200,7 @@ static void fa526_write_core_regs(target_t *target,
uint32_t mask, uint32_t core_regs[16])
{
int i;
struct arm7_9_common_s *arm7_9 = target_to_arm7_9(target);
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
arm_jtag_t *jtag_info = &arm7_9->jtag_info;
/* LDMIA r0-15, [r0] at debug speed
@ -226,7 +226,7 @@ static void fa526_write_core_regs(target_t *target,
static void fa526_write_pc(target_t *target, uint32_t pc)
{
struct arm7_9_common_s *arm7_9 = target_to_arm7_9(target);
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
arm_jtag_t *jtag_info = &arm7_9->jtag_info;
/* LDMIA r0-15, [r0] at debug speed
@ -258,7 +258,7 @@ static void fa526_branch_resume_thumb(target_t *target)
static int fa526_init_arch_info_2(target_t *target,
arm9tdmi_common_t *arm9tdmi, struct jtag_tap *tap)
{
arm7_9_common_t *arm7_9;
struct arm7_9_common *arm7_9;
arm7_9 = &arm9tdmi->arm7_9_common;
@ -318,7 +318,7 @@ static int fa526_init_arch_info(target_t *target,
struct arm920t_common *arm920t, struct jtag_tap *tap)
{
arm9tdmi_common_t *arm9tdmi = &arm920t->arm9tdmi_common;
arm7_9_common_t *arm7_9 = &arm9tdmi->arm7_9_common;
struct arm7_9_common *arm7_9 = &arm9tdmi->arm7_9_common;
/* initialize arm9tdmi specific info (including arm7_9 and armv4_5)
*/

36
src/target/feroceon.c
View File

@ -59,7 +59,7 @@
int feroceon_assert_reset(target_t *target)
{
armv4_5_common_t *armv4_5 = target->arch_info;
arm7_9_common_t *arm7_9 = armv4_5->arch_info;
struct arm7_9_common *arm7_9 = armv4_5->arch_info;
int ud = arm7_9->use_dbgrq;
arm7_9->use_dbgrq = 0;
@ -111,7 +111,7 @@ int feroceon_dummy_clock_out(arm_jtag_t *jtag_info, uint32_t instr)
void feroceon_change_to_arm(target_t *target, uint32_t *r0, uint32_t *pc)
{
armv4_5_common_t *armv4_5 = target->arch_info;
arm7_9_common_t *arm7_9 = armv4_5->arch_info;
struct arm7_9_common *arm7_9 = armv4_5->arch_info;
arm_jtag_t *jtag_info = &arm7_9->jtag_info;
/*
@ -158,7 +158,7 @@ void feroceon_read_core_regs(target_t *target, uint32_t mask, uint32_t* core_reg
{
int i;
armv4_5_common_t *armv4_5 = target->arch_info;
arm7_9_common_t *arm7_9 = armv4_5->arch_info;
struct arm7_9_common *arm7_9 = armv4_5->arch_info;
arm_jtag_t *jtag_info = &arm7_9->jtag_info;
arm9tdmi_clock_out(jtag_info, ARMV4_5_STMIA(0, mask & 0xffff, 0, 0), 0, NULL, 0);
@ -177,7 +177,7 @@ void feroceon_read_core_regs_target_buffer(target_t *target, uint32_t mask, void
{
int i;
armv4_5_common_t *armv4_5 = target->arch_info;
arm7_9_common_t *arm7_9 = armv4_5->arch_info;
struct arm7_9_common *arm7_9 = armv4_5->arch_info;
arm_jtag_t *jtag_info = &arm7_9->jtag_info;
int be = (target->endianness == TARGET_BIG_ENDIAN) ? 1 : 0;
uint32_t *buf_u32 = buffer;
@ -213,7 +213,7 @@ void feroceon_read_core_regs_target_buffer(target_t *target, uint32_t mask, void
void feroceon_read_xpsr(target_t *target, uint32_t *xpsr, int spsr)
{
armv4_5_common_t *armv4_5 = target->arch_info;
arm7_9_common_t *arm7_9 = armv4_5->arch_info;
struct arm7_9_common *arm7_9 = armv4_5->arch_info;
arm_jtag_t *jtag_info = &arm7_9->jtag_info;
arm9tdmi_clock_out(jtag_info, ARMV4_5_MRS(0, spsr & 1), 0, NULL, 0);
@ -236,7 +236,7 @@ void feroceon_read_xpsr(target_t *target, uint32_t *xpsr, int spsr)
void feroceon_write_xpsr(target_t *target, uint32_t xpsr, int spsr)
{
armv4_5_common_t *armv4_5 = target->arch_info;
arm7_9_common_t *arm7_9 = armv4_5->arch_info;
struct arm7_9_common *arm7_9 = armv4_5->arch_info;
arm_jtag_t *jtag_info = &arm7_9->jtag_info;
LOG_DEBUG("xpsr: %8.8" PRIx32 ", spsr: %i", xpsr, spsr);
@ -277,7 +277,7 @@ void feroceon_write_xpsr(target_t *target, uint32_t xpsr, int spsr)
void feroceon_write_xpsr_im8(target_t *target, uint8_t xpsr_im, int rot, int spsr)
{
armv4_5_common_t *armv4_5 = target->arch_info;
arm7_9_common_t *arm7_9 = armv4_5->arch_info;
struct arm7_9_common *arm7_9 = armv4_5->arch_info;
arm_jtag_t *jtag_info = &arm7_9->jtag_info;
LOG_DEBUG("xpsr_im: %2.2x, rot: %i, spsr: %i", xpsr_im, rot, spsr);
@ -295,7 +295,7 @@ void feroceon_write_core_regs(target_t *target, uint32_t mask, uint32_t core_reg
{
int i;
armv4_5_common_t *armv4_5 = target->arch_info;
arm7_9_common_t *arm7_9 = armv4_5->arch_info;
struct arm7_9_common *arm7_9 = armv4_5->arch_info;
arm_jtag_t *jtag_info = &arm7_9->jtag_info;
arm9tdmi_clock_out(jtag_info, ARMV4_5_LDMIA(0, mask & 0xffff, 0, 0), 0, NULL, 0);
@ -314,7 +314,7 @@ void feroceon_write_core_regs(target_t *target, uint32_t mask, uint32_t core_reg
void feroceon_branch_resume(target_t *target)
{
armv4_5_common_t *armv4_5 = target->arch_info;
arm7_9_common_t *arm7_9 = armv4_5->arch_info;
struct arm7_9_common *arm7_9 = armv4_5->arch_info;
arm_jtag_t *jtag_info = &arm7_9->jtag_info;
arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
@ -331,7 +331,7 @@ void feroceon_branch_resume_thumb(target_t *target)
LOG_DEBUG("-");
armv4_5_common_t *armv4_5 = target->arch_info;
arm7_9_common_t *arm7_9 = armv4_5->arch_info;
struct arm7_9_common *arm7_9 = armv4_5->arch_info;
arm_jtag_t *jtag_info = &arm7_9->jtag_info;
uint32_t r0 = buf_get_u32(armv4_5->core_cache->reg_list[0].value, 0, 32);
uint32_t pc = buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32);
@ -364,7 +364,7 @@ void feroceon_branch_resume_thumb(target_t *target)
int feroceon_read_cp15(target_t *target, uint32_t op1, uint32_t op2, uint32_t CRn, uint32_t CRm, uint32_t *value)
{
armv4_5_common_t *armv4_5 = target->arch_info;
arm7_9_common_t *arm7_9 = armv4_5->arch_info;
struct arm7_9_common *arm7_9 = armv4_5->arch_info;
arm_jtag_t *jtag_info = &arm7_9->jtag_info;
int err;
@ -386,7 +386,7 @@ int feroceon_read_cp15(target_t *target, uint32_t op1, uint32_t op2, uint32_t CR
int feroceon_write_cp15(target_t *target, uint32_t op1, uint32_t op2, uint32_t CRn, uint32_t CRm, uint32_t value)
{
armv4_5_common_t *armv4_5 = target->arch_info;
arm7_9_common_t *arm7_9 = armv4_5->arch_info;
struct arm7_9_common *arm7_9 = armv4_5->arch_info;
arm_jtag_t *jtag_info = &arm7_9->jtag_info;
arm9tdmi_clock_out(jtag_info, ARMV4_5_LDMIA(0, 1, 0, 0), 0, NULL, 0);
@ -405,7 +405,7 @@ int feroceon_write_cp15(target_t *target, uint32_t op1, uint32_t op2, uint32_t C
void feroceon_set_dbgrq(target_t *target)
{
armv4_5_common_t *armv4_5 = target->arch_info;
arm7_9_common_t *arm7_9 = armv4_5->arch_info;
struct arm7_9_common *arm7_9 = armv4_5->arch_info;
reg_t *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL];
buf_set_u32(dbg_ctrl->value, 0, 8, 2);
@ -415,7 +415,7 @@ void feroceon_set_dbgrq(target_t *target)
void feroceon_enable_single_step(target_t *target, uint32_t next_pc)
{
armv4_5_common_t *armv4_5 = target->arch_info;
arm7_9_common_t *arm7_9 = armv4_5->arch_info;
struct arm7_9_common *arm7_9 = armv4_5->arch_info;
/* set a breakpoint there */
embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_VALUE], next_pc);
@ -428,7 +428,7 @@ void feroceon_enable_single_step(target_t *target, uint32_t next_pc)
void feroceon_disable_single_step(target_t *target)
{
armv4_5_common_t *armv4_5 = target->arch_info;
arm7_9_common_t *arm7_9 = armv4_5->arch_info;
struct arm7_9_common *arm7_9 = armv4_5->arch_info;
embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_VALUE]);
embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_MASK]);
@ -452,7 +452,7 @@ int feroceon_bulk_write_memory(target_t *target, uint32_t address, uint32_t coun
{
int retval;
armv4_5_common_t *armv4_5 = target->arch_info;
arm7_9_common_t *arm7_9 = armv4_5->arch_info;
struct arm7_9_common *arm7_9 = armv4_5->arch_info;
enum armv4_5_state core_state = armv4_5->core_state;
uint32_t x, flip, shift, save[7];
uint32_t i;
@ -586,7 +586,7 @@ int feroceon_init_target(struct command_context_s *cmd_ctx, struct target_s *tar
void feroceon_common_setup(struct target_s *target)
{
armv4_5_common_t *armv4_5 = target->arch_info;
arm7_9_common_t *arm7_9 = armv4_5->arch_info;
struct arm7_9_common *arm7_9 = armv4_5->arch_info;
/* override some insn sequence functions */
arm7_9->change_to_arm = feroceon_change_to_arm;
@ -643,7 +643,7 @@ int dragonite_target_create(struct target_s *target, Jim_Interp *interp)
int feroceon_examine(struct target_s *target)
{
armv4_5_common_t *armv4_5;
arm7_9_common_t *arm7_9;
struct arm7_9_common *arm7_9;
int retval;
retval = arm9tdmi_examine(target);