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riscv: Add some comments on what else compliance test needs

This commit is contained in:
Megan Wachs 2017-06-28 19:32:30 -07:00
parent 434fb3708a
commit 7bc23c7776
1 changed files with 20 additions and 0 deletions
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20
src/target/riscv/riscv-013.c
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@ -2419,8 +2419,28 @@ int riscv013_test_compliance(struct target *target) {
COMPLIANCE_TEST((riscv_get_register(target, GDB_REGNO_DPC) & dpcmask) == (testvar64 & dpcmask), "DPC must be writable."); COMPLIANCE_TEST((riscv_get_register(target, GDB_REGNO_DPC) & dpcmask) == (testvar64 & dpcmask), "DPC must be writable.");
riscv_set_register(target, GDB_REGNO_DPC, ~testvar64); riscv_set_register(target, GDB_REGNO_DPC, ~testvar64);
COMPLIANCE_TEST((riscv_get_register(target, GDB_REGNO_DPC) & dpcmask) == ((~testvar64) & dpcmask), "DPC must be writable"); COMPLIANCE_TEST((riscv_get_register(target, GDB_REGNO_DPC) & dpcmask) == ((~testvar64) & dpcmask), "DPC must be writable");
} }
//TODO:
// DMACTIVE
// NDMRESET
// Asserting non-debug module reset should not reset Debug Module state.
// But it should reset Hart State, e.g. DPC should get a different value.
// Also make sure that DCSR reports cause of 'HALT' even though previously we single-stepped.
// DMCONTROL
// COMMAND
// PROGBUF
// ABSTRACTAUTO
// DATA
// TODO: HASEL, HAWINDOWSEL
// Single-Step each hart.
// Assert cause is SINGLESTEP
LOG_INFO("PASSED %d of %d TESTS\n", passed_tests, total_tests); LOG_INFO("PASSED %d of %d TESTS\n", passed_tests, total_tests);
if (total_tests == passed_tests) { if (total_tests == passed_tests) {