David Brownell <david-b@pacbell.net> Cleanup the Stellaris target configs:
- remove endianness options; these chips hard-wire "little"
- $_TARGETNAME updates:
* don't pass $_TARGETNAME where a TAP label is required
* flash config uses $_TARGETNAME (it might not be target #0)
* simplify one $_TARGETNAME construction
- update work area setup:
* remove VM spec; these chips have no VM!
* fix some wrong sizes (0x4000 == 16K, not 4K)
* simplify: take defaults
- comment fixups
git-svn-id: svn://svn.berlios.de/openocd/trunk@2589 b42882b7-edfa-0310-969c-e2dbd0fdcd60
This commit is contained in:
oharboe
parent
ed22097a55
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7b4428df97
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@ -6,13 +6,6 @@ if { [info exists CHIPNAME] } {
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set _CHIPNAME lm3s1968
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}
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if { [info exists ENDIAN] } {
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set _ENDIAN $ENDIAN
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} else {
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# this defaults to a little endian
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set _ENDIAN little
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}
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if { [info exists CPUTAPID ] } {
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set _CPUTAPID $CPUTAPID
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} else {
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@ -26,10 +19,10 @@ jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 1 -irmask 0xf -expected-id $_CPUT
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# this stops the debug registers from being cleared
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# this will be fixed in later revisions of silicon
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set _TARGETNAME $_CHIPNAME.cpu
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target create $_TARGETNAME cortex_m3 -endian $_ENDIAN -chain-position $_TARGETNAME -variant lm3s
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target create $_TARGETNAME cortex_m3 -chain-position $_CHIPNAME.cpu -variant lm3s
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# 4k working area at base of ram
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$_TARGETNAME configure -work-area-virt 0 -work-area-phys 0x20000000 -work-area-size 0x4000 -work-area-backup 0
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# 8k working area at base of ram, not backed up
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$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size 0x2000
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#flash configuration
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flash bank stellaris 0 0 0 0 0
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flash bank stellaris 0 0 0 0 $_TARGETNAME
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@ -6,13 +6,6 @@ if { [info exists CHIPNAME] } {
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set _CHIPNAME lm3s3748
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}
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if { [info exists ENDIAN] } {
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set _ENDIAN $ENDIAN
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} else {
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# this defaults to a little endian
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set _ENDIAN little
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}
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if { [info exists CPUTAPID ] } {
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set _CPUTAPID $CPUTAPID
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} else {
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@ -26,11 +19,10 @@ jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 1 -irmask 0xf -expected-id $_CPUT
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# parts (third generation, includes LM3S3748). It keeps the debug registers
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# from being cleared, by using software reset not SRST; NOP on newer revs.
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set _TARGETNAME $_CHIPNAME.cpu
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target create $_TARGETNAME cortex_m3 -endian $_ENDIAN \
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-chain-position $_TARGETNAME -variant lm3s
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target create $_TARGETNAME cortex_m3 -chain-position $_CHIPNAME.cpu -variant lm3s
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# 8k working area at base of ram, not backed up
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$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size 0x2000
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# flash configuration -- one bank of 128K
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flash bank stellaris 0 0 0 0 0
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flash bank stellaris 0 0 0 0 $_TARGETNAME
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@ -1,5 +1,4 @@
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# script for luminary lm3s6965
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# TI/Luminary Stellaris lm3s6965
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if { [info exists CHIPNAME] } {
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set _CHIPNAME $CHIPNAME
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@ -7,17 +6,9 @@ if { [info exists CHIPNAME] } {
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set _CHIPNAME lm3s6965
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}
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if { [info exists ENDIAN] } {
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set _ENDIAN $ENDIAN
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} else {
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# this defaults to a little endian
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set _ENDIAN little
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}
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if { [info exists CPUTAPID ] } {
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set _CPUTAPID $CPUTAPID
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} else {
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# force an error till we get a good number
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set _CPUTAPID 0x3ba00477
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}
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@ -36,11 +27,11 @@ jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 1 -irmask 0xf -expected-id $_CPUT
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# the luminary variant causes a software reset rather than asserting SRST
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# this stops the debug registers from being cleared
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# this will be fixed in later revisions of silicon
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set _TARGETNAME [format "%s.cpu" $_CHIPNAME]
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target create $_TARGETNAME cortex_m3 -endian $_ENDIAN -chain-position $_TARGETNAME -variant lm3s
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set _TARGETNAME $_CHIPNAME.cpu
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target create $_TARGETNAME cortex_m3 -chain-position $_CHIPNAME.cpu -variant lm3s
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# 4k working area at base of ram
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$_TARGETNAME configure -work-area-virt 0 -work-area-phys 0x20000000 -work-area-size 0x4000 -work-area-backup 0
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# 8k working area at base of ram, not backed up
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$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size 0x2000
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#flash configuration
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flash bank stellaris 0 0 0 0 0
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flash bank stellaris 0 0 0 0 $_TARGETNAME
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@ -6,13 +6,6 @@ if { [info exists CHIPNAME] } {
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set _CHIPNAME lm3s811
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}
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if { [info exists ENDIAN] } {
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set _ENDIAN $ENDIAN
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} else {
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# this defaults to a little endian
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set _ENDIAN little
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}
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if { [info exists CPUTAPID ] } {
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set _CPUTAPID $CPUTAPID
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} else {
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@ -26,10 +19,10 @@ jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 1 -irmask 0xf -expected-id $_CPUT
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# this stops the debug registers from being cleared
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# this will be fixed in later revisions of silicon
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set _TARGETNAME $_CHIPNAME.cpu
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target create $_TARGETNAME cortex_m3 -endian $_ENDIAN -chain-position $_TARGETNAME -variant lm3s
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target create $_TARGETNAME cortex_m3 -chain-position $_CHIPNAME.cpu -variant lm3s
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# 8k working area at base of ram
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$_TARGETNAME configure -work-area-virt 0 -work-area-phys 0x20000000 -work-area-size 0x2000 -work-area-backup 0
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# 8k working area at base of ram, not backed up
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$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size 0x2000
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#flash configuration
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flash bank stellaris 0 0 0 0 0
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flash bank stellaris 0 0 0 0 $_TARGETNAME
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@ -11,17 +11,10 @@ if { [info exists CHIPNAME] } {
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set _CHIPNAME lm3s9b9x
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}
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if { [info exists ENDIAN] } {
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set _ENDIAN $ENDIAN
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} else {
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# this defaults to a little endian
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set _ENDIAN little
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}
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if { [info exists CPUTAPID ] } {
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set _CPUTAPID $CPUTAPID
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} else {
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# forth generation Tempest device
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# Fourth generation "Tempest" device
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set _CPUTAPID 0x4ba00477
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}
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@ -30,10 +23,10 @@ jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 1 -irmask 0xf -expected-id $_CPUT
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#Cortex-M3 with Luminary lm3s variant
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set _TARGETNAME $_CHIPNAME.cpu
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target create $_TARGETNAME cortex_m3 -endian $_ENDIAN -chain-position $_TARGETNAME -variant lm3s
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target create $_TARGETNAME cortex_m3 -chain-position $_CHIPNAME.cpu -variant lm3s
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# 16k working area at base of ram
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$_TARGETNAME configure -work-area-virt 0 -work-area-phys 0x20000000 -work-area-size 0x4000 -work-area-backup 0
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# 16k working area at base of ram, not backed up
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$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size 0x4000
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#flash configuration
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flash bank stellaris 0 0 0 0 0
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flash bank stellaris 0 0 0 0 $_TARGETNAME
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