diff --git a/contrib/loaders/flash/cc26xx/Makefile b/contrib/loaders/flash/cc26xx/Makefile new file mode 100644 index 000000000..7cc1fb3c4 --- /dev/null +++ b/contrib/loaders/flash/cc26xx/Makefile @@ -0,0 +1,83 @@ +BIN2C = ../../../../src/helper/bin2char.sh + +CROSS_COMPILE ?= arm-none-eabi- +GCC = $(CROSS_COMPILE)gcc +OBJCOPY = $(CROSS_COMPILE)objcopy + +FLAGS = -mthumb -Os -ffunction-sections -fdata-sections -g -gdwarf-3 +FLAGS += -gstrict-dwarf -Wall -fno-strict-aliasing --asm + +CFLAGS = -c -I. + +CC26X0_CFLAGS = -mcpu=cortex-m3 -DDEVICE_CC26X0 + +CC26X2_CFLAGS = -mcpu=cortex-m4 -DDEVICE_CC26X2 + +CC26X0_OBJS := \ +cc26x0/flashloader.o \ +cc26x0/main.o \ +cc26x0/startup.o \ +cc26x0/flash.o + +CC26X2_OBJS := \ +cc26x2/flashloader.o \ +cc26x2/main.o \ +cc26x2/startup.o \ +cc26x2/flash.o + +all: cc26x0_algo.inc cc26x2_algo.inc + +cc26x0/%.o: %.c + @echo 'Building file: $<' + @echo 'Invoking: GNU Compiler' + $(GCC) $(FLAGS) $(CFLAGS) $(CC26X0_CFLAGS) -o"$@" "$(shell echo $<)" + @echo 'Finished building: $<' + @echo ' ' + +cc26x2/%.o: %.c + @echo 'Building file: $<' + @echo 'Invoking: GNU Compiler' + $(GCC) $(FLAGS) $(CFLAGS) $(CC26X2_CFLAGS) -o"$@" "$(shell echo $<)" + @echo 'Finished building: $<' + @echo ' ' + +cc26x0_algo.out: $(CC26X0_OBJS) + @echo 'Building target: $@' + @echo 'Invoking: GNU Linker' + $(GCC) $(FLAGS) -o$@ $(CC26X0_OBJS) -Wl,-T"cc26x0/cc26x0r2f.lds" + @echo 'Finished building target: $@' + @echo ' ' + +cc26x2_algo.out: $(CC26X2_OBJS) + @echo 'Building target: $@' + @echo 'Invoking: GNU Linker' + $(GCC) $(FLAGS) -o$@ $(CC26X2_OBJS) -Wl,-T"cc26x2/cc26x2r1f.lds" + @echo 'Finished building target: $@' + @echo ' ' + +%.bin: %.out + @echo 'Building target: $@' + @echo 'Invoking: GNU Objcopy Utility' + $(OBJCOPY) -Obinary $< $@ + @echo 'Finished building target: $@' + @echo ' ' + +%.inc: %.bin + @echo 'Building target: $@' + @echo 'Invoking Bin2Char Script' + $(BIN2C) < $< > $@ + rm $< $*.out + @echo 'Finished building target: $@' + @echo ' ' + +clean: + @echo 'Cleaning Targets and Build Artifacts' + rm -rf *.inc *.bin *.out *.map + rm -rf cc26x0/*.o cc26x0/*.d + rm -rf cc26x2/*.o cc26x2/*.d + @echo 'Finished clean' + @echo ' ' + +.PRECIOUS: %.bin + +.PHONY: all clean diff --git a/contrib/loaders/flash/cc26xx/cc26x0/cc26x0r2f.lds b/contrib/loaders/flash/cc26xx/cc26x0/cc26x0r2f.lds new file mode 100644 index 000000000..9a126fc2b --- /dev/null +++ b/contrib/loaders/flash/cc26xx/cc26x0/cc26x0r2f.lds @@ -0,0 +1,90 @@ +/****************************************************************************** +* +* Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions +* are met: +* +* Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* +* Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in the +* documentation and/or other materials provided with the +* distribution. +* +* Neither the name of Texas Instruments Incorporated nor the names of +* its contributors may be used to endorse or promote products derived +* from this software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +/* Entry Point */ +ENTRY( entry ) + +/* System memory map */ +MEMORY +{ + /* Application is stored in and executes from SRAM */ + PROGRAM (RWX) : ORIGIN = 0x20000000, LENGTH = 0x1BD8 + BUFFERS (RWX) : ORIGIN = 0x20001BD8, LENGTH = 0x3028 +} + +/* Section allocation in memory */ +SECTIONS +{ + .text : + { + _text = .; + *(.entry*) + *(.text*) + _etext = .; + } > PROGRAM + + .data : + { _data = .; + *(.rodata*) + *(.data*) + _edata = .; + } + + .bss : + { + __bss_start__ = .; + _bss = .; + *(.bss*) + *(COMMON) + _ebss = .; + __bss_end__ = .; + } > PROGRAM + + .stack : + { + _stack = .; + *(.stack*) + _estack = .; + } > PROGRAM + + .buffers : + { + _buffers = .; + *(.buffers.g_cfg) + *(.buffers.g_buf1) + *(.buffers.g_buf2) + *(.buffers*) + _ebuffers = .; + } > BUFFERS +} diff --git a/contrib/loaders/flash/cc26xx/cc26x0_algo.inc b/contrib/loaders/flash/cc26xx/cc26x0_algo.inc new file mode 100644 index 000000000..2246a3670 --- /dev/null +++ b/contrib/loaders/flash/cc26xx/cc26x0_algo.inc @@ -0,0 +1,1217 @@ +/* Autogenerated with ../../../../src/helper/bin2char.sh */ +0x08,0xb5,0x00,0xbf,0x00,0xbf,0x00,0xbf,0x00,0xbf,0xdf,0xf8,0x1c,0xd0,0x07,0x48, +0x07,0x49,0x4f,0xf0,0x00,0x02,0x88,0x42,0xb8,0xbf,0x40,0xf8,0x04,0x2b,0xfa,0xdb, +0x00,0xf0,0xa8,0xf9,0xfe,0xe7,0x00,0x00,0xf0,0x0e,0x00,0x20,0x54,0x13,0x00,0x20, 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+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, diff --git a/contrib/loaders/flash/cc26xx/cc26x2/cc26x2r1f.lds b/contrib/loaders/flash/cc26xx/cc26x2/cc26x2r1f.lds new file mode 100644 index 000000000..fb7cc5611 --- /dev/null +++ b/contrib/loaders/flash/cc26xx/cc26x2/cc26x2r1f.lds @@ -0,0 +1,90 @@ +/****************************************************************************** +* +* Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions +* are met: +* +* Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* +* Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in the +* documentation and/or other materials provided with the +* distribution. +* +* Neither the name of Texas Instruments Incorporated nor the names of +* its contributors may be used to endorse or promote products derived +* from this software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +/* Entry Point */ +ENTRY( entry ) + +/* System memory map */ +MEMORY +{ + /* Application is stored in and executes from SRAM */ + PROGRAM (RWX) : ORIGIN = 0x20000000, LENGTH = 0x1FD8 + BUFFERS (RWX) : ORIGIN = 0x20001FD8, LENGTH = 0x6028 +} + +/* Section allocation in memory */ +SECTIONS +{ + .text : + { + _text = .; + *(.entry*) + *(.text*) + _etext = .; + } > PROGRAM + + .data : + { _data = .; + *(.rodata*) + *(.data*) + _edata = .; + } + + .bss : + { + __bss_start__ = .; + _bss = .; + *(.bss*) + *(COMMON) + _ebss = .; + __bss_end__ = .; + } > PROGRAM + + .stack : + { + _stack = .; + *(.stack*) + _estack = .; + } > PROGRAM + + .buffers : + { + _buffers = .; + *(.buffers.g_cfg) + *(.buffers.g_buf1) + *(.buffers.g_buf2) + *(.buffers*) + _ebuffers = .; + } > BUFFERS +} diff --git a/contrib/loaders/flash/cc26xx/cc26x2_algo.inc b/contrib/loaders/flash/cc26xx/cc26x2_algo.inc new file mode 100644 index 000000000..9adb919f4 --- /dev/null +++ b/contrib/loaders/flash/cc26xx/cc26x2_algo.inc @@ -0,0 +1,2049 @@ +/* Autogenerated with ../../../../src/helper/bin2char.sh */ +0x08,0xb5,0x00,0xbf,0x00,0xbf,0x00,0xbf,0x00,0xbf,0xdf,0xf8,0x1c,0xd0,0x07,0x48, +0x07,0x49,0x4f,0xf0,0x00,0x02,0x88,0x42,0xb8,0xbf,0x40,0xf8,0x04,0x2b,0xfa,0xdb, +0x00,0xf0,0xa8,0xf9,0xfe,0xe7,0x00,0x00,0xf0,0x0e,0x00,0x20,0x54,0x13,0x00,0x20, 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copyright +* notice, this list of conditions and the following disclaimer. +* +* Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in the +* documentation and/or other materials provided with the +* distribution. +* +* Neither the name of Texas Instruments Incorporated nor the names of +* its contributors may be used to endorse or promote products derived +* from this software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#include +#include +#include "flash.h" + +/****************************************************************************** +* +* Defines for accesses to the security control in the customer configuration +* area in flash top sector. +* +******************************************************************************/ +#define CCFG_OFFSET_SECURITY CCFG_O_BL_CONFIG +#define CCFG_SIZE_SECURITY 0x00000014 + +/****************************************************************************** +* +* Default values for security control in customer configuration area in flash +* top sector. +* +******************************************************************************/ +const uint8_t g_ccfg_default_sec[] = { + 0xFF, 0xFF, 0xFF, 0xC5, + 0xFF, 0xFF, 0xFF, 0xFF, + 0xC5, 0xFF, 0xFF, 0xFF, + 0xC5, 0xC5, 0xC5, 0xFF, + 0xC5, 0xC5, 0xC5, 0xFF +}; + +typedef uint32_t (*flash_prg_pntr_t) (uint8_t *, uint32_t, uint32_t); +typedef uint32_t (*flash_sector_erase_pntr_t) (uint32_t); + +/****************************************************************************** +* +* Function prototypes for static functions +* +******************************************************************************/ +static void issue_fsm_command(flash_state_command_t command); +static void enable_sectors_for_write(void); +static uint32_t scale_cycle_values(uint32_t specified_timing, + uint32_t scale_value); +static void set_write_mode(void); +static void trim_for_write(void); +static void set_read_mode(void); + +/****************************************************************************** +* +* Erase a flash sector +* +******************************************************************************/ +uint32_t flash_sector_erase(uint32_t sector_address) +{ + uint32_t error_return; + flash_sector_erase_pntr_t func_pntr; + + /* Call ROM function */ + func_pntr = (uint32_t (*)(uint32_t))(ROM_API_FLASH_TABLE[5]); + error_return = func_pntr(sector_address); + + /* Enable standby because ROM function might have disabled it */ + HWREGBITW(FLASH_BASE + FLASH_O_CFG, FLASH_CFG_DIS_STANDBY_BITN) = 0; + + /* Return status of operation. */ + return error_return; +} + +/****************************************************************************** +* +* Erase all unprotected sectors in the flash main bank +* +******************************************************************************/ +uint32_t flash_bank_erase(bool force_precondition) +{ + uint32_t error_return; + uint32_t sector_address; + uint32_t reg_val; + + /* Enable all sectors for erase. */ + enable_sectors_for_write(); + + /* Clear the Status register. */ + issue_fsm_command(FAPI_CLEAR_STATUS); + + /* Enable erase of all sectors and enable precondition if required. */ + reg_val = HWREG(FLASH_BASE + FLASH_O_FSM_ST_MACHINE); + HWREG(FLASH_BASE + FLASH_O_FSM_WR_ENA) = FSM_REG_WRT_ENABLE; + HWREG(FLASH_BASE + FLASH_O_FSM_SECTOR1) = 0x00000000; + HWREG(FLASH_BASE + FLASH_O_FSM_SECTOR2) = 0x00000000; + if (force_precondition) + HWREG(FLASH_BASE + FLASH_O_FSM_ST_MACHINE) |= + FLASH_FSM_ST_MACHINE_DO_PRECOND; + HWREG(FLASH_BASE + FLASH_O_FSM_WR_ENA) = FSM_REG_WRT_DISABLE; + + /* Issue the bank erase command to the FSM. */ + issue_fsm_command(FAPI_ERASE_BANK); + + /* Wait for erase to finish. */ + while (flash_check_fsm_for_ready() == FAPI_STATUS_FSM_BUSY) + ; + + /* Update status. */ + error_return = flash_check_fsm_for_error(); + + /* Disable sectors for erase. */ + flash_disable_sectors_for_write(); + + /* Set configured precondition mode since it may have been forced on. */ + if (!(reg_val & FLASH_FSM_ST_MACHINE_DO_PRECOND)) { + HWREG(FLASH_BASE + FLASH_O_FSM_WR_ENA) = FSM_REG_WRT_ENABLE; + HWREG(FLASH_BASE + FLASH_O_FSM_ST_MACHINE) &= + ~FLASH_FSM_ST_MACHINE_DO_PRECOND; + HWREG(FLASH_BASE + FLASH_O_FSM_WR_ENA) = FSM_REG_WRT_DISABLE; + } + + /* Program security data to default values in the customer configuration */ + /* area within the flash top sector if erase was successful. */ + if (error_return == FAPI_STATUS_SUCCESS) { + sector_address = FLASHMEM_BASE + flash_size_get() - + flash_sector_size_get(); + error_return = flash_program((uint8_t *)g_ccfg_default_sec, + (sector_address + CCFG_OFFSET_SECURITY), + CCFG_SIZE_SECURITY); + } + + /* Return status of operation. */ + return error_return; +} + +/****************************************************************************** +* +* Programs unprotected main bank flash sectors +* +******************************************************************************/ +uint32_t flash_program(uint8_t *data_buffer, uint32_t address, uint32_t count) +{ + uint32_t error_return; + flash_prg_pntr_t func_pntr; + + /* Call ROM function */ + func_pntr = (uint32_t (*)(uint8_t *, uint32_t, uint32_t)) + (ROM_API_FLASH_TABLE[6]); + error_return = func_pntr(data_buffer, address, count); + + /* Enable standby because ROM function might have disabled it */ + HWREGBITW(FLASH_BASE + FLASH_O_CFG, FLASH_CFG_DIS_STANDBY_BITN) = 0; + + /* Return status of operation. */ + return error_return; +} + +/****************************************************************************** +* +* Disables all sectors for erase and programming on the active bank +* +******************************************************************************/ +void flash_disable_sectors_for_write(void) +{ + /* Configure flash back to read mode */ + set_read_mode(); + + /* Disable Level 1 Protection. */ + HWREG(FLASH_BASE + FLASH_O_FBPROT) = FLASH_FBPROT_PROTL1DIS; + + /* Disable all sectors for erase and programming. */ + HWREG(FLASH_BASE + FLASH_O_FBSE) = 0x0000; + + /* Enable Level 1 Protection. */ + HWREG(FLASH_BASE + FLASH_O_FBPROT) = 0; + + /* Protect sectors from sector erase. */ + HWREG(FLASH_BASE + FLASH_O_FSM_WR_ENA) = FSM_REG_WRT_ENABLE; + HWREG(FLASH_BASE + FLASH_O_FSM_SECTOR1) = 0xFFFFFFFF; + HWREG(FLASH_BASE + FLASH_O_FSM_SECTOR2) = 0xFFFFFFFF; + HWREG(FLASH_BASE + FLASH_O_FSM_WR_ENA) = FSM_REG_WRT_DISABLE; +} + +/****************************************************************************** +* +* Issues a command to the Flash State Machine. +* +******************************************************************************/ +static void issue_fsm_command(flash_state_command_t command) +{ + /* Enable write to FSM register. */ + HWREG(FLASH_BASE + FLASH_O_FSM_WR_ENA) = FSM_REG_WRT_ENABLE; + + /* Issue FSM command. */ + HWREG(FLASH_BASE + FLASH_O_FSM_CMD) = command; + + /* Start command execute. */ + HWREG(FLASH_BASE + FLASH_O_FSM_EXECUTE) = FLASH_CMD_EXEC; + + /* Disable write to FSM register. */ + HWREG(FLASH_BASE + FLASH_O_FSM_WR_ENA) = FSM_REG_WRT_DISABLE; +} + +/****************************************************************************** +* +* Enables all sectors for erase and programming on the active bank. +* +* This function disables the idle reading power reduction mode, selects the +* flash bank and enables all sectors for erase and programming on the active +* bank. +* Sectors may be protected from programming depending on the value of the +* FLASH_O_FSM_BSLPx registers. +* Sectors may be protected from erase depending on the value of the +* FLASH_O_FSM_BSLEx registers. Additional sector erase protection is set by +* the FLASH_O_FSM_SECTOR1 register. +* +******************************************************************************/ +static void enable_sectors_for_write(void) +{ + /* Trim flash module for program/erase operation. */ + trim_for_write(); + + /* Configure flash to write mode */ + set_write_mode(); + + /* Select flash bank. */ + HWREG(FLASH_BASE + FLASH_O_FMAC) = 0x00; + + /* Disable Level 1 Protection. */ + HWREG(FLASH_BASE + FLASH_O_FBPROT) = FLASH_FBPROT_PROTL1DIS; + + /* Enable all sectors for erase and programming. */ + HWREG(FLASH_BASE + FLASH_O_FBSE) = 0xFFFF; + + /* Enable Level 1 Protection */ + HWREG(FLASH_BASE + FLASH_O_FBPROT) = 0; +} + +/****************************************************************************** +* +* Trims the Flash Bank and Flash Pump for program/erase functionality +* +* This trimming will make it possible to perform erase and program operations +* of the flash. Trim values are loaded from factory configuration area +* (referred to as FCGF1). The trimming done by this function is valid until +* reset of the flash module. +* +* Some registers shall be written with a value that is a number of FCLK +* cycles. The trim values controlling these registers have a value of +* number of half us. FCLK = SysClk / ((RWAIT+1) x 2). +* +******************************************************************************/ +static void trim_for_write(void) +{ + uint32_t value; + uint32_t temp_val; + uint32_t fclk_scale; + uint32_t rwait; + + /* Return if flash is already trimmed for program/erase operations. */ + if (HWREG(FLASH_BASE + FLASH_O_FWFLAG) & FW_WRT_TRIMMED) + return; + + /* Configure the FSM registers */ + + /* Enable access to the FSM registers. */ + HWREG(FLASH_BASE + FLASH_O_FSM_WR_ENA) = FSM_REG_WRT_ENABLE; + + /* Determine the scaling value to be used on timing related trim values. */ + /* The value is based on the flash module clock frequency and RWAIT */ + rwait = (HWREG(FLASH_BASE + FLASH_O_FRDCTL) & + FLASH_FRDCTL_RWAIT_M) >> FLASH_FRDCTL_RWAIT_S; + fclk_scale = (16 * FLASH_MODULE_CLK_FREQ) / (rwait + 1); + + /* Configure Program pulse width bits 15:0. */ + /* (FCFG1 offset 0x188 bits 15:0). */ + value = (HWREG(FLASH_CFG_BASE + FCFG1_OFFSET + FCFG1_O_FLASH_PROG_EP) & + FCFG1_FLASH_PROG_EP_PROGRAM_PW_M) >> + FCFG1_FLASH_PROG_EP_PROGRAM_PW_S; + + value = scale_cycle_values(value, fclk_scale); + + HWREG(FLASH_BASE + FLASH_O_FSM_PRG_PW) = + (HWREG(FLASH_BASE + FLASH_O_FSM_PRG_PW) & + ~FLASH_FSM_PRG_PW_PROG_PUL_WIDTH_M) | + ((value << FLASH_FSM_PRG_PW_PROG_PUL_WIDTH_S) & + FLASH_FSM_PRG_PW_PROG_PUL_WIDTH_M); + + /* Configure Erase pulse width bits 31:0. */ + /* (FCFG1 offset 0x18C bits 31:0). */ + value = (HWREG(FLASH_CFG_BASE + FCFG1_OFFSET + FCFG1_O_FLASH_ERA_PW) & + FCFG1_FLASH_ERA_PW_ERASE_PW_M) >> + FCFG1_FLASH_ERA_PW_ERASE_PW_S; + + value = scale_cycle_values(value, fclk_scale); + + HWREG(FLASH_BASE + FLASH_O_FSM_ERA_PW) = + (HWREG(FLASH_BASE + FLASH_O_FSM_ERA_PW) & + ~FLASH_FSM_ERA_PW_FSM_ERA_PW_M) | + ((value << FLASH_FSM_ERA_PW_FSM_ERA_PW_S) & + FLASH_FSM_ERA_PW_FSM_ERA_PW_M); + + /* Configure no of flash clock cycles from EXECUTEZ going low to the the + verify data can be read in the program verify mode bits 7:0. */ + /* (FCFG1 offset 0x174 bits 23:16). */ + value = (HWREG(FLASH_CFG_BASE + FCFG1_OFFSET + FCFG1_O_FLASH_C_E_P_R) & + FCFG1_FLASH_C_E_P_R_PV_ACCESS_M) >> + FCFG1_FLASH_C_E_P_R_PV_ACCESS_S; + + value = scale_cycle_values(value, fclk_scale); + + HWREG(FLASH_BASE + FLASH_O_FSM_EX_VAL) = + (HWREG(FLASH_BASE + FLASH_O_FSM_EX_VAL) & + ~FLASH_FSM_EX_VAL_EXE_VALD_M) | + ((value << FLASH_FSM_EX_VAL_EXE_VALD_S) & + FLASH_FSM_EX_VAL_EXE_VALD_M); + + /* Configure the number of flash clocks from the start of the Read mode at + the end of the operations until the FSM clears the BUSY bit in FMSTAT. */ + /* (FCFG1 offset 0x178 bits 23:16). */ + value = (HWREG(FLASH_CFG_BASE + FCFG1_OFFSET + FCFG1_O_FLASH_P_R_PV) & + FCFG1_FLASH_P_R_PV_RH_M) >> + FCFG1_FLASH_P_R_PV_RH_S; + + HWREG(FLASH_BASE + FLASH_O_FSM_RD_H) = + (HWREG(FLASH_BASE + FLASH_O_FSM_RD_H) & + ~FLASH_FSM_RD_H_RD_H_M) | + ((value << FLASH_FSM_RD_H_RD_H_S) & + FLASH_FSM_RD_H_RD_H_M); + + /* Configure Program hold time */ + /* (FCFG1 offset 0x178 bits 31:24). */ + value = (HWREG(FLASH_CFG_BASE + FCFG1_OFFSET + FCFG1_O_FLASH_P_R_PV) & + FCFG1_FLASH_P_R_PV_PH_M) >> + FCFG1_FLASH_P_R_PV_PH_S; + + value = scale_cycle_values(value, fclk_scale); + + HWREG(FLASH_BASE + FLASH_O_FSM_P_OH) = + (HWREG(FLASH_BASE + FLASH_O_FSM_P_OH) & + ~FLASH_FSM_P_OH_PGM_OH_M) | + ((value << FLASH_FSM_P_OH_PGM_OH_S) & + FLASH_FSM_P_OH_PGM_OH_M); + + /* Configure Erase hold time */ + /* (FCFG1 offset 0x17C bits 31:24). */ + value = (HWREG(FLASH_CFG_BASE + FCFG1_OFFSET + FCFG1_O_FLASH_EH_SEQ) & + FCFG1_FLASH_EH_SEQ_EH_M) >> + FCFG1_FLASH_EH_SEQ_EH_S; + + value = scale_cycle_values(value, fclk_scale); + + HWREG(FLASH_BASE + FLASH_O_FSM_ERA_OH) = + (HWREG(FLASH_BASE + FLASH_O_FSM_ERA_OH) & + ~FLASH_FSM_ERA_OH_ERA_OH_M) | + ((value << FLASH_FSM_ERA_OH_ERA_OH_S) & + FLASH_FSM_ERA_OH_ERA_OH_M); + + /* Configure Program verify row switch time */ + /* (FCFG1 offset0x178 bits 15:8). */ + value = (HWREG(FLASH_CFG_BASE + FCFG1_OFFSET + FCFG1_O_FLASH_P_R_PV) & + FCFG1_FLASH_P_R_PV_PVH_M) >> + FCFG1_FLASH_P_R_PV_PVH_S; + + value = scale_cycle_values(value, fclk_scale); + + HWREG(FLASH_BASE + FLASH_O_FSM_PE_VH) = + (HWREG(FLASH_BASE + FLASH_O_FSM_PE_VH) & + ~FLASH_FSM_PE_VH_PGM_VH_M) | + ((value << FLASH_FSM_PE_VH_PGM_VH_S) & + FLASH_FSM_PE_VH_PGM_VH_M); + + /* Configure Program Operation Setup time */ + /* (FCFG1 offset 0x170 bits 31:24). */ + value = (HWREG(FLASH_CFG_BASE + FCFG1_OFFSET + FCFG1_O_FLASH_E_P) & + FCFG1_FLASH_E_P_PSU_M) >> + FCFG1_FLASH_E_P_PSU_S; + + HWREG(FLASH_BASE + FLASH_O_FSM_PE_OSU) = + (HWREG(FLASH_BASE + FLASH_O_FSM_PE_OSU) & + ~FLASH_FSM_PE_OSU_PGM_OSU_M) | + ((value << FLASH_FSM_PE_OSU_PGM_OSU_S) & + FLASH_FSM_PE_OSU_PGM_OSU_M); + + /* Configure Erase Operation Setup time */ + /* (FCGF1 offset 0x170 bits 23:16). */ + value = (HWREG(FLASH_CFG_BASE + FCFG1_OFFSET + FCFG1_O_FLASH_E_P) & + FCFG1_FLASH_E_P_ESU_M) >> + FCFG1_FLASH_E_P_ESU_S; + + HWREG(FLASH_BASE + FLASH_O_FSM_PE_OSU) = + (HWREG(FLASH_BASE + FLASH_O_FSM_PE_OSU) & + ~FLASH_FSM_PE_OSU_ERA_OSU_M) | + ((value << FLASH_FSM_PE_OSU_ERA_OSU_S) & + FLASH_FSM_PE_OSU_ERA_OSU_M); + + /* Confgure Program Verify Setup time */ + /* (FCFG1 offset 0x170 bits 15:8). */ + value = (HWREG(FLASH_CFG_BASE + FCFG1_OFFSET + FCFG1_O_FLASH_E_P) & + FCFG1_FLASH_E_P_PVSU_M) >> + FCFG1_FLASH_E_P_PVSU_S; + + HWREG(FLASH_BASE + FLASH_O_FSM_PE_VSU) = + (HWREG(FLASH_BASE + FLASH_O_FSM_PE_VSU) & + ~FLASH_FSM_PE_VSU_PGM_VSU_M) | + ((value << FLASH_FSM_PE_VSU_PGM_VSU_S) & + FLASH_FSM_PE_VSU_PGM_VSU_M); + + /* Configure Erase Verify Setup time */ + /* (FCFG1 offset 0x170 bits 7:0). */ + value = (HWREG(FLASH_CFG_BASE + FCFG1_OFFSET + FCFG1_O_FLASH_E_P) & + FCFG1_FLASH_E_P_EVSU_M) >> + FCFG1_FLASH_E_P_EVSU_S; + + HWREG(FLASH_BASE + FLASH_O_FSM_PE_VSU) = + (HWREG(FLASH_BASE + FLASH_O_FSM_PE_VSU) & + ~FLASH_FSM_PE_VSU_ERA_VSU_M) | + ((value << FLASH_FSM_PE_VSU_ERA_VSU_S) & + FLASH_FSM_PE_VSU_ERA_VSU_M); + + /* Configure Addr to EXECUTEZ low setup time */ + /* (FCFG1 offset 0x174 bits 15:12). */ + value = (HWREG(FLASH_CFG_BASE + FCFG1_OFFSET + FCFG1_O_FLASH_C_E_P_R) & + FCFG1_FLASH_C_E_P_R_A_EXEZ_SETUP_M) >> + FCFG1_FLASH_C_E_P_R_A_EXEZ_SETUP_S; + + HWREG(FLASH_BASE + FLASH_O_FSM_CMP_VSU) = + (HWREG(FLASH_BASE + FLASH_O_FSM_CMP_VSU) & + ~FLASH_FSM_CMP_VSU_ADD_EXZ_M) | + ((value << FLASH_FSM_CMP_VSU_ADD_EXZ_S) & + FLASH_FSM_CMP_VSU_ADD_EXZ_M); + + /* Configure Voltage Status Count */ + /* (FCFG1 offset 0x17C bits 15:12). */ + value = (HWREG(FLASH_CFG_BASE + FCFG1_OFFSET + FCFG1_O_FLASH_EH_SEQ) & + FCFG1_FLASH_EH_SEQ_VSTAT_M) >> + FCFG1_FLASH_EH_SEQ_VSTAT_S; + + HWREG(FLASH_BASE + FLASH_O_FSM_VSTAT) = + (HWREG(FLASH_BASE + FLASH_O_FSM_VSTAT) & + ~FLASH_FSM_VSTAT_VSTAT_CNT_M) | + ((value << FLASH_FSM_VSTAT_VSTAT_CNT_S) & + FLASH_FSM_VSTAT_VSTAT_CNT_M); + + /* Configure Repeat Verify action setup */ + /* (FCFG1 offset 0x174 bits 31:24). */ + value = (HWREG(FLASH_CFG_BASE + FCFG1_OFFSET + FCFG1_O_FLASH_C_E_P_R) & + FCFG1_FLASH_C_E_P_R_RVSU_M) >> + FCFG1_FLASH_C_E_P_R_RVSU_S; + + HWREG(FLASH_BASE + FLASH_O_FSM_EX_VAL) = + (HWREG(FLASH_BASE + FLASH_O_FSM_EX_VAL) & + ~FLASH_FSM_EX_VAL_REP_VSU_M) | + ((value << FLASH_FSM_EX_VAL_REP_VSU_S) & + FLASH_FSM_EX_VAL_REP_VSU_M); + + /* Configure Maximum Programming Pulses */ + /* (FCFG1 offset 0x184 bits 15:0). */ + value = (HWREG(FLASH_CFG_BASE + FCFG1_OFFSET + FCFG1_O_FLASH_PP) & + FCFG1_FLASH_PP_MAX_PP_M) >> + FCFG1_FLASH_PP_MAX_PP_S; + + HWREG(FLASH_BASE + FLASH_O_FSM_PRG_PUL) = + (HWREG(FLASH_BASE + FLASH_O_FSM_PRG_PUL) & + ~FLASH_FSM_PRG_PUL_MAX_PRG_PUL_M) | + ((value << FLASH_FSM_PRG_PUL_MAX_PRG_PUL_S) & + FLASH_FSM_PRG_PUL_MAX_PRG_PUL_M); + + /* Configure Beginning level for VHVCT used during erase modes */ + /* (FCFG1 offset 0x180 bits 31:16). */ + value = (HWREG(FLASH_CFG_BASE + FCFG1_OFFSET + FCFG1_O_FLASH_VHV_E) & + FCFG1_FLASH_VHV_E_VHV_E_START_M) >> + FCFG1_FLASH_VHV_E_VHV_E_START_S; + + HWREG(FLASH_BASE + FLASH_O_FSM_PRG_PUL) = + (HWREG(FLASH_BASE + FLASH_O_FSM_PRG_PUL) & + ~FLASH_FSM_PRG_PUL_BEG_EC_LEVEL_M) | + ((value << FLASH_FSM_PRG_PUL_BEG_EC_LEVEL_S) & + FLASH_FSM_PRG_PUL_BEG_EC_LEVEL_M); + + /* Configure Maximum EC Level */ + /* (FCFG1 offset 0x2B0 bits 21:18). */ + value = (HWREG(FLASH_CFG_BASE + FCFG1_OFFSET + FCFG1_O_FLASH_OTP_DATA3) & + FCFG1_FLASH_OTP_DATA3_MAX_EC_LEVEL_M) >> + FCFG1_FLASH_OTP_DATA3_MAX_EC_LEVEL_S; + + HWREG(FLASH_BASE + FLASH_O_FSM_ERA_PUL) = + (HWREG(FLASH_BASE + FLASH_O_FSM_ERA_PUL) & + ~FLASH_FSM_ERA_PUL_MAX_EC_LEVEL_M) | + ((value << FLASH_FSM_ERA_PUL_MAX_EC_LEVEL_S) & + FLASH_FSM_ERA_PUL_MAX_EC_LEVEL_M); + + /* Configure Maximum Erase Pulses */ + /* (FCFG1 offset 0x188 bits 31:16). */ + value = (HWREG(FLASH_CFG_BASE + FCFG1_OFFSET + FCFG1_O_FLASH_PROG_EP) & + FCFG1_FLASH_PROG_EP_MAX_EP_M) >> + FCFG1_FLASH_PROG_EP_MAX_EP_S; + + HWREG(FLASH_BASE + FLASH_O_FSM_ERA_PUL) = + (HWREG(FLASH_BASE + FLASH_O_FSM_ERA_PUL) & + ~FLASH_FSM_ERA_PUL_MAX_ERA_PUL_M) | + ((value << FLASH_FSM_ERA_PUL_MAX_ERA_PUL_S) & + FLASH_FSM_ERA_PUL_MAX_ERA_PUL_M); + + /* Configure the VHVCT Step Size. This is the number of erase pulses that + must be completed for each level before the FSM increments the + CUR_EC_LEVEL to the next higher level. Actual erase pulses per level + equals (EC_STEP_SIZE +1). The stepping is only needed for the VHVCT + voltage. */ + /* (FCFG1 offset 0x2B0 bits 31:23). */ + value = (HWREG(FLASH_CFG_BASE + FCFG1_OFFSET + FCFG1_O_FLASH_OTP_DATA3) & + FCFG1_FLASH_OTP_DATA3_EC_STEP_SIZE_M) >> + FCFG1_FLASH_OTP_DATA3_EC_STEP_SIZE_S; + + HWREG(FLASH_BASE + FLASH_O_FSM_STEP_SIZE) = + (HWREG(FLASH_BASE + FLASH_O_FSM_STEP_SIZE) & + ~FLASH_FSM_STEP_SIZE_EC_STEP_SIZE_M) | + ((value << FLASH_FSM_STEP_SIZE_EC_STEP_SIZE_S) & + FLASH_FSM_STEP_SIZE_EC_STEP_SIZE_M); + + /* Configure the hight of each EC step. This is the number of counts that + the CUR_EC_LEVEL will increment when going to a new level. Actual count + size equals (EC_STEP_HEIGHT + 1). The stepping applies only to the VHVCT + voltage. + The read trim value is decremented by 1 before written to the register + since actual counts equals (register value + 1). */ + /* (FCFG1 offset 0x180 bits 15:0). */ + value = (HWREG(FLASH_CFG_BASE + FCFG1_OFFSET + FCFG1_O_FLASH_VHV_E) & + FCFG1_FLASH_VHV_E_VHV_E_STEP_HIGHT_M) >> + FCFG1_FLASH_VHV_E_VHV_E_STEP_HIGHT_S; + + HWREG(FLASH_BASE + FLASH_O_FSM_EC_STEP_HEIGHT) = ((value - 1) & + FLASH_FSM_EC_STEP_HEIGHT_EC_STEP_HEIGHT_M); + + /* Configure Precondition used in erase operations */ + /* (FCFG1 offset 0x2B0 bit 22). */ + value = (HWREG(FLASH_CFG_BASE + FCFG1_OFFSET + FCFG1_O_FLASH_OTP_DATA3) & + FCFG1_FLASH_OTP_DATA3_DO_PRECOND_M) >> + FCFG1_FLASH_OTP_DATA3_DO_PRECOND_S; + + HWREG(FLASH_BASE + FLASH_O_FSM_ST_MACHINE) = + (HWREG(FLASH_BASE + FLASH_O_FSM_ST_MACHINE) & + ~FLASH_FSM_ST_MACHINE_DO_PRECOND_M) | + ((value << FLASH_FSM_ST_MACHINE_DO_PRECOND_S) & + FLASH_FSM_ST_MACHINE_DO_PRECOND_M); + + /* Enable the recommended Good Time function. */ + HWREG(FLASH_BASE + FLASH_O_FSM_ST_MACHINE) |= + FLASH_FSM_ST_MACHINE_ONE_TIME_GOOD; + + /* Disable write access to FSM registers. */ + HWREG(FLASH_BASE + FLASH_O_FSM_WR_ENA) = FSM_REG_WRT_DISABLE; + + /* Configure the voltage registers */ + + /* Unlock voltage registers (0x2080 - 0x2098). */ + HWREG(FLASH_BASE + FLASH_O_FLOCK) = 0xAAAA; + + /* Configure voltage level for the specified pump voltage of high + voltage supply input during erase operation VHVCT_E and TRIM13_E */ + /* (FCFG1 offset 0x190 bits[3:0] and bits[11:8]). */ + temp_val = HWREG(FLASH_CFG_BASE + FCFG1_OFFSET + FCFG1_O_FLASH_VHV); + + value = ((temp_val & FCFG1_FLASH_VHV_TRIM13_E_M)>> + FCFG1_FLASH_VHV_TRIM13_E_S) << FLASH_FVHVCT1_TRIM13_E_S; + value |= ((temp_val & FCFG1_FLASH_VHV_VHV_E_M)>> + FCFG1_FLASH_VHV_VHV_E_S) << FLASH_FVHVCT1_VHVCT_E_S; + + HWREG(FLASH_BASE + FLASH_O_FVHVCT1) = (HWREG(FLASH_BASE + FLASH_O_FVHVCT1) & + ~(FLASH_FVHVCT1_TRIM13_E_M | FLASH_FVHVCT1_VHVCT_E_M)) | value; + + /* Configure voltage level for the specified pump voltage of high voltage + supply input during program verify operation VHVCT_PV and TRIM13_PV */ + /* (OTP offset 0x194 bits[19:16] and bits[27:24]). */ + temp_val = HWREG(FLASH_CFG_BASE + FCFG1_OFFSET + FCFG1_O_FLASH_VHV_PV); + + value = ((temp_val & FCFG1_FLASH_VHV_PV_TRIM13_PV_M) >> + FCFG1_FLASH_VHV_PV_TRIM13_PV_S) << FLASH_FVHVCT1_TRIM13_PV_S; + value |= ((temp_val & FCFG1_FLASH_VHV_PV_VHV_PV_M) >> + FCFG1_FLASH_VHV_PV_VHV_PV_S) << FLASH_FVHVCT1_VHVCT_PV_S; + + HWREG(FLASH_BASE + FLASH_O_FVHVCT1) = (HWREG(FLASH_BASE + FLASH_O_FVHVCT1) & + ~(FLASH_FVHVCT1_TRIM13_PV_M | FLASH_FVHVCT1_VHVCT_PV_M)) | value; + + /* Configure voltage level for the specified pump voltage of high voltage + supply input during program operation VHVCT_P and TRIM13_P */ + /* (FCFG1 offset 0x190 bits[19:16] and bits[27:24]). */ + temp_val = HWREG(FLASH_CFG_BASE + FCFG1_OFFSET + FCFG1_O_FLASH_VHV); + + value = ((temp_val & FCFG1_FLASH_VHV_TRIM13_P_M) >> + FCFG1_FLASH_VHV_TRIM13_P_S) << FLASH_FVHVCT2_TRIM13_P_S; + value |= ((temp_val & FCFG1_FLASH_VHV_VHV_P_M) >> + FCFG1_FLASH_VHV_VHV_P_S) << FLASH_FVHVCT2_VHVCT_P_S; + + HWREG(FLASH_BASE + FLASH_O_FVHVCT2) = (HWREG(FLASH_BASE + FLASH_O_FVHVCT2) & + ~(FLASH_FVHVCT2_TRIM13_P_M | FLASH_FVHVCT2_VHVCT_P_M)) | value; + + /* Configure voltage level for the specified pump voltage of wordline power + supply for read mode */ + /* (FCFG1 offset 0x198 Bits 15:8). */ + value = (HWREG(FLASH_CFG_BASE + FCFG1_OFFSET + FCFG1_O_FLASH_V) & + FCFG1_FLASH_V_V_READ_M) >> FCFG1_FLASH_V_V_READ_S; + + HWREG(FLASH_BASE + FLASH_O_FVREADCT) = + (HWREG(FLASH_BASE + FLASH_O_FVREADCT) & + ~FLASH_FVREADCT_VREADCT_M) | + ((value << FLASH_FVREADCT_VREADCT_S) & + FLASH_FVREADCT_VREADCT_M); + + /* Configure the voltage level for the VCG 2.5 CT pump voltage */ + /* (FCFG1 offset 0x194 bits 15:8). */ + value = (HWREG(FLASH_CFG_BASE + FCFG1_OFFSET + FCFG1_O_FLASH_VHV_PV) & + FCFG1_FLASH_VHV_PV_VCG2P5_M) >> + FCFG1_FLASH_VHV_PV_VCG2P5_S; + + HWREG(FLASH_BASE + FLASH_O_FVNVCT) = + (HWREG(FLASH_BASE + FLASH_O_FVNVCT) & + ~FLASH_FVNVCT_VCG2P5CT_M) | + ((value << FLASH_FVNVCT_VCG2P5CT_S) & + FLASH_FVNVCT_VCG2P5CT_M); + + /* Configure the voltage level for the specified pump voltage of high + current power input during program operation */ + /* (FCFG1 offset 0x198 bits 31:24). */ + value = (HWREG(FLASH_CFG_BASE + FCFG1_OFFSET + FCFG1_O_FLASH_V) & + FCFG1_FLASH_V_VSL_P_M) >> + FCFG1_FLASH_V_VSL_P_S; + + HWREG(FLASH_BASE + FLASH_O_FVSLP) = + (HWREG(FLASH_BASE + FLASH_O_FVSLP) & + ~FLASH_FVSLP_VSL_P_M) | + ((value << FLASH_FVSLP_VSL_P_S) & + FLASH_FVSLP_VSL_P_M); + + /* Configure the voltage level for the specified pump voltage of wordline + power supply during programming operations */ + /* (OTP offset 0x198 bits 23:16). */ + value = (HWREG(FLASH_CFG_BASE + FCFG1_OFFSET + FCFG1_O_FLASH_V) & + FCFG1_FLASH_V_VWL_P_M) >> + FCFG1_FLASH_V_VWL_P_S; + + HWREG(FLASH_BASE + FLASH_O_FVWLCT) = + (HWREG(FLASH_BASE + FLASH_O_FVWLCT) & + ~FLASH_FVWLCT_VWLCT_P_M) | + ((value << FLASH_FVWLCT_VWLCT_P_S) & + FLASH_FVWLCT_VWLCT_P_M); + + /* Configure the pump's TRIM_1P7 port pins. */ + /* (FCFG1 offset 0x2B0 bits 17:16). */ + value = (HWREG(FLASH_CFG_BASE + FCFG1_OFFSET + FCFG1_O_FLASH_OTP_DATA3) & + FCFG1_FLASH_OTP_DATA3_TRIM_1P7_M) >> + FCFG1_FLASH_OTP_DATA3_TRIM_1P7_S; + + HWREG(FLASH_BASE + FLASH_O_FSEQPMP) = + (HWREG(FLASH_BASE + FLASH_O_FSEQPMP) & + ~FLASH_FSEQPMP_TRIM_1P7_M) | + ((value << FLASH_FSEQPMP_TRIM_1P7_S) & + FLASH_FSEQPMP_TRIM_1P7_M); + + /* Lock the voltage registers. */ + HWREG(FLASH_BASE + FLASH_O_FLOCK) = 0x55AA; + + /* Set trimmed flag. */ + HWREG(FLASH_BASE + FLASH_O_FWLOCK) = 5; + HWREG(FLASH_BASE + FLASH_O_FWFLAG) |= FW_WRT_TRIMMED; + HWREG(FLASH_BASE + FLASH_O_FWLOCK) = 0; +} + +/****************************************************************************** +* +* Used to scale the TI OTP values based on the FClk scaling value. +* +******************************************************************************/ +static uint32_t scale_cycle_values(uint32_t specified_timing, + uint32_t scale_value) +{ + uint32_t scaled_value = (specified_timing * scale_value) >> 6; + return scaled_value; +} + +/****************************************************************************** +* +* Used to set flash in read mode. +* +* Flash is configured with values loaded from OTP dependent on the current +* regulator mode. +* +******************************************************************************/ +static void set_read_mode(void) +{ + uint32_t trim_value; + uint32_t value; + + /* Configure the STANDBY_MODE_SEL, STANDBY_PW_SEL, DIS_STANDBY, DIS_IDLE, + VIN_AT_X and VIN_BY_PASS for read mode */ + if (HWREG(AON_PMCTL_BASE + AON_PMCTL_O_PWRCTL) & + AON_PMCTL_PWRCTL_EXT_REG_MODE) { + + /* Select trim values for external regulator mode: + Configure STANDBY_MODE_SEL (OTP offset 0x308 bit 7) + Configure STANDBY_PW_SEL (OTP offset 0x308 bit 6:5) + Must be done while the register bit field CONFIG.DIS_STANDBY = 1 */ + HWREG(FLASH_BASE + FLASH_O_CFG) |= FLASH_CFG_DIS_STANDBY; + + trim_value = + HWREG(FLASH_CFG_BASE + FCFG1_OFFSET + FCFG1_O_FLASH_OTP_DATA4); + + value = ((trim_value & + FCFG1_FLASH_OTP_DATA4_STANDBY_MODE_SEL_EXT_RD_M) >> + FCFG1_FLASH_OTP_DATA4_STANDBY_MODE_SEL_EXT_RD_S) << + FLASH_CFG_STANDBY_MODE_SEL_S; + + value |= ((trim_value & + FCFG1_FLASH_OTP_DATA4_STANDBY_PW_SEL_EXT_RD_M) >> + FCFG1_FLASH_OTP_DATA4_STANDBY_PW_SEL_EXT_RD_S) << + FLASH_CFG_STANDBY_PW_SEL_S; + + /* Configure DIS_STANDBY (OTP offset 0x308 bit 4). + Configure DIS_IDLE (OTP offset 0x308 bit 3). */ + value |= ((trim_value & + (FCFG1_FLASH_OTP_DATA4_DIS_STANDBY_EXT_RD_M | + FCFG1_FLASH_OTP_DATA4_DIS_IDLE_EXT_RD_M)) >> + FCFG1_FLASH_OTP_DATA4_DIS_IDLE_EXT_RD_S) << + FLASH_CFG_DIS_IDLE_S; + + HWREG(FLASH_BASE + FLASH_O_CFG) = (HWREG(FLASH_BASE + FLASH_O_CFG) & + ~(FLASH_CFG_STANDBY_MODE_SEL_M | FLASH_CFG_STANDBY_PW_SEL_M | + FLASH_CFG_DIS_STANDBY_M | FLASH_CFG_DIS_IDLE_M)) | value; + + /* Check if sample and hold functionality is disabled. */ + if (HWREG(FLASH_BASE + FLASH_O_CFG) & FLASH_CFG_DIS_IDLE) { + /* Wait for disabled sample and hold functionality to be stable. */ + while (!(HWREG(FLASH_BASE+FLASH_O_STAT) & FLASH_STAT_SAMHOLD_DIS)) + ; + } + + /* Configure VIN_AT_X (OTP offset 0x308 bits 2:0) */ + value = ((trim_value & + FCFG1_FLASH_OTP_DATA4_VIN_AT_X_EXT_RD_M) >> + FCFG1_FLASH_OTP_DATA4_VIN_AT_X_EXT_RD_S) << + FLASH_FSEQPMP_VIN_AT_X_S; + + /* Configure VIN_BY_PASS which is dependent on the VIN_AT_X value. + If VIN_AT_X = 7 then VIN_BY_PASS should be 0 otherwise + VIN_BY_PASS should be 1 */ + if (((value & FLASH_FSEQPMP_VIN_AT_X_M) >> + FLASH_FSEQPMP_VIN_AT_X_S) != 0x7) + value |= FLASH_FSEQPMP_VIN_BY_PASS; + + HWREG(FLASH_BASE + FLASH_O_FLOCK) = 0xAAAA; + HWREG(FLASH_BASE + FLASH_O_FSEQPMP) = + (HWREG(FLASH_BASE + FLASH_O_FSEQPMP) & + ~(FLASH_FSEQPMP_VIN_BY_PASS_M | + FLASH_FSEQPMP_VIN_AT_X_M)) | value; + HWREG(FLASH_BASE + FLASH_O_FLOCK) = 0x55AA; + } else { + + /* Select trim values for internal regulator mode: + Configure STANDBY_MODE_SEL (OTP offset 0x308 bit 15) + COnfigure STANDBY_PW_SEL (OTP offset 0x308 bit 14:13) + Must be done while the register bit field CONFIG.DIS_STANDBY = 1 */ + HWREG(FLASH_BASE + FLASH_O_CFG) |= FLASH_CFG_DIS_STANDBY; + + trim_value = + HWREG(FLASH_CFG_BASE + FCFG1_OFFSET + FCFG1_O_FLASH_OTP_DATA4); + + value = ((trim_value & + FCFG1_FLASH_OTP_DATA4_STANDBY_MODE_SEL_INT_RD_M) >> + FCFG1_FLASH_OTP_DATA4_STANDBY_MODE_SEL_INT_RD_S) << + FLASH_CFG_STANDBY_MODE_SEL_S; + + value |= ((trim_value & + FCFG1_FLASH_OTP_DATA4_STANDBY_PW_SEL_INT_RD_M) >> + FCFG1_FLASH_OTP_DATA4_STANDBY_PW_SEL_INT_RD_S) << + FLASH_CFG_STANDBY_PW_SEL_S; + + /* Configure DIS_STANDBY (OTP offset 0x308 bit 12). + Configure DIS_IDLE (OTP offset 0x308 bit 11). */ + value |= ((trim_value & + (FCFG1_FLASH_OTP_DATA4_DIS_STANDBY_INT_RD_M | + FCFG1_FLASH_OTP_DATA4_DIS_IDLE_INT_RD_M)) >> + FCFG1_FLASH_OTP_DATA4_DIS_IDLE_INT_RD_S) << + FLASH_CFG_DIS_IDLE_S; + + HWREG(FLASH_BASE + FLASH_O_CFG) = (HWREG(FLASH_BASE + FLASH_O_CFG) & + ~(FLASH_CFG_STANDBY_MODE_SEL_M | FLASH_CFG_STANDBY_PW_SEL_M | + FLASH_CFG_DIS_STANDBY_M | FLASH_CFG_DIS_IDLE_M)) | value; + + /* Check if sample and hold functionality is disabled. */ + if (HWREG(FLASH_BASE + FLASH_O_CFG) & FLASH_CFG_DIS_IDLE) { + /* Wait for disabled sample and hold functionality to be stable. */ + while (!(HWREG(FLASH_BASE + FLASH_O_STAT) & FLASH_STAT_SAMHOLD_DIS)) + ; + } + + /* Configure VIN_AT_X (OTP offset 0x308 bits 10:8) */ + value = (((trim_value & + FCFG1_FLASH_OTP_DATA4_VIN_AT_X_INT_RD_M) >> + FCFG1_FLASH_OTP_DATA4_VIN_AT_X_INT_RD_S) << + FLASH_FSEQPMP_VIN_AT_X_S); + + /* Configure VIN_BY_PASS which is dependent on the VIN_AT_X value. + If VIN_AT_X = 7 then VIN_BY_PASS should be 0 otherwise + VIN_BY_PASS should be 1 */ + if (((value & FLASH_FSEQPMP_VIN_AT_X_M) >> + FLASH_FSEQPMP_VIN_AT_X_S) != 0x7) + value |= FLASH_FSEQPMP_VIN_BY_PASS; + + HWREG(FLASH_BASE + FLASH_O_FLOCK) = 0xAAAA; + HWREG(FLASH_BASE + FLASH_O_FSEQPMP) = + (HWREG(FLASH_BASE + FLASH_O_FSEQPMP) & + ~(FLASH_FSEQPMP_VIN_BY_PASS_M | + FLASH_FSEQPMP_VIN_AT_X_M)) | value; + HWREG(FLASH_BASE + FLASH_O_FLOCK) = 0x55AA; + } +} + +/****************************************************************************** +* +* Used to set flash in write mode. +* +* Flash is configured with values loaded from OTP dependent on the current +* regulator mode. +* +******************************************************************************/ +static void set_write_mode(void) +{ + uint32_t trim_value; + uint32_t value; + + /* Configure the STANDBY_MODE_SEL, STANDBY_PW_SEL, DIS_STANDBY, DIS_IDLE, + VIN_AT_X and VIN_BY_PASS for program/erase mode */ + if (HWREG(AON_PMCTL_BASE + AON_PMCTL_O_PWRCTL) & + AON_PMCTL_PWRCTL_EXT_REG_MODE) { + + /* Select trim values for external regulator mode: + Configure STANDBY_MODE_SEL (OTP offset 0x308 bit 23) + Configure STANDBY_PW_SEL (OTP offset 0x308 bit 22:21) + Must be done while the register bit field CONFIG.DIS_STANDBY = 1 */ + HWREG(FLASH_BASE + FLASH_O_CFG) |= FLASH_CFG_DIS_STANDBY; + + trim_value = + HWREG(FLASH_CFG_BASE + FCFG1_OFFSET + FCFG1_O_FLASH_OTP_DATA4); + + value = ((trim_value & + FCFG1_FLASH_OTP_DATA4_STANDBY_MODE_SEL_EXT_WRT_M) >> + FCFG1_FLASH_OTP_DATA4_STANDBY_MODE_SEL_EXT_WRT_S) << + FLASH_CFG_STANDBY_MODE_SEL_S; + + value |= ((trim_value & + FCFG1_FLASH_OTP_DATA4_STANDBY_PW_SEL_EXT_WRT_M) >> + FCFG1_FLASH_OTP_DATA4_STANDBY_PW_SEL_EXT_WRT_S) << + FLASH_CFG_STANDBY_PW_SEL_S; + + /* Configure DIS_STANDBY (OTP offset 0x308 bit 20). + Configure DIS_IDLE (OTP offset 0x308 bit 19). */ + value |= ((trim_value & + (FCFG1_FLASH_OTP_DATA4_DIS_STANDBY_EXT_WRT_M | + FCFG1_FLASH_OTP_DATA4_DIS_IDLE_EXT_WRT_M)) >> + FCFG1_FLASH_OTP_DATA4_DIS_IDLE_EXT_WRT_S) << + FLASH_CFG_DIS_IDLE_S; + + HWREG(FLASH_BASE + FLASH_O_CFG) = (HWREG(FLASH_BASE + FLASH_O_CFG) & + ~(FLASH_CFG_STANDBY_MODE_SEL_M | FLASH_CFG_STANDBY_PW_SEL_M | + FLASH_CFG_DIS_STANDBY_M | FLASH_CFG_DIS_IDLE_M)) | value; + + /* Check if sample and hold functionality is disabled. */ + if (HWREG(FLASH_BASE + FLASH_O_CFG) & FLASH_CFG_DIS_IDLE) { + /* Wait for disabled sample and hold functionality to be stable. */ + while (!(HWREG(FLASH_BASE + FLASH_O_STAT) & FLASH_STAT_SAMHOLD_DIS)) + ; + } + + /* Configure VIN_AT_X (OTP offset 0x308 bits 18:16) */ + value = ((trim_value & + FCFG1_FLASH_OTP_DATA4_VIN_AT_X_EXT_WRT_M) >> + FCFG1_FLASH_OTP_DATA4_VIN_AT_X_EXT_WRT_S) << + FLASH_FSEQPMP_VIN_AT_X_S; + + /* Configure VIN_BY_PASS which is dependent on the VIN_AT_X value. + If VIN_AT_X = 7 then VIN_BY_PASS should be 0 otherwise + VIN_BY_PASS should be 1 */ + if (((value & FLASH_FSEQPMP_VIN_AT_X_M) >> + FLASH_FSEQPMP_VIN_AT_X_S) != 0x7) + value |= FLASH_FSEQPMP_VIN_BY_PASS; + + HWREG(FLASH_BASE + FLASH_O_FLOCK) = 0xAAAA; + HWREG(FLASH_BASE + FLASH_O_FSEQPMP) = + (HWREG(FLASH_BASE + FLASH_O_FSEQPMP) & + ~(FLASH_FSEQPMP_VIN_BY_PASS_M | + FLASH_FSEQPMP_VIN_AT_X_M)) | value; + HWREG(FLASH_BASE + FLASH_O_FLOCK) = 0x55AA; + } else { + /* Select trim values for internal regulator mode: + Configure STANDBY_MODE_SEL (OTP offset 0x308 bit 31) + COnfigure STANDBY_PW_SEL (OTP offset 0x308 bit 30:29) + Must be done while the register bit field CONFIG.DIS_STANDBY = 1 */ + HWREG(FLASH_BASE + FLASH_O_CFG) |= FLASH_CFG_DIS_STANDBY; + + trim_value = + HWREG(FLASH_CFG_BASE + FCFG1_OFFSET + FCFG1_O_FLASH_OTP_DATA4); + + value = ((trim_value & + FCFG1_FLASH_OTP_DATA4_STANDBY_MODE_SEL_INT_WRT_M) >> + FCFG1_FLASH_OTP_DATA4_STANDBY_MODE_SEL_INT_WRT_S) << + FLASH_CFG_STANDBY_MODE_SEL_S; + + value |= ((trim_value & + FCFG1_FLASH_OTP_DATA4_STANDBY_PW_SEL_INT_WRT_M) >> + FCFG1_FLASH_OTP_DATA4_STANDBY_PW_SEL_INT_WRT_S) << + FLASH_CFG_STANDBY_PW_SEL_S; + + /* Configure DIS_STANDBY (OTP offset 0x308 bit 28). + Configure DIS_IDLE (OTP offset 0x308 bit 27). */ + value |= ((trim_value & + (FCFG1_FLASH_OTP_DATA4_DIS_STANDBY_INT_WRT_M | + FCFG1_FLASH_OTP_DATA4_DIS_IDLE_INT_WRT_M)) >> + FCFG1_FLASH_OTP_DATA4_DIS_IDLE_INT_WRT_S) << + FLASH_CFG_DIS_IDLE_S; + + HWREG(FLASH_BASE + FLASH_O_CFG) = (HWREG(FLASH_BASE + FLASH_O_CFG) & + ~(FLASH_CFG_STANDBY_MODE_SEL_M | FLASH_CFG_STANDBY_PW_SEL_M | + FLASH_CFG_DIS_STANDBY_M | FLASH_CFG_DIS_IDLE_M)) | value; + + /* Check if sample and hold functionality is disabled. */ + if (HWREG(FLASH_BASE + FLASH_O_CFG) & FLASH_CFG_DIS_IDLE) { + /* Wait for disabled sample and hold functionality to be stable. */ + while (!(HWREG(FLASH_BASE + FLASH_O_STAT) & FLASH_STAT_SAMHOLD_DIS)) + ; + } + + /* Configure VIN_AT_X (OTP offset 0x308 bits 26:24) */ + value = ((trim_value & + FCFG1_FLASH_OTP_DATA4_VIN_AT_X_INT_WRT_M) >> + FCFG1_FLASH_OTP_DATA4_VIN_AT_X_INT_WRT_S) << + FLASH_FSEQPMP_VIN_AT_X_S; + + /* Configure VIN_BY_PASS which is dependent on the VIN_AT_X value. + If VIN_AT_X = 7 then VIN_BY_PASS should be 0 otherwise + VIN_BY_PASS should be 1 */ + if (((value & FLASH_FSEQPMP_VIN_AT_X_M) >> + FLASH_FSEQPMP_VIN_AT_X_S) != 0x7) + value |= FLASH_FSEQPMP_VIN_BY_PASS; + + HWREG(FLASH_BASE + FLASH_O_FLOCK) = 0xAAAA; + HWREG(FLASH_BASE + FLASH_O_FSEQPMP) = + (HWREG(FLASH_BASE + FLASH_O_FSEQPMP) & + ~(FLASH_FSEQPMP_VIN_BY_PASS_M | + FLASH_FSEQPMP_VIN_AT_X_M)) | value; + HWREG(FLASH_BASE + FLASH_O_FLOCK) = 0x55AA; + } +} diff --git a/contrib/loaders/flash/cc26xx/flash.h b/contrib/loaders/flash/cc26xx/flash.h new file mode 100644 index 000000000..ec1c24fc5 --- /dev/null +++ b/contrib/loaders/flash/cc26xx/flash.h @@ -0,0 +1,378 @@ +/****************************************************************************** +* +* Copyright (C) 2016-2018 Texas Instruments Incorporated - http://www.ti.com/ +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions +* are met: +* +* Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* +* Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in the +* documentation and/or other materials provided with the +* distribution. +* +* Neither the name of Texas Instruments Incorporated nor the names of +* its contributors may be used to endorse or promote products derived +* from this software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef OPENOCD_LOADERS_FLASH_CC26XX_FLASH_H +#define OPENOCD_LOADERS_FLASH_CC26XX_FLASH_H + +#ifdef __cplusplus +extern "C" +{ +#endif + +#include +#include +#include "hw_regs.h" + +/* Location of flash in memory map */ +#define FLASHMEM_BASE 0 + +/* Defines to access flash API calls in ROM */ +#define ROM_API_TABLE ((uint32_t *) 0x10000180) +#define ROM_VERSION (ROM_API_TABLE[0]) +#define ROM_API_FLASH_TABLE ((uint32_t *) (ROM_API_TABLE[10])) + +#if defined(DEVICE_CC26X2) + +/* Agama (CC26x2) specific definitions */ + +#define FLASH_ERASE_SIZE 8192 +/* Agama (and Agama 1M) has a maximum of 132 flash sectors (1056KB / 8KB) */ +#define FLASH_MAX_SECTOR_COUNT 132 +#define FLASH_SECTOR_BASE_M 0xFFFFE000 + +/* Bootloader Configuration */ +#define CCFG_O_BL_CONFIG 0x00001FD8 + +#elif defined(DEVICE_CC26X0) + +/* Chameleon (CC26x0) specific definitions */ + +#define FLASH_ERASE_SIZE 4096 +/* Chameleon has a maximum of 32 flash sectors (128KB / 4KB) */ +#define FLASH_MAX_SECTOR_COUNT 32 +#define FLASH_SECTOR_BASE_M 0xFFFFF000 + +/* Bootloader Configuration */ +#define CCFG_O_BL_CONFIG 0x00000FD8 + +#else +#error No DEVICE defined. +#endif + +/****************************************************************************** +* +* Values that can be returned from the API functions +* +******************************************************************************/ +#define FAPI_STATUS_SUCCESS 0x00000000 /* Function completed successfully */ +#define FAPI_STATUS_FSM_BUSY 0x00000001 /* FSM is Busy */ +#define FAPI_STATUS_FSM_READY 0x00000002 /* FSM is Ready */ +#define FAPI_STATUS_INCORRECT_DATABUFFER_LENGTH \ + 0x00000003 /* Incorrect parameter value */ +#define FAPI_STATUS_FSM_ERROR 0x00000004 /* Operation failed */ + +/****************************************************************************** +* +* Define used by the flash programming and erase functions +* +******************************************************************************/ +#define ADDR_OFFSET (0x1F800000 - FLASHMEM_BASE) + +/****************************************************************************** +* +* Define used for access to factory configuration area. +* +******************************************************************************/ +#define FCFG1_OFFSET 0x1000 + +/****************************************************************************** +* +* Define for the clock frequencey input to the flash module in number of MHz +* +******************************************************************************/ +#define FLASH_MODULE_CLK_FREQ 48 + +/****************************************************************************** +* +* Defined values for Flash State Machine commands +* +******************************************************************************/ +typedef enum { + FAPI_PROGRAM_DATA = 0x0002, /* Program data. */ + FAPI_ERASE_SECTOR = 0x0006, /* Erase sector. */ + FAPI_ERASE_BANK = 0x0008, /* Erase bank. */ + FAPI_VALIDATE_SECTOR = 0x000E, /* Validate sector. */ + FAPI_CLEAR_STATUS = 0x0010, /* Clear status. */ + FAPI_PROGRAM_RESUME = 0x0014, /* Program resume. */ + FAPI_ERASE_RESUME = 0x0016, /* Erase resume. */ + FAPI_CLEAR_MORE = 0x0018, /* Clear more. */ + FAPI_PROGRAM_SECTOR = 0x0020, /* Program sector. */ + FAPI_ERASE_OTP = 0x0030 /* Erase OTP. */ +} flash_state_command_t; + +/****************************************************************************** +* +* Defines for values written to the FLASH_O_FSM_WR_ENA register +* +******************************************************************************/ +#define FSM_REG_WRT_ENABLE 5 +#define FSM_REG_WRT_DISABLE 2 + +/****************************************************************************** +* +* Defines for the bank power mode field the FLASH_O_FBFALLBACK register +* +******************************************************************************/ +#define FBFALLBACK_SLEEP 0 +#define FBFALLBACK_DEEP_STDBY 1 +#define FBFALLBACK_ACTIVE 3 + +/****************************************************************************** +* +* Defines for the bank grace period and pump grace period +* +******************************************************************************/ +#define FLASH_BAGP 0x14 +#define FLASH_PAGP 0x14 + +/****************************************************************************** +* +* Defines for the FW flag bits in the FLASH_O_FWFLAG register +* +******************************************************************************/ +#define FW_WRT_TRIMMED 0x00000001 + +/****************************************************************************** +* +* Defines used by the flash programming functions +* +******************************************************************************/ +typedef volatile uint8_t fwp_write_byte; +#define FWPWRITE_BYTE_ADDRESS \ + ((fwp_write_byte *)((FLASH_BASE + FLASH_O_FWPWRITE0))) + +/****************************************************************************** +* +* Define for FSM command execution +* +******************************************************************************/ +#define FLASH_CMD_EXEC 0x15 + +/****************************************************************************** +* +* Get size of a flash sector in number of bytes. +* +* This function will return the size of a flash sector in number of bytes. +* +* Returns size of a flash sector in number of bytes. +* +******************************************************************************/ +static inline uint32_t flash_sector_size_get(void) +{ + uint32_t sector_size_in_kbyte; + + sector_size_in_kbyte = (HWREG(FLASH_BASE + FLASH_O_FCFG_B0_SSIZE0) & + FLASH_FCFG_B0_SSIZE0_B0_SECT_SIZE_M) >> + FLASH_FCFG_B0_SSIZE0_B0_SECT_SIZE_S; + + /* Return flash sector size in number of bytes. */ + return sector_size_in_kbyte * 1024; +} + +/****************************************************************************** +* +* Get the size of the flash. +* +* This function returns the size of the flash main bank in number of bytes. +* +* Returns the flash size in number of bytes. +* +******************************************************************************/ +static inline uint32_t flash_size_get(void) +{ + uint32_t num_of_sectors; + + /* Get number of flash sectors */ + num_of_sectors = (HWREG(FLASH_BASE + FLASH_O_FLASH_SIZE) & + FLASH_FLASH_SIZE_SECTORS_M) >> + FLASH_FLASH_SIZE_SECTORS_S; + + /* Return flash size in number of bytes */ + return num_of_sectors * flash_sector_size_get(); +} + +/****************************************************************************** +* +* Checks if the Flash state machine has detected an error. +* +* This function returns the status of the Flash State Machine indicating if +* an error is detected or not. Primary use is to check if an Erase or +* Program operation has failed. +* +* Please note that code can not execute in flash while any part of the flash +* is being programmed or erased. This function must be called from ROM or +* SRAM while any part of the flash is being programmed or erased. +* +* Returns status of Flash state machine: +* FAPI_STATUS_FSM_ERROR +* FAPI_STATUS_SUCCESS +* +******************************************************************************/ +static inline uint32_t flash_check_fsm_for_error(void) +{ + if (HWREG(FLASH_BASE + FLASH_O_FMSTAT) & FLASH_FMSTAT_CSTAT) + return FAPI_STATUS_FSM_ERROR; + else + return FAPI_STATUS_SUCCESS; +} + +/****************************************************************************** +* +* Checks if the Flash state machine is ready. +* +* This function returns the status of the Flash State Machine indicating if +* it is ready to accept a new command or not. Primary use is to check if an +* Erase or Program operation has finished. +* +* Please note that code can not execute in flash while any part of the flash +* is being programmed or erased. This function must be called from ROM or +* SRAM while any part of the flash is being programmed or erased. +* +* Returns readiness status of Flash state machine: +* FAPI_STATUS_FSM_READY +* FAPI_STATUS_FSM_BUSY +* +******************************************************************************/ +static inline uint32_t flash_check_fsm_for_ready(void) +{ + if (HWREG(FLASH_BASE + FLASH_O_STAT) & FLASH_STAT_BUSY) + return FAPI_STATUS_FSM_BUSY; + else + return FAPI_STATUS_FSM_READY; +} + +/****************************************************************************** +* +* Erase a flash sector. +* +* This function will erase the specified flash sector. The function will +* not return until the flash sector has been erased or an error condition +* occurred. If flash top sector is erased the function will program the +* the device security data bytes with default values. The device security +* data located in the customer configuration area of the flash top sector, +* must have valid values at all times. These values affect the configuration +* of the device during boot. +* +* Please note that code can not execute in flash while any part of the flash +* is being programmed or erased. This function must only be executed from ROM +* or SRAM. +* +* sector_address is the starting address in flash of the sector to be +* erased. +* +* Returns the status of the sector erase: +* FAPI_STATUS_SUCCESS : Success. +* FAPI_STATUS_INCORRECT_DATABUFFER_LENGTH : Invalid argument. +* FAPI_STATUS_FSM_ERROR : Programming error was encountered. +* +******************************************************************************/ +extern uint32_t flash_sector_erase(uint32_t sector_address); + +/****************************************************************************** +* +* Erase all unprotected sectors in the flash main bank. +* +* This function will erase all unprotected flash sectors. The function will +* not return until the flash sectors has been erased or an error condition +* occurred. Since the flash top sector is erased the function will program the +* the device security data bytes with default values. The device security +* data located in the customer configuration area of the flash top sector, +* must have valid values at all times. These values affect the configuration +* of the device during boot. The execution time of the operation increases if +* erase precondition is forced. This will cause the flash module to first +* program all 1 bits in the bank to 0 before the actual erase is started. +* +* force_precondition controls if erase precondition should be forced. +* +* Returns the status of the sector erase: +* FAPI_STATUS_SUCCESS : Success +* FAPI_STATUS_FSM_ERROR : Erase error was encountered. +* +******************************************************************************/ +extern uint32_t flash_bank_erase(bool force_precondition); + +/****************************************************************************** +* +* Programs unprotected main bank flash sectors. +* +* This function will program a sequence of bytes into the on-chip flash. +* Programming each location consists of the result of an AND operation +* of the new data and the existing data; in other words bits that contain +* 1 can remain 1 or be changed to 0, but bits that are 0 cannot be changed +* to 1. Therefore, a byte can be programmed multiple times as long as these +* rules are followed; if a program operation attempts to change a 0 bit to +* a 1 bit, that bit will not have its value changed. +* +* This function will not return until the data has been programmed or an +* programming error has occurred. +* +* Please note that code can not execute in flash while any part of the flash +* is being programmed or erased. This function must only be executed from ROM +* or SRAM. +* +* The data_buffer pointer cannot point to flash. +* +* data_buffer is a pointer to the data to be programmed. +* address is the starting address in flash to be programmed. +* count is the number of bytes to be programmed. +* +* Returns status of the flash programming: +* FAPI_STATUS_SUCCESS : Success. +* FAPI_STATUS_INCORRECT_DATABUFFER_LENGTH : Too many bytes were requested. +* FAPI_STATUS_FSM_ERROR : Programming error was encountered. +* +******************************************************************************/ +extern uint32_t flash_program(uint8_t *data_buffer, uint32_t address, + uint32_t count); + +/****************************************************************************** +* +* Disables all sectors for erase and programming on the active bank. +* +* This function disables all sectors for erase and programming on the active +* bank and enables the Idle Reading Power reduction mode if no low power +* mode is configured. Furthermore, an additional level of protection from +* erase is enabled. +* +* Please note that code can not execute in flash while any part of the flash +* is being programmed or erased. +* +******************************************************************************/ +extern void flash_disable_sectors_for_write(void); + +#ifdef __cplusplus +} +#endif + +#endif /* #ifndef OPENOCD_LOADERS_FLASH_CC26XX_FLASH_H */ diff --git a/contrib/loaders/flash/cc26xx/flashloader.c b/contrib/loaders/flash/cc26xx/flashloader.c new file mode 100644 index 000000000..2eaf61864 --- /dev/null +++ b/contrib/loaders/flash/cc26xx/flashloader.c @@ -0,0 +1,177 @@ +/****************************************************************************** +* +* Copyright (C) 2017-2018 Texas Instruments Incorporated - http://www.ti.com/ +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions +* are met: +* +* Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* +* Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in the +* documentation and/or other materials provided with the +* distribution. +* +* Neither the name of Texas Instruments Incorporated nor the names of +* its contributors may be used to endorse or promote products derived +* from this software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#include +#include +#include "flashloader.h" +#include "flash.h" + +/* Array holding erased state of the flash sectors. */ +static bool g_is_erased[FLASH_MAX_SECTOR_COUNT]; + +extern uint8_t g_retain_buf[]; + +uint32_t flashloader_init(struct flash_params *params, uint8_t *buf1, + uint8_t *buf2) +{ + /* Initialize params buffers */ + memset((void *)params, 0, 2 * sizeof(struct flash_params)); + params[0].buf_addr = (uint32_t)buf1; + params[1].buf_addr = (uint32_t)buf2; + + /* Mark all sectors at "not erased" */ + memset(g_is_erased, false, sizeof(g_is_erased)); + + return STATUS_OK; +} + +uint32_t flashloader_erase_and_program(uint8_t *src, uint32_t address, + uint32_t byte_count) +{ + if (byte_count > BUFFER_LEN) + return STATUS_FAILED_INVALID_ARGUMENTS; + + /* Erase affected sectors */ + uint32_t status = flashloader_erase_sectors(address, byte_count); + + if (status != STATUS_OK) + return status; + + /* Program data */ + status = flashloader_program(src, address, byte_count); + + return status; +} + +uint32_t flashloader_program_with_retain(uint8_t *src, uint32_t address, + uint32_t byte_count) +{ +#if (BUFFER_LEN > FLASH_ERASE_SIZE) +#error Buffer size cannot be larger than the flash sector size! +#endif + + uint32_t first_sector_idx; + uint32_t last_sector_idx; + uint32_t status = STATUS_OK; + uint32_t i; + + first_sector_idx = flashloader_address_to_sector(address); + last_sector_idx = flashloader_address_to_sector(address + byte_count - 1); + + /* Mark all sectors as "not erased" before starting */ + memset(g_is_erased, false, sizeof(g_is_erased)); + + uint32_t sec_offset = address % FLASH_ERASE_SIZE; + uint32_t curr_count; + uint32_t src_offset = 0; + + for (i = first_sector_idx; i <= last_sector_idx; i++) { + + /* Chop off at sector boundary if data goes into the next sector. */ + curr_count = byte_count; + if ((address + byte_count) > ((i+1) * FLASH_ERASE_SIZE)) + curr_count -= (address + byte_count) % FLASH_ERASE_SIZE; + + /* Copy flash sector to retain buffer */ + memcpy(g_retain_buf, (void *)(i * FLASH_ERASE_SIZE), FLASH_ERASE_SIZE); + + /* Copy data buffer to retain buffer */ + memcpy(&g_retain_buf[sec_offset], &src[src_offset], curr_count); + + /* Erase and program from retain buffer */ + status = flashloader_erase_and_program(g_retain_buf, + (i * FLASH_ERASE_SIZE), FLASH_ERASE_SIZE); + if (status != STATUS_OK) + return status; + + address += curr_count; + sec_offset = address % FLASH_ERASE_SIZE; + byte_count -= curr_count; + src_offset += curr_count; + } + + return status; +} + +uint32_t flashloader_erase_all(void) +{ + if (flash_bank_erase(true) != FAPI_STATUS_SUCCESS) + return STATUS_FAILED_ERASE_ALL; + + memset(g_is_erased, true, sizeof(g_is_erased)); + + return STATUS_OK; +} + +uint32_t flashloader_erase_sectors(uint32_t address, uint32_t byte_count) +{ + uint32_t first_sector_idx; + uint32_t last_sector_idx; + uint32_t status; + uint32_t idx; + + /* Floor address to the start of the sector and convert to sector number */ + first_sector_idx = flashloader_address_to_sector(address); + last_sector_idx = flashloader_address_to_sector(address + byte_count - 1); + + /* Erase given sector(s) */ + for (idx = first_sector_idx; idx <= last_sector_idx; idx++) { + + /* Only erase sectors that haven't already been erased */ + if (g_is_erased[idx] == false) { + status = flash_sector_erase(idx * FLASH_ERASE_SIZE); + if (status != FAPI_STATUS_SUCCESS) { + status = (STATUS_FAILED_SECTOR_ERASE | + ((idx << STATUS_EXT_INFO_S) & STATUS_EXT_INFO_M) | + ((status << STATUS_ROM_CODE_S) & STATUS_ROM_CODE_M)); + return status; + } + g_is_erased[idx] = true; + } + } + + return STATUS_OK; +} + +uint32_t flashloader_program(uint8_t *src, uint32_t address, + uint32_t byte_count) +{ + uint32_t status = flash_program(src, address, byte_count); + if (status != FAPI_STATUS_SUCCESS) { + status = (STATUS_FAILED_PROGRAM | + ((status << STATUS_ROM_CODE_S) & STATUS_ROM_CODE_M)); + } + + return STATUS_OK; +} diff --git a/contrib/loaders/flash/cc26xx/flashloader.h b/contrib/loaders/flash/cc26xx/flashloader.h new file mode 100644 index 000000000..aec74aaa9 --- /dev/null +++ b/contrib/loaders/flash/cc26xx/flashloader.h @@ -0,0 +1,187 @@ +/****************************************************************************** +* +* Copyright (C) 2017-2018 Texas Instruments Incorporated - http://www.ti.com/ +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions +* are met: +* +* Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* +* Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in the +* documentation and/or other materials provided with the +* distribution. +* +* Neither the name of Texas Instruments Incorporated nor the names of +* its contributors may be used to endorse or promote products derived +* from this software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef OPENOCD_LOADERS_FLASH_CC26XX_FLASHLOADER_H +#define OPENOCD_LOADERS_FLASH_CC26XX_FLASHLOADER_H + +#include +#include +#include +#include "flash.h" + +/* Number of elements in an array */ +#define NELEMS(a) (sizeof(a) / sizeof(a[0])) + +struct __attribute__((__packed__)) flash_params { + uint32_t dest; /* Destination address in flash */ + uint32_t len; /* Number of bytes */ + uint32_t cmd; /* Command */ + uint32_t full; /* Handshake signal. Is buffer ready? */ + uint32_t buf_addr; /* Address of data buffer. */ +}; + +typedef enum { + CMD_NO_ACTION = 0, /* No action, default value */ + CMD_ERASE_ALL = 1, /* Erase all unprotected sectors */ + CMD_PROGRAM = 2, /* Program data */ + CMD_ERASE_AND_PROGRAM = 3, /* Erase and program data */ + CMD_ERASE_AND_PROGRAM_WITH_RETAIN = 4, /* Erase and program, but retain */ + /* sector data outside given range */ + CMD_ERASE_SECTORS = 5 /* Erase unprotected sectors */ +} flash_commands_t; + +typedef enum { + BUFFER_EMPTY = 0x0, /* No data in buffer, flags last task complete */ + BUFFER_FULL = 0xFFFFFFFF /* Buffer has data, flags next task to start */ +} flash_handshake_t; + +#define STATUS_FLASHLOADER_STATUS_M 0x0000FFFF +#define STATUS_FLASHLOADER_STATUS_S 0 +#define STATUS_ROM_CODE_M 0x00FF0000 +#define STATUS_ROM_CODE_S 16 +#define STATUS_EXT_INFO_M 0xFF000000 +#define STATUS_EXT_INFO_S 24 + +typedef enum { + STATUS_OK = 0, + STATUS_FAILED_ERASE_ALL = 0x101, + STATUS_FAILED_SECTOR_ERASE = 0x102, + STATUS_FAILED_PROGRAM = 0x103, + STATUS_FAILED_INVALID_ARGUMENTS = 0x104, + STATUS_FAILED_UNKNOWN_COMMAND = 0x105, +} flash_status_t; + +/* The buffer size used by the flashloader. The size of 1 flash sector. */ +#define BUFFER_LEN FLASH_ERASE_SIZE + +/* +* This function initializes the flashloader. The application must +* allocate memory for the two data buffers and the flash_params structures. +* +* params Pointer an flash_params array with 2 elements. +* buf1 Pointer to data buffer 1 +* buf2 Pointer to data buffer 2 +* +* Returns STATUS_OK +* +*/ +extern uint32_t flashloader_init(struct flash_params *params, uint8_t *buf1, + uint8_t *buf2); + +/* +* Erase and program the necessary sectors. Data outside the given +* range will be deleted. +* +* src Pointer to buffer containing the data. +* address Start address in device flash +* byte_count The number of bytes to program +* +* Returns STATUS_OK on success. For status on failure: +* See flashloader_program() and flashloader_erase_sectors(). +* +*/ +extern uint32_t flashloader_erase_and_program(uint8_t *src, uint32_t address, + uint32_t byte_count); + +/* +* Erase and program the device sectors. Data outside the given +* data range will be kept unchanged. +* +* src Pointer to buffer containing the data. +* address Start address in device flash +* byte_count The number of bytes to program +* +* Returns STATUS_OK on success. For status on failure: +* See flashloader_program() and flashloader_erase_sectors(). +* +*/ +extern uint32_t flashloader_program_with_retain(uint8_t *src, uint32_t address, + uint32_t byte_count); + +/* +* Erases all flash sectors (that are not write-protected). +* +* Returns STATUS_OK on success. +* +*/ +extern uint32_t flashloader_erase_all(void); + +/* +* Erases the flash sectors affected by the given range. +* +* This function only erases sectors that are not already erased. +* +* start_addr The first address in the range. +* byte_count The number of bytes in the range. +* +* Returns STATUS_OK on success. Returns a combined status on failure: +* [31:24] The sector that failed. +* [23:16] ROM function status code. 0 means success. +* [16: 0] STATUS_FAILED_SECTOR_ERASE +* +*/ +extern uint32_t flashloader_erase_sectors(uint32_t start_addr, + uint32_t byte_count); + +/* +* Program the given range. +* +* This function does not erase anything, it assumes the sectors are ready to +* be programmed. +* +* src Pointer to buffer containing the data. +* address Start address in device flash +* byte_count The number of bytes to program +* +* Returns STATUS_OK on success. Returns a combined status value on failure: +* [31:16] ROM function status code. 0 means success. +* [15:0 ] STATUS_FAILED_PROGRAM +* +*/ +extern uint32_t flashloader_program(uint8_t *src, uint32_t address, + uint32_t byte_count); + +/* +* Convert the input address into a sector number. +* +* address The address. +* +* Returns the flash sector which the address resides in. The first sector +* is sector 0. +* +*/ +static inline uint32_t flashloader_address_to_sector(uint32_t address) + { return (address / FLASH_ERASE_SIZE); }; + +#endif /* #ifndef OPENOCD_LOADERS_FLASH_CC26XX_FLASHLOADER_H */ diff --git a/contrib/loaders/flash/cc26xx/hw_regs.h b/contrib/loaders/flash/cc26xx/hw_regs.h new file mode 100644 index 000000000..830d3af25 --- /dev/null +++ b/contrib/loaders/flash/cc26xx/hw_regs.h @@ -0,0 +1,1382 @@ +/****************************************************************************** +* +* Copyright (C) 2017-2018 Texas Instruments Incorporated - http://www.ti.com/ +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions +* are met: +* +* Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* +* Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in the +* documentation and/or other materials provided with the +* distribution. +* +* Neither the name of Texas Instruments Incorporated nor the names of +* its contributors may be used to endorse or promote products derived +* from this software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef OPENOCD_LOADERS_FLASH_CC26XX_HW_REGS_H +#define OPENOCD_LOADERS_FLASH_CC26XX_HW_REGS_H + +/****************************************************************************** +* +* Macros for direct hardware access. +* +* If using these macros the programmer should be aware of any limitations to +* the address accessed i.e. if it supports word and/or byte access. +* +******************************************************************************/ +/* Word (32 bit) access to address x */ +/* Read example : my32BitVar = HWREG(base_addr + offset) ; */ +/* Write example : HWREG(base_addr + offset) = my32BitVar ; */ +#define HWREG(x) (*((volatile unsigned long *)(x))) + +/* Half word (16 bit) access to address x */ +/* Read example : my16BitVar = HWREGH(base_addr + offset) ; */ +/* Write example : HWREGH(base_addr + offset) = my16BitVar ; */ +#define HWREGH(x) (*((volatile unsigned short *)(x))) + +/* Byte (8 bit) access to address x */ +/* Read example : my8BitVar = HWREGB(base_addr + offset) ; */ +/* Write example : HWREGB(base_addr + offset) = my8BitVar ; */ +#define HWREGB(x) (*((volatile unsigned char *)(x))) + +/****************************************************************************** +* +* Macro for access to bit-band supported addresses via the bit-band region. +* +* Macro calculates the corresponding address to access in the bit-band region +* based on the actual address of the memory/register and the bit number. +* +* Do NOT use this macro to access the bit-band region directly! +* +******************************************************************************/ +/* Bit-band access to address x bit number b using word access (32 bit) */ +#define HWREGBITW(x, b) \ + HWREG(((unsigned long)(x) & 0xF0000000) | 0x02000000 | \ + (((unsigned long)(x) & 0x000FFFFF) << 5) | ((b) << 2)) + +/****************************************************************************** +* +* Memory mapped components base address definitions +* +******************************************************************************/ +#define FLASH_BASE 0x40030000 +#define FLASH_CFG_BASE 0x50000000 +#define AON_PMCTL_BASE 0x40090000 + +/****************************************************************************** +* +* This section defines the register offsets of FLASH component +* +******************************************************************************/ + +/* FMC and Efuse Status */ +#define FLASH_O_STAT 0x0000001C + +/* Configuration */ +#define FLASH_O_CFG 0x00000024 + +/* Flash Size Configuration */ +#define FLASH_O_FLASH_SIZE 0x0000002C + +/* Firmware Lock */ +#define FLASH_O_FWLOCK 0x0000003C + +/* Firmware Flags */ +#define FLASH_O_FWFLAG 0x00000040 + +/* FMC Read Control */ +#define FLASH_O_FRDCTL 0x00002000 + +/* FMC Bank Protection */ +#define FLASH_O_FBPROT 0x00002030 + +/* FMC Bank Sector Enable */ +#define FLASH_O_FBSE 0x00002034 + +/* FMC Module Access Control */ +#define FLASH_O_FMAC 0x00002050 + +/* FMC Module Status */ +#define FLASH_O_FMSTAT 0x00002054 + +/* FMC Flash Lock */ +#define FLASH_O_FLOCK 0x00002064 + +/* FMC VREADCT Trim */ +#define FLASH_O_FVREADCT 0x00002080 + +/* FMC VHVCT1 Trim */ +#define FLASH_O_FVHVCT1 0x00002084 + +/* FMC VHVCT2 Trim */ +#define FLASH_O_FVHVCT2 0x00002088 + +/* FMC VNVCT Trim */ +#define FLASH_O_FVNVCT 0x00002090 + +/* FMC VSL_P Trim */ +#define FLASH_O_FVSLP 0x00002094 + +/* FMC VWLCT Trim */ +#define FLASH_O_FVWLCT 0x00002098 + +/* FMC Sequential Pump Information */ +#define FLASH_O_FSEQPMP 0x000020A8 + +/* FMC FSM Command */ +#define FLASH_O_FSM_CMD 0x0000220C + +/* FMC FSM Program/Erase Operation Setup */ +#define FLASH_O_FSM_PE_OSU 0x00002210 + +/* FMC FSM Voltage Status Setup */ +#define FLASH_O_FSM_VSTAT 0x00002214 + +/* FMC FSM Program/Erase Verify Setup */ +#define FLASH_O_FSM_PE_VSU 0x00002218 + +/* FMC FSM Compare Verify Setup */ +#define FLASH_O_FSM_CMP_VSU 0x0000221C + +/* FMC FSM EXECUTEZ to Valid Data */ +#define FLASH_O_FSM_EX_VAL 0x00002220 + +/* FMC FSM Read Mode Hold */ +#define FLASH_O_FSM_RD_H 0x00002224 + +/* FMC FSM Program Hold */ +#define FLASH_O_FSM_P_OH 0x00002228 + +/* FMC FSM Erase Operation Hold */ +#define FLASH_O_FSM_ERA_OH 0x0000222C + +/* FMC FSM Program/Erase Verify Hold */ +#define FLASH_O_FSM_PE_VH 0x00002234 + +/* FMC FSM Program Pulse Width */ +#define FLASH_O_FSM_PRG_PW 0x00002240 + +/* FMC FSM Erase Pulse Width */ +#define FLASH_O_FSM_ERA_PW 0x00002244 + +/* FMC FSM Maximum Programming Pulses */ +#define FLASH_O_FSM_PRG_PUL 0x00002268 + +/* FMC FSM Maximum Erase Pulses */ +#define FLASH_O_FSM_ERA_PUL 0x0000226C + +/* FMC FSM EC Step Size */ +#define FLASH_O_FSM_STEP_SIZE 0x00002270 + +/* FMC FSM EC Step Height */ +#define FLASH_O_FSM_EC_STEP_HEIGHT 0x00002278 + +/* FMC FSM_ST_MACHINE */ +#define FLASH_O_FSM_ST_MACHINE 0x0000227C + +/* FMC FSM Register Write Enable */ +#define FLASH_O_FSM_WR_ENA 0x00002288 + +/* FMC FSM Command Execute */ +#define FLASH_O_FSM_EXECUTE 0x000022B4 + +/* FMC FSM Sector Erased 1 */ +#define FLASH_O_FSM_SECTOR1 0x000022C0 + +/* FMC FSM Sector Erased 2 */ +#define FLASH_O_FSM_SECTOR2 0x000022C4 + +/* FMC Flash Bank 0 Starting Address */ +#define FLASH_O_FCFG_B0_START 0x00002410 + +/* FMC Flash Bank 0 Sector Size 0 */ +#define FLASH_O_FCFG_B0_SSIZE0 0x00002430 + +/****************************************************************************** +* +* Register: FLASH_O_STAT +* +******************************************************************************/ +/* Field: [2] SAMHOLD_DIS +* +* Status indicator of flash sample and hold sequencing logic. This bit will go +* to 1 some delay after CFG.DIS_IDLE is set to 1. +* 0: Not disabled +* 1: Sample and hold disabled and stable */ +#define FLASH_STAT_SAMHOLD_DIS 0x00000004 + +/* Field: [1] BUSY +* +* Fast version of the FMC FMSTAT.BUSY bit. +* This flag is valid immediately after the operation setting it (FMSTAT.BUSY +* is delayed some cycles) +* 0 : Not busy +* 1 : Busy */ +#define FLASH_STAT_BUSY 0x00000002 + +/****************************************************************************** +* +* Register: FLASH_O_CFG +* +******************************************************************************/ +/* Field: [8] STANDBY_MODE_SEL +* +* [Configured by boot firmware] +* STANDBY mode selection control. This bit, in conjunction with +* STANDBY_PW_SEL, determine which 1 of 4 sub-modes is selected for control of +* the behavior and timing of the STANDBY input to the pump. +* +* 0 : Legacy PG1 behavior is selected when STANDBY_PW_SEL = 00. This is +* referred to as sub-mode 1. When STANDBY_PW_SEL != 00, then sub-mode 2 +* behavior is selected. STANDBY will be glitchy in these modes. +* 1 : STANDBY pulse-width counter modes selected. In these two modes (referred +* to as sub-mode 3 and sub-mode 4), the low time pulse width of the STANDBY +* signal to the pump, is controlled by a programmable timer. STANDBY will not +* be glitchy in these modes. */ +#define FLASH_CFG_STANDBY_MODE_SEL_M 0x00000100 +#define FLASH_CFG_STANDBY_MODE_SEL_S 8 + +/* Field: [7:6] STANDBY_PW_SEL +* +* [Configured by boot firmware] +* STANDBY pulse width counter selection control. These bits, in conjunction +* with STANDBY_MODE_SEL, determine which 1 of 4 sub-modes is selected for +* control of the behavior and timing of the STANDBY input to the pump. +* +* 00 : Legacy PG1 behavior is selected when STANDBY_MODE_SEL=0. Sub-mode 4 is +* selected when STANDBY_MODE_SEL=1. In sub-mode 4, STANDBY will be low for at +* least 9 pump clock cycles. +* 01 : Sub-mode 2 or 3 is selected, and STANDBY will be low for at least 9 +* pump clock cycles. +* 10: Sub-mode 2 or 3 is selected, and STANDBY will be low for at least 5 pump +* clock cycles. +* 11: Sub-mode 2 or 3 is selected, and STANDBY will be low for at least 13 +* pump clock cycles. */ +#define FLASH_CFG_STANDBY_PW_SEL_M 0x000000C0 +#define FLASH_CFG_STANDBY_PW_SEL_S 6 + +/* Field: [1] DIS_STANDBY +* +* [Configured by boot firmware] +* Disable standby functionality in read idle state */ +#define FLASH_CFG_DIS_STANDBY 0x00000002 +#define FLASH_CFG_DIS_STANDBY_BITN 1 +#define FLASH_CFG_DIS_STANDBY_M 0x00000002 + +/* Field: [0] DIS_IDLE +* +* [Configured by boot firmware] +* Disable sample and hold functionality in read idle state */ +#define FLASH_CFG_DIS_IDLE 0x00000001 +#define FLASH_CFG_DIS_IDLE_M 0x00000001 +#define FLASH_CFG_DIS_IDLE_S 0 + +/****************************************************************************** +* +* Register: FLASH_O_FLASH_SIZE +* +******************************************************************************/ +/* Field: [7:0] SECTORS +* +* [Configured by boot firmware] +* Flash size. The number of flash sectors in the configured device. Read +* access to sectors equal to this number or higher will result in an error. +* The CCFG area is the sector (SECTORS - 1) Writing to this register is +* disabled by the CFG.CONFIGURED bit. */ +#define FLASH_FLASH_SIZE_SECTORS_M 0x000000FF +#define FLASH_FLASH_SIZE_SECTORS_S 0 + +/****************************************************************************** +* +* Register: FLASH_O_FRDCTL +* +******************************************************************************/ +/* Field: [11:8] RWAIT +* +* [Configured by boot firmware] +* FMC Wait State. This field determines the FLCLK period during FMC controlled +* flash accesses: +* - During power up/ power down / low power mode +* - During FSM operations like program, erase +* - During software interface mode (see FLOCK , FBSTROBES registers) +* FLCLK_period = HCLK_period X (RWAIT + 1), +* FSM state machine operations are usually twice this amount. This value +* should never be set less than 2. */ +#define FLASH_FRDCTL_RWAIT_M 0x00000F00 +#define FLASH_FRDCTL_RWAIT_S 8 + +/****************************************************************************** +* +* Register: FLASH_O_FBPROT +* +******************************************************************************/ +/* Field: [0] PROTL1DIS +* +* Level 1 Protection Disable bit. Setting this bit disables protection from +* writing to the FBAC.OTPPROTDIS bits as well as the Sector Enable registers +* FBSE for all banks. Clearing this bit enables protection and disables write +* access to the FBAC.OTPPROTDIS register bits and FBSE register. */ +#define FLASH_FBPROT_PROTL1DIS 0x00000001 + +/****************************************************************************** +* +* Register: FLASH_O_FMSTAT +* +******************************************************************************/ +/* Field: [4] CSTAT +* +* Command Status. Once the FSM starts any failure will set this bit. When set, +* this bit informs the host that the program, erase, or validate sector +* command failed and the command was stopped. This bit is cleared by the +* Clear_Status command. For some errors, this will be the only indication of +* an FSM error because the cause does not fall within the other error bit +* types. */ +#define FLASH_FMSTAT_CSTAT 0x00000010 + +/****************************************************************************** +* +* Register: FLASH_O_FVREADCT +* +******************************************************************************/ +/* Field: [3:0] VREADCT +* +* [Configured by boot firmware] +* These bits control the voltage level for the specified pump voltage of +* wordline power supply for read mode. */ +#define FLASH_FVREADCT_VREADCT_M 0x0000000F +#define FLASH_FVREADCT_VREADCT_S 0 + +/****************************************************************************** +* +* Register: FLASH_O_FVHVCT1 +* +******************************************************************************/ +/* Field: [23:20] TRIM13_E +* +* [Configured by boot firmware] +* These bits control the voltage level for the specified pump voltage of high +* voltage supply input during erase operation. */ +#define FLASH_FVHVCT1_TRIM13_E_M 0x00F00000 +#define FLASH_FVHVCT1_TRIM13_E_S 20 + +/* Field: [19:16] VHVCT_E +* +* [Configured by boot firmware] +* These bits control the voltage level for the specified pump voltage of high +* voltage supply input during erase operation. */ +#define FLASH_FVHVCT1_VHVCT_E_M 0x000F0000 +#define FLASH_FVHVCT1_VHVCT_E_S 16 + +/* Field: [7:4] TRIM13_PV +* +* [Configured by boot firmware] +* These bits control the voltage level for the specified pump voltage of high +* voltage supply input during program verify operation. */ +#define FLASH_FVHVCT1_TRIM13_PV_M 0x000000F0 +#define FLASH_FVHVCT1_TRIM13_PV_S 4 + +/* Field: [3:0] VHVCT_PV +* +* [Configured by boot firmware] +* These bits control the voltage level for the specified pump voltage of high +* voltage supply input during program verify operation. */ +#define FLASH_FVHVCT1_VHVCT_PV_M 0x0000000F +#define FLASH_FVHVCT1_VHVCT_PV_S 0 + +/****************************************************************************** +* +* Register: FLASH_O_FVHVCT2 +* +******************************************************************************/ +/* Field: [23:20] TRIM13_P +* +* [Configured by boot firmware] +* These bits control the voltage level for the specified pump voltage of high +* voltage supply input during program operation. */ +#define FLASH_FVHVCT2_TRIM13_P_M 0x00F00000 +#define FLASH_FVHVCT2_TRIM13_P_S 20 + +/* Field: [19:16] VHVCT_P +* +* [Configured by boot firmware] +* These bits control the voltage level for the specified pump voltage of high +* voltage supply input during program operation. */ +#define FLASH_FVHVCT2_VHVCT_P_M 0x000F0000 +#define FLASH_FVHVCT2_VHVCT_P_S 16 + +/****************************************************************************** +* +* Register: FLASH_O_FVNVCT +* +******************************************************************************/ +/* Field: [12:8] VCG2P5CT +* +* [Configured by boot firmware] +* These bits control the voltage level for the VCG 2.5 CT pump voltage. */ +#define FLASH_FVNVCT_VCG2P5CT_M 0x00001F00 +#define FLASH_FVNVCT_VCG2P5CT_S 8 + +/****************************************************************************** +* +* Register: FLASH_O_FVSLP +* +******************************************************************************/ +/* Field: [15:12] VSL_P +* +* [Configured by boot firmware] +* These bits control the voltage level for the specified pump voltage of high +* current power input during program operation. */ +#define FLASH_FVSLP_VSL_P_M 0x0000F000 +#define FLASH_FVSLP_VSL_P_S 12 + +/****************************************************************************** +* +* Register: FLASH_O_FVWLCT +* +******************************************************************************/ +/* Field: [4:0] VWLCT_P +* +* [Configured by boot firmware] +* These bits control the voltage level for the specified pump voltage of +* wordline power supply during programming operations. */ +#define FLASH_FVWLCT_VWLCT_P_M 0x0000001F +#define FLASH_FVWLCT_VWLCT_P_S 0 + +/****************************************************************************** +* +* Register: FLASH_O_FSEQPMP +* +******************************************************************************/ +/* Field: [21:20] TRIM_1P7 +* +* [Configured by boot firmware] +* This register goes directly to the pump's TRIM_1P7 port pins. */ +#define FLASH_FSEQPMP_TRIM_1P7_M 0x00300000 +#define FLASH_FSEQPMP_TRIM_1P7_S 20 + +/* Field: [14:12] VIN_AT_X +* +* This register controls to the pump's VIN_AT_XPX port pins with the following +* encoding; +* +* If VIN_BY_PASS=0 then pump VIN_AT_XPX is equal to VIN_AT_XIN input ports +* from the BATMON logic after clocking through synchronizers and the sequence +* checker FSM logic contained in the flash wrapper. +* +* If VIN_BY_PASS=1 and VIN_AT_X=??? +* +* 0: then all pump VIN_AT_XPX signals are 0. +* 1: then pump VIN_AT_1P7 is set. +* 2: then pump VIN_AT_2P1 is also set. +* 3: then pump VIN_AT_2P4 is also set. +* 4-7: then pump VIN_AT_3P0 is also set (ie all VIN_AT_XPX signals are 1). */ +#define FLASH_FSEQPMP_VIN_AT_X_M 0x00007000 +#define FLASH_FSEQPMP_VIN_AT_X_S 12 + +/* Field: [8] VIN_BY_PASS +* +* [Configured by boot firmware] +* +* When this bit is a zero, the pump's VIN_AT_XPX ports comes from the FMC +* input port VIN_AT_XIN. +* +* When this bit is a one, the pump's VIN_AT_XPX ports comes from the VIN_AT_X +* bits in 14:12. */ +#define FLASH_FSEQPMP_VIN_BY_PASS 0x00000100 +#define FLASH_FSEQPMP_VIN_BY_PASS_M 0x00000100 + +/****************************************************************************** +* +* Register: FLASH_O_FSM_PE_OSU +* +******************************************************************************/ +/* Field: [15:8] PGM_OSU +* +* [Configured by boot firmware] +* Program Operation Setup time. This determines the flash clocks from the mode +* change to program, to the start of the program pulse. */ +#define FLASH_FSM_PE_OSU_PGM_OSU_M 0x0000FF00 +#define FLASH_FSM_PE_OSU_PGM_OSU_S 8 + +/* Field: [7:0] ERA_OSU +* +* [Configured by boot firmware] +* Erase Operation Setup time. This determines the flash clocks from the mode +* change to erase, to the start of the erase pulse. */ +#define FLASH_FSM_PE_OSU_ERA_OSU_M 0x000000FF +#define FLASH_FSM_PE_OSU_ERA_OSU_S 0 + +/****************************************************************************** +* +* Register: FLASH_O_FSM_VSTAT +* +******************************************************************************/ +/* Field: [15:12] VSTAT_CNT +* +* [Configured by boot firmware] +* Voltage Status Count. Gives the number of consecutive HCLK pulses that must +* be out of range before a voltage-out-of-range status error is given in +* FMSTAT.VOLSTAT. One pulse in range will reset the counter. This is mainly a +* glitch filter on the voltage status pump signal. */ +#define FLASH_FSM_VSTAT_VSTAT_CNT_M 0x0000F000 +#define FLASH_FSM_VSTAT_VSTAT_CNT_S 12 + +/****************************************************************************** +* +* Register: FLASH_O_FSM_PE_VSU +* +******************************************************************************/ +/* Field: [15:8] PGM_VSU +* +* [Configured by boot firmware] +* Program Verify Setup time. This determines the flash clocks from the mode +* change to program verify, to the change of address and the beginning of the +* address setup time. */ +#define FLASH_FSM_PE_VSU_PGM_VSU_M 0x0000FF00 +#define FLASH_FSM_PE_VSU_PGM_VSU_S 8 + +/* Field: [7:0] ERA_VSU +* +* [Configured by boot firmware] +* Erase Verify Setup time. This determines the flash clocks from the mode +* change to erase verify, to the change of address and the beginning of the +* address setup time. */ +#define FLASH_FSM_PE_VSU_ERA_VSU_M 0x000000FF +#define FLASH_FSM_PE_VSU_ERA_VSU_S 0 + +/****************************************************************************** +* +* Register: FLASH_O_FSM_CMP_VSU +* +******************************************************************************/ +/* Field: [15:12] ADD_EXZ +* +* [Configured by boot firmware] +* Address to EXECUTEZ low setup time. This determines the flash clocks from +* the row address change to the time EXECUTEZ goes low. All operations use +* this value. */ +#define FLASH_FSM_CMP_VSU_ADD_EXZ_M 0x0000F000 +#define FLASH_FSM_CMP_VSU_ADD_EXZ_S 12 + +/****************************************************************************** +* +* Register: FLASH_O_FSM_EX_VAL +* +******************************************************************************/ +/* Field: [15:8] REP_VSU +* +* [Configured by boot firmware] +* Repeat Verify action setup. If a program or erase operation advances to the +* program_verify or erase_verify then this special shorter mode transition +* time will be used in place of FSM_PE_VSU.PGM_VSU or FSM_PE_VSU.ERA_VSU +* times. */ +#define FLASH_FSM_EX_VAL_REP_VSU_M 0x0000FF00 +#define FLASH_FSM_EX_VAL_REP_VSU_S 8 + +/* Field: [7:0] EXE_VALD +* +* [Configured by boot firmware] +* EXECUTEZ low to valid Data. Determines the number of Flash clock cycles from +* EXECUTEZ going low to the time the verify data can be read in the program +* verify mode. Erase and compact verify is always a constant value which is +* currently set at one flash clock. This value must be greater than 0. */ +#define FLASH_FSM_EX_VAL_EXE_VALD_M 0x000000FF +#define FLASH_FSM_EX_VAL_EXE_VALD_S 0 + +/****************************************************************************** +* +* Register: FLASH_O_FSM_RD_H +* +******************************************************************************/ +/* Field: [7:0] RD_H +* +* [Configured by boot firmware] +* Read mode hold. This determines the number of flash clocks from the start of +* the Read mode at the end of the operations until the FSM clears the +* FMSTAT.BUSY. Writing a zero to this register will result in a value of 1. +* The reset value of this register is 0x3Ah before FMC version 3.0.10.0 and +* 0x5Ah after this version. */ +#define FLASH_FSM_RD_H_RD_H_M 0x000000FF +#define FLASH_FSM_RD_H_RD_H_S 0 + +/****************************************************************************** +* +* Register: FLASH_O_FSM_P_OH +* +******************************************************************************/ +/* Field: [15:8] PGM_OH +* +* [Configured by boot firmware] +* EXECUTEZ high to mode change. This value determines the flash clocks from +* the EXECUTEZ going high at the end of a program operation to the time the +* mode can change. This value must be greater than or equal to one. */ +#define FLASH_FSM_P_OH_PGM_OH_M 0x0000FF00 +#define FLASH_FSM_P_OH_PGM_OH_S 8 + +/****************************************************************************** +* +* Register: FLASH_O_FSM_ERA_OH +* +******************************************************************************/ +/* Field: [15:0] ERA_OH +* +* [Configured by boot firmware] +* EXECUTEZ high to mode change. Determines the flash clocks from EXECUTEZ +* going high at the end of an erase operation to the time the mode can change. +* If a bank erase is happening, then this is the time to when the TEZ and TCR +* values for bank erase are released. The mode changes 10 flash clocks after +* they are released. This value must be greater than or equal to one. */ +#define FLASH_FSM_ERA_OH_ERA_OH_M 0x0000FFFF +#define FLASH_FSM_ERA_OH_ERA_OH_S 0 + +/****************************************************************************** +* +* Register: FLASH_O_FSM_PE_VH +* +******************************************************************************/ +/* Field: [15:8] PGM_VH +* +* [Configured by boot firmware] +* Program Verify Hold. This register determines the flash clocks from EXECUTEZ +* going high after a program verify to a mode change. This value must be +* greater than or equal to one */ +#define FLASH_FSM_PE_VH_PGM_VH_M 0x0000FF00 +#define FLASH_FSM_PE_VH_PGM_VH_S 8 + +/****************************************************************************** +* +* Register: FLASH_O_FSM_PRG_PW +* +******************************************************************************/ +/* Field: [15:0] PROG_PUL_WIDTH +* +* [Configured by boot firmware] +* Program Pulse width.This register gives the number of flash clocks that the +* EXECUTEZ signal is low in a program operation. */ +#define FLASH_FSM_PRG_PW_PROG_PUL_WIDTH_M 0x0000FFFF +#define FLASH_FSM_PRG_PW_PROG_PUL_WIDTH_S 0 + +/****************************************************************************** +* +* Register: FLASH_O_FSM_ERA_PW +* +******************************************************************************/ +/* Field: [31:0] FSM_ERA_PW +* +* [Configured by boot firmware] +* Erase Pulse width. This register gives the number flash clocks that the +* EXECUTEZ signal is low in an erase operation. */ +#define FLASH_FSM_ERA_PW_FSM_ERA_PW_M 0xFFFFFFFF +#define FLASH_FSM_ERA_PW_FSM_ERA_PW_S 0 + +/****************************************************************************** +* +* Register: FLASH_O_FSM_PRG_PUL +* +******************************************************************************/ +/* Field: [19:16] BEG_EC_LEVEL +* +* [Configured by boot firmware] +* Beginning level for VHVCT. This determines the beginning level for VHVCT +* that is used during erase modes. The pump voltage control registers supply +* the other values that do not change during FSM operations. The reset value +* is the same as FVHVCT1.VHVCT_E. */ +#define FLASH_FSM_PRG_PUL_BEG_EC_LEVEL_M 0x000F0000 +#define FLASH_FSM_PRG_PUL_BEG_EC_LEVEL_S 16 + +/* Field: [11:0] MAX_PRG_PUL +* +* [Configured by boot firmware] +* Maximum Programming Pulses. This register contains the maximum number of +* programming pulses allowed at one address. If it takes any more than this +* amount during a programming operation then the FSM will exit with an error +* and with the program violation, FMSTAT.PGV set, and the general error set, +* FMSTAT.CSTAT. Setting FSM_ST_MACHINE.OVERRIDE to 0 will allow more than this +* maximum value to occur without an error. During pre-conditioning for an +* erase operation the FSM programs all the bits to zero. If the maximum number +* of programming pulses is reached for an address, the FSM will continue with +* the next address and set the FMSTAT.PCV and the general error FMSTAT.CSTAT. +* If the FSM_ST_MACHINE.PREC_STOP_EN is set then the FSM will stop with errors +* when more than the maximum number of pulses is needed. The +* FSM_ST_MACHINE.OVERRIDE bit will take priority over the +* FSM_ST_MACHINE.PREC_STOP_EN and continue doing pulses without setting the +* error bits. Suspend operations will count a pulse if the program operation +* began no matter how long the pulse lasted before is was suspended. Frequent +* suspend or auto-suspend operations could result in max_pulse count error. */ +#define FLASH_FSM_PRG_PUL_MAX_PRG_PUL_M 0x00000FFF +#define FLASH_FSM_PRG_PUL_MAX_PRG_PUL_S 0 + +/****************************************************************************** +* +* Register: FLASH_O_FSM_ERA_PUL +* +******************************************************************************/ +/* Field: [19:16] MAX_EC_LEVEL +* +* [Configured by boot firmware] +* Maximum VHVCT Level. This determines the maximum level for VHVCT that is +* used during erase modes. The FSM will stop advancing VHVCT once it counts up +* to the MAX_EC_LEVEL level from the beginning level. The MAX_EC_LEVEL + +* FSM_EC_STEP_HEIGHT.EC_STEP_HEIGHT must be less than 0x200. The reset value +* is the same as FVHVCT1.VHVCT_E. */ +#define FLASH_FSM_ERA_PUL_MAX_EC_LEVEL_M 0x000F0000 +#define FLASH_FSM_ERA_PUL_MAX_EC_LEVEL_S 16 + +/* Field: [11:0] MAX_ERA_PUL +* +* [Configured by boot firmware] +* Maximum Erase Pulses. This register contains the maximum number of erase +* pulses allowed at one address. If it takes any more than this amount the FSM +* will exit with an error and with both the FMSTAT.EV and FMSTAT.CSTAT bits +* set. Setting FSM_ST_MACHINE.OVERRIDE to 1 will allow more than this maximum +* value to occur without an error. Suspend operations will count a pulse if +* the erase operation began no matter how long the pulse lasted before is was +* suspended. Frequent suspend or auto-suspend operations could result in +* max_pulse count error. */ +#define FLASH_FSM_ERA_PUL_MAX_ERA_PUL_M 0x00000FFF +#define FLASH_FSM_ERA_PUL_MAX_ERA_PUL_S 0 + +/****************************************************************************** +* +* Register: FLASH_O_FSM_STEP_SIZE +* +******************************************************************************/ +/* Field: [24:16] EC_STEP_SIZE +* +* [Configured by boot firmware] +* VHVCT Step Size. This is the number of erase pulses that must be completed +* for each level before the FSM increments the FSM_PUL_CNTR.CUR_EC_LEVEL to +* the next higher level. Actual erase pulses per level equals (EC_STEP_SIZE +* +1). The stepping is only needed for the VHVCT voltage. */ +#define FLASH_FSM_STEP_SIZE_EC_STEP_SIZE_M 0x01FF0000 +#define FLASH_FSM_STEP_SIZE_EC_STEP_SIZE_S 16 + +/****************************************************************************** +* +* Register: FLASH_O_FSM_EC_STEP_HEIGHT +* +******************************************************************************/ +/* Field: [3:0] EC_STEP_HEIGHT +* +* [Configured by boot firmware] +* Height of each EC step. This is the number of counts that the +* FSM_PUL_CNTR.CUR_EC_LEVEL will increment when going to a new level. Actual +* count size equals (EC_STEP_HEIGHT + 1). The stepping applies only to the +* VHVCT voltage. If adding the height to the FSM_PUL_CNTR.CUR_EC_LEVEL results +* in a value higher than the FSM_ERA_PUL.MAX_EC_LEVEL then the +* FSM_PUL_CNTR.CUR_EC_LEVEL will be lowered to the MAX LEVEL before it is used +* in the next erase pulse. */ +#define FLASH_FSM_EC_STEP_HEIGHT_EC_STEP_HEIGHT_M 0x0000000F + +/****************************************************************************** +* +* Register: FLASH_O_FSM_ST_MACHINE +* +******************************************************************************/ +/* Field: [23] DO_PRECOND +* +* [Configured by boot firmware] +* Do preconditioning. When this bit is a one, the FSM will precondition the +* sector or bank before doing an erase operation. When zero, the FSM will just +* begin with the erase verify and skip the preconditioning. */ +#define FLASH_FSM_ST_MACHINE_DO_PRECOND 0x00800000 +#define FLASH_FSM_ST_MACHINE_DO_PRECOND_M 0x00800000 +#define FLASH_FSM_ST_MACHINE_DO_PRECOND_S 23 + +/* Field: [14] ONE_TIME_GOOD +* +* [Configured by boot firmware] +* One Time Good function. If this bit is a one then the 'One Time Good' +* function is enabled for all program operations. This includes operations +* inside the erase functions and other functions. When zero, this function is +* disabled for all modes. When doing the One Time Good function, the FSM will +* attempt to program a location with data. If a desired zero bit reads back +* from the flash one time as good then that bit is blocked from writing a zero +* to the flash array again for this address. When the address changes, all +* bits are unblocked. This prevents a bit from reading 0 in one programming +* pulse and then 1 in the next programming pulse. On the second time the bit +* would get a programming pulse even though it read 0 in an earlier read. If +* this bit is a zero then the zero bits will be masked for each program verify +* operation. It is recommended for this bit to be set to 1. */ +#define FLASH_FSM_ST_MACHINE_ONE_TIME_GOOD 0x00004000 + +/****************************************************************************** +* +* Register: FLASH_O_FCFG_B0_SSIZE0 +* +******************************************************************************/ +/* Field: [3:0] B0_SECT_SIZE +* +* Size of sectors in Bank 0. Common sector size for all sectors in the bank in +* 1K bytes multiples. +* 0x0: 0K bytes +* 0x1: 1K bytes(FLES) +* 0x2: 2K bytes +* 0x4: 4K bytes (FLEE) +* ... +* 0xF: 15K bytes */ +#define FLASH_FCFG_B0_SSIZE0_B0_SECT_SIZE_M 0x0000000F +#define FLASH_FCFG_B0_SSIZE0_B0_SECT_SIZE_S 0 + +/****************************************************************************** +* +* This section defines the register offsets of FCFG1 component +* +******************************************************************************/ + +/* Flash Erase and Program Setup Time */ +#define FCFG1_O_FLASH_E_P 0x00000170 + +/* Flash Compaction, Execute, Program and Read */ +#define FCFG1_O_FLASH_C_E_P_R 0x00000174 + +/* Flash Program, Read, and Program Verify */ +#define FCFG1_O_FLASH_P_R_PV 0x00000178 + +/* Flash Erase Hold and Sequence */ +#define FCFG1_O_FLASH_EH_SEQ 0x0000017C + +/* Flash VHV Erase */ +#define FCFG1_O_FLASH_VHV_E 0x00000180 + +/* Flash Program Pulse */ +#define FCFG1_O_FLASH_PP 0x00000184 + +/* Flash Program and Erase Pulse */ +#define FCFG1_O_FLASH_PROG_EP 0x00000188 + +/* Flash Erase Pulse Width */ +#define FCFG1_O_FLASH_ERA_PW 0x0000018C + +/* Flash VHV */ +#define FCFG1_O_FLASH_VHV 0x00000190 + +/* Flash VHV Program Verify */ +#define FCFG1_O_FLASH_VHV_PV 0x00000194 + +/* Flash Voltages */ +#define FCFG1_O_FLASH_V 0x00000198 + +/* Flash OTP Data 3 */ +#define FCFG1_O_FLASH_OTP_DATA3 0x000002B0 + +/* Flash OTP Data 4 */ +#define FCFG1_O_FLASH_OTP_DATA4 0x00000308 + +/****************************************************************************** +* +* Register: FCFG1_O_FLASH_E_P +* +******************************************************************************/ +/* Field: [31:24] PSU +* +* Program setup time in cycles. Value will be written to +* FLASH:FSM_PE_OSU.PGM_OSU by the flash device driver when an erase/program +* operation is initiated. */ +#define FCFG1_FLASH_E_P_PSU_M 0xFF000000 +#define FCFG1_FLASH_E_P_PSU_S 24 + +/* Field: [23:16] ESU +* +* Erase setup time in cycles. Value will be written to +* FLASH:FSM_PE_OSU.ERA_OSU by the flash device driver when an erase/program +* operation is initiated. */ +#define FCFG1_FLASH_E_P_ESU_M 0x00FF0000 +#define FCFG1_FLASH_E_P_ESU_S 16 + +/* Field: [15:8] PVSU +* +* Program verify setup time in cycles. Value will be written to +* FLASH:FSM_PE_VSU.PGM_VSU by the flash device driver when an erase/program +* operation is initiated. */ +#define FCFG1_FLASH_E_P_PVSU_M 0x0000FF00 +#define FCFG1_FLASH_E_P_PVSU_S 8 + +/* Field: [7:0] EVSU +* +* Erase verify setup time in cycles. Value will be written to +* FLASH:FSM_PE_VSU.ERA_VSU by the flash device driver when an erase/program +* operation is initiated. */ +#define FCFG1_FLASH_E_P_EVSU_M 0x000000FF +#define FCFG1_FLASH_E_P_EVSU_S 0 + +/****************************************************************************** +* +* Register: FCFG1_O_FLASH_C_E_P_R +* +******************************************************************************/ +/* Field: [31:24] RVSU +* +* Repeat verify setup time in cycles. Used for repeated verifies during +* program and erase. Value will be written to FLASH:FSM_EX_VAL.REP_VSU by the +* flash device driver when an erase/program operation is initiated. */ +#define FCFG1_FLASH_C_E_P_R_RVSU_M 0xFF000000 +#define FCFG1_FLASH_C_E_P_R_RVSU_S 24 + +/* Field: [23:16] PV_ACCESS +* +* Program verify EXECUTEZ->data valid time in half-microseconds. Value +* will be converted to number of FCLK cycles by by flash device driver and the +* converted value is written to FLASH:FSM_EX_VAL.EXE_VALD when an +* erase/program operation is initiated. */ +#define FCFG1_FLASH_C_E_P_R_PV_ACCESS_M 0x00FF0000 +#define FCFG1_FLASH_C_E_P_R_PV_ACCESS_S 16 + +/* Field: [15:12] A_EXEZ_SETUP +* +* Address->EXECUTEZ setup time in cycles. Value will be written to +* FLASH:FSM_CMP_VSU.ADD_EXZ by the flash device driver when an erase/program +* operation is initiated. */ +#define FCFG1_FLASH_C_E_P_R_A_EXEZ_SETUP_M 0x0000F000 +#define FCFG1_FLASH_C_E_P_R_A_EXEZ_SETUP_S 12 + +/****************************************************************************** +* +* Register: FCFG1_O_FLASH_P_R_PV +* +******************************************************************************/ +/* Field: [31:24] PH +* +* Program hold time in half-microseconds after SAFELV goes high. Value will be +* converted to number of FCLK cycles by the flash device driver and the +* converted value is written to FLASH:FSM_P_OH.PGM_OH when an erase/program +* operation is initiated. */ +#define FCFG1_FLASH_P_R_PV_PH_M 0xFF000000 +#define FCFG1_FLASH_P_R_PV_PH_S 24 + +/* Field: [23:16] RH +* +* Read hold/mode transition time in cycles. Value will be written to the RD_H +* field bits[7:0] of the FSM_RD_H register in the flash module by the flash +* device driver when an erase/program operation is initiated. */ +#define FCFG1_FLASH_P_R_PV_RH_M 0x00FF0000 +#define FCFG1_FLASH_P_R_PV_RH_S 16 + +/* Field: [15:8] PVH +* +* Program verify hold time in half-microseconds after SAFELV goes high. Value +* will be converted to number of FCLK cycles by the flash device driver and +* the converted value is written to FLASH:FSM_PE_VH.PGM_VH when an +* erase/program operation is initiated. */ +#define FCFG1_FLASH_P_R_PV_PVH_M 0x0000FF00 +#define FCFG1_FLASH_P_R_PV_PVH_S 8 + +/****************************************************************************** +* +* Register: FCFG1_O_FLASH_EH_SEQ +* +******************************************************************************/ +/* Field: [31:24] EH +* +* Erase hold time in half-microseconds after SAFELV goes high. Value will be +* converted to number of FCLK cycles by the flash device driver and the +* converted value is written to FLASH:FSM_ERA_OH.ERA_OH when an erase/program +* operation is initiated. */ +#define FCFG1_FLASH_EH_SEQ_EH_M 0xFF000000 +#define FCFG1_FLASH_EH_SEQ_EH_S 24 + +/* Field: [15:12] VSTAT +* +* Max number of HCLK cycles allowed for pump brown-out. Value will be written +* to FLASH:FSM_VSTAT.VSTAT_CNT when an erase/program operation is initiated. */ +#define FCFG1_FLASH_EH_SEQ_VSTAT_M 0x0000F000 +#define FCFG1_FLASH_EH_SEQ_VSTAT_S 12 + +/****************************************************************************** +* +* Register: FCFG1_O_FLASH_VHV_E +* +******************************************************************************/ +/* Field: [31:16] VHV_E_START +* +* Starting VHV-Erase CT for stairstep erase. Value will be written to +* FLASH:FSM_PRG_PUL.BEG_EC_LEVEL when erase/program operation is initiated. */ +#define FCFG1_FLASH_VHV_E_VHV_E_START_M 0xFFFF0000 +#define FCFG1_FLASH_VHV_E_VHV_E_START_S 16 + +/* Field: [15:0] VHV_E_STEP_HIGHT +* +* Number of VHV CTs to step after each erase pulse (up to the max). The actual +* FMC register value should be one less than this since the FMC starts +* counting from zero. Value will be written to +* FLASH:FSM_EC_STEP_HEIGHT.EC_STEP_HEIGHT when an erase/program operation is +* initiated. */ +#define FCFG1_FLASH_VHV_E_VHV_E_STEP_HIGHT_M 0x0000FFFF +#define FCFG1_FLASH_VHV_E_VHV_E_STEP_HIGHT_S 0 + +/****************************************************************************** +* +* Register: FCFG1_O_FLASH_PP +* +******************************************************************************/ +/* Field: [15:0] MAX_PP +* +* Max program pulse limit per program operation. Value will be written to +* FLASH:FSM_PRG_PUL.MAX_PRG_PUL when an erase/program operation is initiated. */ +#define FCFG1_FLASH_PP_MAX_PP_M 0x0000FFFF +#define FCFG1_FLASH_PP_MAX_PP_S 0 + +/****************************************************************************** +* +* Register: FCFG1_O_FLASH_PROG_EP +* +******************************************************************************/ +/* Field: [31:16] MAX_EP +* +* Max erase pulse limit per erase operation. Value will be written to +* FLASH:FSM_ERA_PUL.MAX_ERA_PUL when an erase/program operation is initiated. */ +#define FCFG1_FLASH_PROG_EP_MAX_EP_M 0xFFFF0000 +#define FCFG1_FLASH_PROG_EP_MAX_EP_S 16 + +/* Field: [15:0] PROGRAM_PW +* +* Program pulse width in half-microseconds. Value will be converted to number +* of FCLK cycles by the flash device driver and the converted value is written +* to FLASH:FSM_PRG_PW.PROG_PUL_WIDTH when a erase/program operation is +* initiated. */ +#define FCFG1_FLASH_PROG_EP_PROGRAM_PW_M 0x0000FFFF +#define FCFG1_FLASH_PROG_EP_PROGRAM_PW_S 0 + +/****************************************************************************** +* +* Register: FCFG1_O_FLASH_ERA_PW +* +******************************************************************************/ +/* Field: [31:0] ERASE_PW +* +* Erase pulse width in half-microseconds. Value will be converted to number of +* FCLK cycles by the flash device driver and the converted value is written to +* FLASH:FSM_ERA_PW.FSM_ERA_PW when a erase/program operation is initiated. */ +#define FCFG1_FLASH_ERA_PW_ERASE_PW_M 0xFFFFFFFF +#define FCFG1_FLASH_ERA_PW_ERASE_PW_S 0 + +/****************************************************************************** +* +* Register: FCFG1_O_FLASH_VHV +* +******************************************************************************/ +/* Field: [27:24] TRIM13_P +* +* Value will be written to FLASH:FVHVCT2.TRIM13_P by the flash device driver +* when an erase/program operation is initiated. */ +#define FCFG1_FLASH_VHV_TRIM13_P_M 0x0F000000 +#define FCFG1_FLASH_VHV_TRIM13_P_S 24 + +/* Field: [19:16] VHV_P +* +* Value will be written to FLASH:FVHVCT2.VHVCT_P by the flash device driver +* when an erase/program operation is initiated. */ +#define FCFG1_FLASH_VHV_VHV_P_M 0x000F0000 +#define FCFG1_FLASH_VHV_VHV_P_S 16 + +/* Field: [11:8] TRIM13_E +* +* Value will be written to FLASH:FVHVCT1.TRIM13_E by the flash device driver +* when an erase/program operation is initiated. */ +#define FCFG1_FLASH_VHV_TRIM13_E_M 0x00000F00 +#define FCFG1_FLASH_VHV_TRIM13_E_S 8 + +/* Field: [3:0] VHV_E +* +* Value will be written to FLASH:FVHVCT1.VHVCT_E by the flash device driver +* when an erase/program operation is initiated */ +#define FCFG1_FLASH_VHV_VHV_E_M 0x0000000F +#define FCFG1_FLASH_VHV_VHV_E_S 0 + +/****************************************************************************** +* +* Register: FCFG1_O_FLASH_VHV_PV +* +******************************************************************************/ +/* Field: [27:24] TRIM13_PV +* +* Value will be written to FLASH:FVHVCT1.TRIM13_PV by the flash device driver +* when an erase/program operation is initiated. */ +#define FCFG1_FLASH_VHV_PV_TRIM13_PV_M 0x0F000000 +#define FCFG1_FLASH_VHV_PV_TRIM13_PV_S 24 + +/* Field: [19:16] VHV_PV +* +* Value will be written to FLASH:FVHVCT1.VHVCT_PV by the flash device driver +* when an erase/program operation is initiated. */ +#define FCFG1_FLASH_VHV_PV_VHV_PV_M 0x000F0000 +#define FCFG1_FLASH_VHV_PV_VHV_PV_S 16 + +/* Field: [15:8] VCG2P5 +* +* Control gate voltage during read, read margin, and erase verify. Value will +* be written to FLASH:FVNVCT.VCG2P5CT by the flash device driver when an +* erase/program operation is initiated. */ +#define FCFG1_FLASH_VHV_PV_VCG2P5_M 0x0000FF00 +#define FCFG1_FLASH_VHV_PV_VCG2P5_S 8 + +/****************************************************************************** +* +* Register: FCFG1_O_FLASH_V +* +******************************************************************************/ +/* Field: [31:24] VSL_P +* +* Sourceline voltage applied to the selected block during programming. Value +* will be written to FLASH:FVSLP.VSL_P by the flash device driver when an +* erase/program operation is initiated. */ +#define FCFG1_FLASH_V_VSL_P_M 0xFF000000 +#define FCFG1_FLASH_V_VSL_P_S 24 + +/* Field: [23:16] VWL_P +* +* Wordline voltage applied to the selected half-row during programming. Value +* will be written to FLASH:FVWLCT.VWLCT_P by the flash device driver when an +* erase/program operation is initiated. */ +#define FCFG1_FLASH_V_VWL_P_M 0x00FF0000 +#define FCFG1_FLASH_V_VWL_P_S 16 + +/* Field: [15:8] V_READ +* +* Wordline voltage applied to the selected block during reads and verifies. +* Value will be written to FLASH:FVREADCT.VREADCT by the flash device driver +* when an erase/program operation is initiated. */ +#define FCFG1_FLASH_V_V_READ_M 0x0000FF00 +#define FCFG1_FLASH_V_V_READ_S 8 + +/****************************************************************************** +* +* Register: FCFG1_O_FLASH_OTP_DATA3 +* +******************************************************************************/ +/* Field: [31:23] EC_STEP_SIZE +* +* Value will be written to FLASH:FSM_STEP_SIZE.EC_STEP_SIZE by the flash +* device driver when a erase/program operation is initiated. */ +#define FCFG1_FLASH_OTP_DATA3_EC_STEP_SIZE_M 0xFF800000 +#define FCFG1_FLASH_OTP_DATA3_EC_STEP_SIZE_S 23 + +/* Field: [22] DO_PRECOND +* +* Value will be written to FLASH:FSM_ST_MACHINE.DO_PRECOND by the flash device +* driver when a erase/program operation is initiated. +* +* Note that during a Total Erase operation the flash bank will always be +* erased with Precondition enabled independent of the value of this FCFG1 bit +* field. */ +#define FCFG1_FLASH_OTP_DATA3_DO_PRECOND_M 0x00400000 +#define FCFG1_FLASH_OTP_DATA3_DO_PRECOND_S 22 + +/* Field: [21:18] MAX_EC_LEVEL +* +* Value will be written to FLASH:FSM_ERA_PUL.MAX_EC_LEVEL by the flash device +* driver when a erase/program operation is initiated. */ +#define FCFG1_FLASH_OTP_DATA3_MAX_EC_LEVEL_M 0x003C0000 +#define FCFG1_FLASH_OTP_DATA3_MAX_EC_LEVEL_S 18 + +/* Field: [17:16] TRIM_1P7 +* +* Value will be written to FLASH:FSEQPMP.TRIM_1P7 by the flash device driver +* when a erase/program operation is initiated. */ +#define FCFG1_FLASH_OTP_DATA3_TRIM_1P7_M 0x00030000 +#define FCFG1_FLASH_OTP_DATA3_TRIM_1P7_S 16 + +/****************************************************************************** +* +* Register: FCFG1_O_FLASH_OTP_DATA4 +* +******************************************************************************/ +/* Field: [31] STANDBY_MODE_SEL_INT_WRT +* +* If AON_PMCTL:PWRCTL.EXT_REG_MODE = 0, this value will be written to +* FLASH:CFG.STANDBY_MODE_SEL by flash device driver FW when a flash write +* operation is initiated. */ +#define FCFG1_FLASH_OTP_DATA4_STANDBY_MODE_SEL_INT_WRT_M 0x80000000 +#define FCFG1_FLASH_OTP_DATA4_STANDBY_MODE_SEL_INT_WRT_S 31 + +/* Field: [30:29] STANDBY_PW_SEL_INT_WRT +* +* If AON_PMCTL:PWRCTL.EXT_REG_MODE = 0, this value will be written to +* FLASH:CFG.STANDBY_PW_SEL by flash device driver FW when a flash write +* operation is initiated. */ +#define FCFG1_FLASH_OTP_DATA4_STANDBY_PW_SEL_INT_WRT_M 0x60000000 +#define FCFG1_FLASH_OTP_DATA4_STANDBY_PW_SEL_INT_WRT_S 29 + +/* Field: [28] DIS_STANDBY_INT_WRT +* +* If AON_PMCTL:PWRCTL.EXT_REG_MODE = 0, this value will be written to +* FLASH:CFG.DIS_STANDBY by flash device driver FW when a flash write operation +* is initiated. */ +#define FCFG1_FLASH_OTP_DATA4_DIS_STANDBY_INT_WRT_M 0x10000000 + +/* Field: [27] DIS_IDLE_INT_WRT +* +* If AON_PMCTL:PWRCTL.EXT_REG_MODE = 0, this value will be written to +* FLASH:CFG.DIS_IDLE by flash device driver FW when a flash write operation is +* initiated. */ +#define FCFG1_FLASH_OTP_DATA4_DIS_IDLE_INT_WRT_M 0x08000000 +#define FCFG1_FLASH_OTP_DATA4_DIS_IDLE_INT_WRT_S 27 + +/* Field: [26:24] VIN_AT_X_INT_WRT +* +* If AON_PMCTL:PWRCTL.EXT_REG_MODE = 0, this value will be written to +* FLASH:FSEQPMP.VIN_AT_X by flash device driver FW when a flash write +* operation is initiated. */ +#define FCFG1_FLASH_OTP_DATA4_VIN_AT_X_INT_WRT_M 0x07000000 +#define FCFG1_FLASH_OTP_DATA4_VIN_AT_X_INT_WRT_S 24 + +/* Field: [23] STANDBY_MODE_SEL_EXT_WRT +* +* If AON_PMCTL:PWRCTL.EXT_REG_MODE = 1, this value will be written to +* FLASH:CFG.STANDBY_MODE_SEL by flash device driver FW when a flash write +* operation is initiated. */ +#define FCFG1_FLASH_OTP_DATA4_STANDBY_MODE_SEL_EXT_WRT_M 0x00800000 +#define FCFG1_FLASH_OTP_DATA4_STANDBY_MODE_SEL_EXT_WRT_S 23 + +/* Field: [22:21] STANDBY_PW_SEL_EXT_WRT +* +* If AON_PMCTL:PWRCTL.EXT_REG_MODE = 1, this value will be written to +* FLASH:CFG.STANDBY_PW_SEL by flash device driver FW when a flash write +* operation is initiated. */ +#define FCFG1_FLASH_OTP_DATA4_STANDBY_PW_SEL_EXT_WRT_M 0x00600000 +#define FCFG1_FLASH_OTP_DATA4_STANDBY_PW_SEL_EXT_WRT_S 21 + +/* Field: [20] DIS_STANDBY_EXT_WRT +* +* If AON_PMCTL:PWRCTL.EXT_REG_MODE = 1, this value will be written to +* FLASH:CFG.DIS_STANDBY by flash device driver FW when a flash write operation +* is initiated. */ +#define FCFG1_FLASH_OTP_DATA4_DIS_STANDBY_EXT_WRT_M 0x00100000 + +/* Field: [19] DIS_IDLE_EXT_WRT +* +* If AON_PMCTL:PWRCTL.EXT_REG_MODE = 1, this value will be written to +* FLASH:CFG.DIS_IDLE by flash device driver FW when a flash write operation is +* initiated. */ +#define FCFG1_FLASH_OTP_DATA4_DIS_IDLE_EXT_WRT_M 0x00080000 +#define FCFG1_FLASH_OTP_DATA4_DIS_IDLE_EXT_WRT_S 19 + +/* Field: [18:16] VIN_AT_X_EXT_WRT +* +* If AON_PMCTL:PWRCTL.EXT_REG_MODE = 1, this value will be written to +* FLASH:FSEQPMP.VIN_AT_X by flash device driver FW when a flash write +* operation is initiated. */ +#define FCFG1_FLASH_OTP_DATA4_VIN_AT_X_EXT_WRT_M 0x00070000 +#define FCFG1_FLASH_OTP_DATA4_VIN_AT_X_EXT_WRT_S 16 + +/* Field: [15] STANDBY_MODE_SEL_INT_RD +* +* If AON_PMCTL:PWRCTL.EXT_REG_MODE = 0, this value will be written to +* FLASH:CFG.STANDBY_MODE_SEL both by boot FW while in safezone, and by flash +* device driver FW after completion of a flash write operation. */ +#define FCFG1_FLASH_OTP_DATA4_STANDBY_MODE_SEL_INT_RD_M 0x00008000 +#define FCFG1_FLASH_OTP_DATA4_STANDBY_MODE_SEL_INT_RD_S 15 + +/* Field: [14:13] STANDBY_PW_SEL_INT_RD +* +* If AON_PMCTL:PWRCTL.EXT_REG_MODE = 0, this value will be written to +* FLASH:CFG.STANDBY_PW_SEL both by boot FW while in safezone, and by flash +* device driver FW after completion of a flash write operation. */ +#define FCFG1_FLASH_OTP_DATA4_STANDBY_PW_SEL_INT_RD_M 0x00006000 +#define FCFG1_FLASH_OTP_DATA4_STANDBY_PW_SEL_INT_RD_S 13 + +/* Field: [12] DIS_STANDBY_INT_RD +* +* If AON_PMCTL:PWRCTL.EXT_REG_MODE = 0, this value will be written to +* FLASH:CFG.DIS_STANDBY both by boot FW while in safezone, and by flash device +* driver FW after completion of a flash write operation. */ +#define FCFG1_FLASH_OTP_DATA4_DIS_STANDBY_INT_RD_M 0x00001000 + +/* Field: [11] DIS_IDLE_INT_RD +* +* If AON_PMCTL:PWRCTL.EXT_REG_MODE = 0, this value will be written to +* FLASH:CFG.DIS_IDLE both by boot FW while in safezone, and by flash device +* driver FW after completion of a flash write operation. */ +#define FCFG1_FLASH_OTP_DATA4_DIS_IDLE_INT_RD_M 0x00000800 +#define FCFG1_FLASH_OTP_DATA4_DIS_IDLE_INT_RD_S 11 + +/* Field: [10:8] VIN_AT_X_INT_RD +* +* If AON_PMCTL:PWRCTL.EXT_REG_MODE = 0, this value will be written to +* FLASH:FSEQPMP.VIN_AT_X both by boot FW while in safezone, and by flash +* device driver FW after completion of a flash write operation. */ +#define FCFG1_FLASH_OTP_DATA4_VIN_AT_X_INT_RD_M 0x00000700 +#define FCFG1_FLASH_OTP_DATA4_VIN_AT_X_INT_RD_S 8 + +/* Field: [7] STANDBY_MODE_SEL_EXT_RD +* +* If AON_PMCTL:PWRCTL.EXT_REG_MODE = 1, this value will be written to +* FLASH:CFG.STANDBY_MODE_SEL both by boot FW while in safezone, and by flash +* device driver FW after completion of a flash write operation. */ +#define FCFG1_FLASH_OTP_DATA4_STANDBY_MODE_SEL_EXT_RD_M 0x00000080 +#define FCFG1_FLASH_OTP_DATA4_STANDBY_MODE_SEL_EXT_RD_S 7 + +/* Field: [6:5] STANDBY_PW_SEL_EXT_RD +* +* If AON_PMCTL:PWRCTL.EXT_REG_MODE = 1, this value will be written to +* FLASH:CFG.STANDBY_PW_SEL both by boot FW while in safezone, and by flash +* device driver FW after completion of a flash write operation. */ +#define FCFG1_FLASH_OTP_DATA4_STANDBY_PW_SEL_EXT_RD_M 0x00000060 +#define FCFG1_FLASH_OTP_DATA4_STANDBY_PW_SEL_EXT_RD_S 5 + +/* Field: [4] DIS_STANDBY_EXT_RD +* +* If AON_PMCTL:PWRCTL.EXT_REG_MODE = 1, this value will be written to +* FLASH:CFG.DIS_STANDBY both by boot FW while in safezone, and by flash device +* driver FW after completion of a flash write operation. */ +#define FCFG1_FLASH_OTP_DATA4_DIS_STANDBY_EXT_RD_M 0x00000010 + +/* Field: [3] DIS_IDLE_EXT_RD +* +* If AON_PMCTL:PWRCTL.EXT_REG_MODE = 1, this value will be written to +* FLASH:CFG.DIS_IDLE both by boot FW while in safezone, and by flash device +* driver FW after completion of a flash write operation. */ +#define FCFG1_FLASH_OTP_DATA4_DIS_IDLE_EXT_RD_M 0x00000008 +#define FCFG1_FLASH_OTP_DATA4_DIS_IDLE_EXT_RD_S 3 + +/* Field: [2:0] VIN_AT_X_EXT_RD +* +* If AON_PMCTL:PWRCTL.EXT_REG_MODE = 1, this value will be written to +* FLASH:FSEQPMP.VIN_AT_X both by boot FW while in safezone, and by flash +* device driver FW after completion of a flash write operation. */ +#define FCFG1_FLASH_OTP_DATA4_VIN_AT_X_EXT_RD_M 0x00000007 +#define FCFG1_FLASH_OTP_DATA4_VIN_AT_X_EXT_RD_S 0 + +/****************************************************************************** +* +* This section defines the register offsets of AON_PMCTL component +* +******************************************************************************/ + +/* Power Management Control */ +#if defined(DEVICE_CC26X2) +/* Agama (CC26x2) specific definition */ +#define AON_PMCTL_O_PWRCTL 0x00000010 +#elif defined(DEVICE_CC26X0) +/* Chameleon (CC26x0) specific definition */ +#define AON_PMCTL_O_PWRCTL 0x00000000 +#endif + +/* Field: [1] EXT_REG_MODE +* +* Status of source for VDDRsupply: +* +* 0: DCDC or GLDO are generating VDDR +* 1: DCDC and GLDO are bypassed and an external regulator supplies VDDR */ +#define AON_PMCTL_PWRCTL_EXT_REG_MODE 0x00000002 + +#endif /* #ifndef OPENOCD_LOADERS_FLASH_CC26XX_HW_REGS_H */ diff --git a/contrib/loaders/flash/cc26xx/main.c b/contrib/loaders/flash/cc26xx/main.c new file mode 100644 index 000000000..13204b458 --- /dev/null +++ b/contrib/loaders/flash/cc26xx/main.c @@ -0,0 +1,179 @@ +/****************************************************************************** +* +* Copyright (C) 2017-2018 Texas Instruments Incorporated - http://www.ti.com/ +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions +* are met: +* +* Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* +* Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in the +* documentation and/or other materials provided with the +* distribution. +* +* Neither the name of Texas Instruments Incorporated nor the names of +* its contributors may be used to endorse or promote products derived +* from this software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#include +#include +#include "flashloader.h" + +/* Data buffers used by host to communicate with flashloader */ + +/* Flashloader parameter structure. */ +__attribute__ ((section(".buffers.g_cfg"))) +volatile struct flash_params g_cfg[2]; +/* Data buffer 1. */ +__attribute__ ((section(".buffers.g_buf1"))) +uint8_t g_buf1[BUFFER_LEN]; +/* Data buffer 2. */ +__attribute__ ((section(".buffers.g_buf2"))) +uint8_t g_buf2[BUFFER_LEN]; + +/* Buffer used for program with retain feature */ +__attribute__ ((section(".buffers.g_retain_buf"))) +uint8_t g_retain_buf[BUFFER_LEN]; + +uint32_t g_curr_buf; /* Current buffer used. */ +uint32_t g_vims_ctl; /* Saved flash cache state. */ + +/****************************************************************************** +* +* This function stores the current VIMS configuration before +* - disabling VIMS flash cache +* - flushing the flash line buffers. +* +* Note Not using driverlib calls because it requires using "NO_ROM" define in +* order to work for both Cha. R1 and R2 using the same code. Manually +* doing the steps to minimize code footprint. +* +******************************************************************************/ +static void disable_flash_cache() +{ + /* 1. Make sure VIMS is not currently changing mode (VIMS:STAT register) */ + while ((HWREG(0x40034000) & 0x00000008) == 0x8) + ; + + /* Save current VIMS:CTL state */ + g_vims_ctl = HWREG(0x40034004); + + /* 2. Set VIMS mode to OFF and disable flash line buffers */ + uint32_t new_vims_ctl = g_vims_ctl | 0x33; + HWREG(0x40034004) = new_vims_ctl; + + /* 3. Wait for VIMS to have changed mode (VIMS:STAT register) */ + while ((HWREG(0x40034000) & 0x00000008) == 0x8) + ; +} + +/****************************************************************************** +* +* This function restores the VIMS configuration saved off by +* disable_flash_cache(). +* +* Note Not using driverlib calls because it requires using "NO_ROM" define in +* order to work for both Cha. R1 and R2 using the same code. Manually +* doing the steps to minimize code footprint. +* +******************************************************************************/ +static void restore_cache_state() +{ + HWREG(0x40034004) = g_vims_ctl; + + /* Wait for VIMS to have changed mode (VIMS:STAT register) */ + while ((HWREG(0x40034000) & 0x00000008) == 0x8) + ; +} + +/****************************************************************************** +* +* CC13xx/CC26xx flashloader main function. +* +******************************************************************************/ +int main(void) +{ + flashloader_init((struct flash_params *)g_cfg, g_buf1, g_buf2); + + g_curr_buf = 0; /* start with the first buffer */ + uint32_t status; + + while (1) { + /* Wait for host to signal buffer is ready */ + while (g_cfg[g_curr_buf].full == BUFFER_EMPTY) + ; + + disable_flash_cache(); + + /* Perform requested task */ + switch (g_cfg[g_curr_buf].cmd) { + case CMD_ERASE_ALL: + status = flashloader_erase_all(); + break; + case CMD_PROGRAM: + status = + flashloader_program( + (uint8_t *)g_cfg[g_curr_buf].buf_addr, + g_cfg[g_curr_buf].dest, g_cfg[g_curr_buf].len); + break; + case CMD_ERASE_AND_PROGRAM: + status = + flashloader_erase_and_program( + (uint8_t *)g_cfg[g_curr_buf].buf_addr, + g_cfg[g_curr_buf].dest, g_cfg[g_curr_buf].len); + break; + case CMD_ERASE_AND_PROGRAM_WITH_RETAIN: + status = + flashloader_program_with_retain( + (uint8_t *)g_cfg[g_curr_buf].buf_addr, + g_cfg[g_curr_buf].dest, g_cfg[g_curr_buf].len); + break; + case CMD_ERASE_SECTORS: + status = + flashloader_erase_sectors(g_cfg[g_curr_buf].dest, + g_cfg[g_curr_buf].len); + break; + default: + status = STATUS_FAILED_UNKNOWN_COMMAND; + break; + } + + restore_cache_state(); + + /* Enter infinite loop on error condition */ + if (status != STATUS_OK) { + g_cfg[g_curr_buf].full = status; + while (1) + ; + } + + /* Mark current task complete, and begin looking at next buffer */ + g_cfg[g_curr_buf].full = BUFFER_EMPTY; + g_curr_buf ^= 1; + } +} + +void _exit(int status) +{ + /* Enter infinite loop on hitting an exit condition */ + (void)status; /* Unused parameter */ + while (1) + ; +} diff --git a/contrib/loaders/flash/cc26xx/startup.c b/contrib/loaders/flash/cc26xx/startup.c new file mode 100644 index 000000000..70fd83650 --- /dev/null +++ b/contrib/loaders/flash/cc26xx/startup.c @@ -0,0 +1,97 @@ +/****************************************************************************** +* +* Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions +* are met: +* +* Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* +* Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in the +* documentation and/or other materials provided with the +* distribution. +* +* Neither the name of Texas Instruments Incorporated nor the names of +* its contributors may be used to endorse or promote products derived +* from this software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#include + +/****************************************************************************** +* +* The entry point for the application startup code. +* +******************************************************************************/ +extern int main(void); + +/****************************************************************************** +* +* Reserve space for the system stack. +* +******************************************************************************/ +__attribute__ ((section(".stack"))) +static uint32_t stack[100]; +const uint32_t stack_pntr = (uint32_t)stack + sizeof(stack); + +/****************************************************************************** +* +* The following are constructs created by the linker indicating where the +* the "bss" and "ebss" segments reside in memory. +* +******************************************************************************/ +extern uint32_t _bss; +extern uint32_t _ebss; + +/****************************************************************************** +* +* This is the entry point that handles setting the stack within the allowed +* workspace, initializing the .bss segment, and then jumping to main. +* +******************************************************************************/ +__attribute__ ((section(".entry"))) +void entry(void) +{ + /* Workaround for ITT instructions. */ + __asm(" NOP"); + __asm(" NOP"); + __asm(" NOP"); + __asm(" NOP"); + + /* Initialize stack pointer */ + __asm(" ldr sp, =stack_pntr"); + + /* Zero fill the bss segment. */ + __asm(" ldr r0, =_bss\n" + " ldr r1, =_ebss\n" + " mov r2, #0\n" + " .thumb_func\n" + " zero_loop:\n" + " cmp r0, r1\n" + " it lt\n" + " strlt r2, [r0], #4\n" + " blt zero_loop"); + + /* Call the application's entry point. */ + main(); + + /* If we ever return, enter an infinite loop */ + while (1) + ; +} diff --git a/doc/openocd.texi b/doc/openocd.texi index 0122224c7..3ae11df8c 100644 --- a/doc/openocd.texi +++ b/doc/openocd.texi @@ -5575,7 +5575,18 @@ flash erase_sector 0 0 127 # It will perform a mass erase on BlueNRG-2 @end example Triggering a mass erase is also useful when users want to disable readout protection. +@end deffn +@deffn {Flash Driver} cc26xx +All versions of the SimpleLink CC13xx and CC26xx microcontrollers from Texas +Instruments include internal flash. The cc26xx flash driver supports both the +CC13xx and CC26xx family of devices. The driver automatically recognizes the +specific version's flash parameters and autoconfigures itself. Flash bank 0 +starts at address 0. + +@example +flash bank $_FLASHNAME cc26xx 0 0 0 0 $_TARGETNAME +@end example @end deffn @deffn {Flash Driver} cc3220sf diff --git a/src/flash/nor/Makefile.am b/src/flash/nor/Makefile.am index 5e5cdcd3e..991869804 100644 --- a/src/flash/nor/Makefile.am +++ b/src/flash/nor/Makefile.am @@ -20,6 +20,7 @@ NOR_DRIVERS = \ %D%/avrf.c \ %D%/bluenrg-x.c \ %D%/cc3220sf.c \ + %D%/cc26xx.c \ %D%/cfi.c \ %D%/dsp5680xx_flash.c \ %D%/efm32.c \ @@ -66,6 +67,7 @@ NOR_DRIVERS = \ NORHEADERS = \ %D%/core.h \ %D%/cc3220sf.h \ + %D%/cc26xx.h \ %D%/cfi.h \ %D%/driver.h \ %D%/imp.h \ diff --git a/src/flash/nor/cc26xx.c b/src/flash/nor/cc26xx.c new file mode 100644 index 000000000..e6e9e5999 --- /dev/null +++ b/src/flash/nor/cc26xx.c @@ -0,0 +1,567 @@ +/*************************************************************************** + * Copyright (C) 2017 by Texas Instruments, Inc. * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program. If not, see . * + ***************************************************************************/ + +#ifdef HAVE_CONFIG_H +#include "config.h" +#endif + +#include "imp.h" +#include "cc26xx.h" +#include +#include +#include +#include +#include + +#define FLASH_TIMEOUT 8000 + +struct cc26xx_bank { + const char *family_name; + uint32_t icepick_id; + uint32_t user_id; + uint32_t device_type; + uint32_t sector_length; + bool probed; + struct working_area *working_area; + struct armv7m_algorithm armv7m_info; + const uint8_t *algo_code; + uint32_t algo_size; + uint32_t algo_working_size; + uint32_t buffer_addr[2]; + uint32_t params_addr[2]; +}; + +static int cc26xx_auto_probe(struct flash_bank *bank); + +static uint32_t cc26xx_device_type(uint32_t icepick_id, uint32_t user_id) +{ + uint32_t device_type = 0; + + switch (icepick_id & ICEPICK_ID_MASK) { + case CC26X0_ICEPICK_ID: + device_type = CC26X0_TYPE; + break; + case CC26X1_ICEPICK_ID: + device_type = CC26X1_TYPE; + break; + case CC13X0_ICEPICK_ID: + device_type = CC13X0_TYPE; + break; + case CC13X2_CC26X2_ICEPICK_ID: + default: + if ((user_id & USER_ID_CC13_MASK) != 0) + device_type = CC13X2_TYPE; + else + device_type = CC26X2_TYPE; + break; + } + + return device_type; +} + +static uint32_t cc26xx_sector_length(uint32_t icepick_id) +{ + uint32_t sector_length; + + switch (icepick_id & ICEPICK_ID_MASK) { + case CC26X0_ICEPICK_ID: + case CC26X1_ICEPICK_ID: + case CC13X0_ICEPICK_ID: + /* Chameleon family device */ + sector_length = CC26X0_SECTOR_LENGTH; + break; + case CC13X2_CC26X2_ICEPICK_ID: + default: + /* Agama family device */ + sector_length = CC26X2_SECTOR_LENGTH; + break; + } + + return sector_length; +} + +static int cc26xx_wait_algo_done(struct flash_bank *bank, uint32_t params_addr) +{ + struct target *target = bank->target; + struct cc26xx_bank *cc26xx_bank = bank->driver_priv; + + uint32_t status_addr = params_addr + CC26XX_STATUS_OFFSET; + uint32_t status = CC26XX_BUFFER_FULL; + long long start_ms; + long long elapsed_ms; + + int retval = ERROR_OK; + + start_ms = timeval_ms(); + while (CC26XX_BUFFER_FULL == status) { + retval = target_read_u32(target, status_addr, &status); + if (ERROR_OK != retval) + return retval; + + elapsed_ms = timeval_ms() - start_ms; + if (elapsed_ms > 500) + keep_alive(); + if (elapsed_ms > FLASH_TIMEOUT) + break; + }; + + if (CC26XX_BUFFER_EMPTY != status) { + LOG_ERROR("%s: Flash operation failed", cc26xx_bank->family_name); + return ERROR_FAIL; + } + + return ERROR_OK; +} + +static int cc26xx_init(struct flash_bank *bank) +{ + struct target *target = bank->target; + struct cc26xx_bank *cc26xx_bank = bank->driver_priv; + + int retval; + + /* Make sure we've probed the flash to get the device and size */ + retval = cc26xx_auto_probe(bank); + if (ERROR_OK != retval) + return retval; + + /* Check for working area to use for flash helper algorithm */ + if (NULL != cc26xx_bank->working_area) + target_free_working_area(target, cc26xx_bank->working_area); + retval = target_alloc_working_area(target, cc26xx_bank->algo_working_size, + &cc26xx_bank->working_area); + if (ERROR_OK != retval) + return retval; + + /* Confirm the defined working address is the area we need to use */ + if (CC26XX_ALGO_BASE_ADDRESS != cc26xx_bank->working_area->address) + return ERROR_TARGET_RESOURCE_NOT_AVAILABLE; + + /* Write flash helper algorithm into target memory */ + retval = target_write_buffer(target, CC26XX_ALGO_BASE_ADDRESS, + cc26xx_bank->algo_size, cc26xx_bank->algo_code); + if (ERROR_OK != retval) { + LOG_ERROR("%s: Failed to load flash helper algorithm", + cc26xx_bank->family_name); + target_free_working_area(target, cc26xx_bank->working_area); + return retval; + } + + /* Initialize the ARMv7 specific info to run the algorithm */ + cc26xx_bank->armv7m_info.common_magic = ARMV7M_COMMON_MAGIC; + cc26xx_bank->armv7m_info.core_mode = ARM_MODE_THREAD; + + /* Begin executing the flash helper algorithm */ + retval = target_start_algorithm(target, 0, NULL, 0, NULL, + CC26XX_ALGO_BASE_ADDRESS, 0, &cc26xx_bank->armv7m_info); + if (ERROR_OK != retval) { + LOG_ERROR("%s: Failed to start flash helper algorithm", + cc26xx_bank->family_name); + target_free_working_area(target, cc26xx_bank->working_area); + return retval; + } + + /* + * At this point, the algorithm is running on the target and + * ready to receive commands and data to flash the target + */ + + return retval; +} + +static int cc26xx_quit(struct flash_bank *bank) +{ + struct target *target = bank->target; + struct cc26xx_bank *cc26xx_bank = bank->driver_priv; + + int retval; + + /* Regardless of the algo's status, attempt to halt the target */ + (void)target_halt(target); + + /* Now confirm target halted and clean up from flash helper algorithm */ + retval = target_wait_algorithm(target, 0, NULL, 0, NULL, 0, FLASH_TIMEOUT, + &cc26xx_bank->armv7m_info); + + target_free_working_area(target, cc26xx_bank->working_area); + cc26xx_bank->working_area = NULL; + + return retval; +} + +static int cc26xx_mass_erase(struct flash_bank *bank) +{ + struct target *target = bank->target; + struct cc26xx_bank *cc26xx_bank = bank->driver_priv; + struct cc26xx_algo_params algo_params; + + int retval; + + if (TARGET_HALTED != target->state) { + LOG_ERROR("Target not halted"); + return ERROR_TARGET_NOT_HALTED; + } + + retval = cc26xx_init(bank); + if (ERROR_OK != retval) + return retval; + + /* Initialize algorithm parameters */ + buf_set_u32(algo_params.address, 0, 32, 0); + buf_set_u32(algo_params.length, 0, 32, 4); + buf_set_u32(algo_params.command, 0, 32, CC26XX_CMD_ERASE_ALL); + buf_set_u32(algo_params.status, 0, 32, CC26XX_BUFFER_FULL); + + /* Issue flash helper algorithm parameters for mass erase */ + retval = target_write_buffer(target, cc26xx_bank->params_addr[0], + sizeof(algo_params), (uint8_t *)&algo_params); + + /* Wait for command to complete */ + if (ERROR_OK == retval) + retval = cc26xx_wait_algo_done(bank, cc26xx_bank->params_addr[0]); + + /* Regardless of errors, try to close down algo */ + (void)cc26xx_quit(bank); + + return retval; +} + +FLASH_BANK_COMMAND_HANDLER(cc26xx_flash_bank_command) +{ + struct cc26xx_bank *cc26xx_bank; + + if (CMD_ARGC < 6) + return ERROR_COMMAND_SYNTAX_ERROR; + + cc26xx_bank = malloc(sizeof(struct cc26xx_bank)); + if (NULL == cc26xx_bank) + return ERROR_FAIL; + + /* Initialize private flash information */ + memset((void *)cc26xx_bank, 0x00, sizeof(struct cc26xx_bank)); + cc26xx_bank->family_name = "cc26xx"; + cc26xx_bank->device_type = CC26XX_NO_TYPE; + cc26xx_bank->sector_length = 0x1000; + + /* Finish initialization of bank */ + bank->driver_priv = cc26xx_bank; + bank->next = NULL; + + return ERROR_OK; +} + +static int cc26xx_erase(struct flash_bank *bank, int first, int last) +{ + struct target *target = bank->target; + struct cc26xx_bank *cc26xx_bank = bank->driver_priv; + struct cc26xx_algo_params algo_params; + + uint32_t address; + uint32_t length; + int retval; + + if (TARGET_HALTED != target->state) { + LOG_ERROR("Target not halted"); + return ERROR_TARGET_NOT_HALTED; + } + + /* Do a mass erase if user requested all sectors of flash */ + if ((first == 0) && (last == (bank->num_sectors - 1))) { + /* Request mass erase of flash */ + return cc26xx_mass_erase(bank); + } + + address = first * cc26xx_bank->sector_length; + length = (last - first + 1) * cc26xx_bank->sector_length; + + retval = cc26xx_init(bank); + if (ERROR_OK != retval) + return retval; + + /* Set up algorithm parameters for erase command */ + buf_set_u32(algo_params.address, 0, 32, address); + buf_set_u32(algo_params.length, 0, 32, length); + buf_set_u32(algo_params.command, 0, 32, CC26XX_CMD_ERASE_SECTORS); + buf_set_u32(algo_params.status, 0, 32, CC26XX_BUFFER_FULL); + + /* Issue flash helper algorithm parameters for erase */ + retval = target_write_buffer(target, cc26xx_bank->params_addr[0], + sizeof(algo_params), (uint8_t *)&algo_params); + + /* If no error, wait for erase to finish */ + if (ERROR_OK == retval) + retval = cc26xx_wait_algo_done(bank, cc26xx_bank->params_addr[0]); + + /* Regardless of errors, try to close down algo */ + (void)cc26xx_quit(bank); + + return retval; +} + +static int cc26xx_protect(struct flash_bank *bank, int set, int first, + int last) +{ + return ERROR_OK; +} + +static int cc26xx_write(struct flash_bank *bank, const uint8_t *buffer, + uint32_t offset, uint32_t count) +{ + struct target *target = bank->target; + struct cc26xx_bank *cc26xx_bank = bank->driver_priv; + struct cc26xx_algo_params algo_params[2]; + uint32_t size = 0; + long long start_ms; + long long elapsed_ms; + uint32_t address; + + uint32_t index; + int retval; + + if (TARGET_HALTED != target->state) { + LOG_ERROR("Target not halted"); + return ERROR_TARGET_NOT_HALTED; + } + + retval = cc26xx_init(bank); + if (ERROR_OK != retval) + return retval; + + /* Initialize algorithm parameters to default values */ + buf_set_u32(algo_params[0].command, 0, 32, CC26XX_CMD_PROGRAM); + buf_set_u32(algo_params[1].command, 0, 32, CC26XX_CMD_PROGRAM); + + /* Write requested data, ping-ponging between two buffers */ + index = 0; + start_ms = timeval_ms(); + address = bank->base + offset; + while (count > 0) { + + if (count > cc26xx_bank->sector_length) + size = cc26xx_bank->sector_length; + else + size = count; + + /* Put next block of data to flash into buffer */ + retval = target_write_buffer(target, cc26xx_bank->buffer_addr[index], + size, buffer); + if (ERROR_OK != retval) { + LOG_ERROR("Unable to write data to target memory"); + break; + } + + /* Update algo parameters for next block */ + buf_set_u32(algo_params[index].address, 0, 32, address); + buf_set_u32(algo_params[index].length, 0, 32, size); + buf_set_u32(algo_params[index].status, 0, 32, CC26XX_BUFFER_FULL); + + /* Issue flash helper algorithm parameters for block write */ + retval = target_write_buffer(target, cc26xx_bank->params_addr[index], + sizeof(algo_params[index]), (uint8_t *)&algo_params[index]); + if (ERROR_OK != retval) + break; + + /* Wait for next ping pong buffer to be ready */ + index ^= 1; + retval = cc26xx_wait_algo_done(bank, cc26xx_bank->params_addr[index]); + if (ERROR_OK != retval) + break; + + count -= size; + buffer += size; + address += size; + + elapsed_ms = timeval_ms() - start_ms; + if (elapsed_ms > 500) + keep_alive(); + } + + /* If no error yet, wait for last buffer to finish */ + if (ERROR_OK == retval) { + index ^= 1; + retval = cc26xx_wait_algo_done(bank, cc26xx_bank->params_addr[index]); + } + + /* Regardless of errors, try to close down algo */ + (void)cc26xx_quit(bank); + + return retval; +} + +static int cc26xx_probe(struct flash_bank *bank) +{ + struct target *target = bank->target; + struct cc26xx_bank *cc26xx_bank = bank->driver_priv; + + uint32_t sector_length; + uint32_t value; + int num_sectors; + int max_sectors; + + int retval; + + retval = target_read_u32(target, FCFG1_ICEPICK_ID, &value); + if (ERROR_OK != retval) + return retval; + cc26xx_bank->icepick_id = value; + + retval = target_read_u32(target, FCFG1_USER_ID, &value); + if (ERROR_OK != retval) + return retval; + cc26xx_bank->user_id = value; + + cc26xx_bank->device_type = cc26xx_device_type(cc26xx_bank->icepick_id, + cc26xx_bank->user_id); + + sector_length = cc26xx_sector_length(cc26xx_bank->icepick_id); + + /* Set up appropriate flash helper algorithm */ + switch (cc26xx_bank->icepick_id & ICEPICK_ID_MASK) { + case CC26X0_ICEPICK_ID: + case CC26X1_ICEPICK_ID: + case CC13X0_ICEPICK_ID: + /* Chameleon family device */ + cc26xx_bank->algo_code = cc26x0_algo; + cc26xx_bank->algo_size = sizeof(cc26x0_algo); + cc26xx_bank->algo_working_size = CC26X0_WORKING_SIZE; + cc26xx_bank->buffer_addr[0] = CC26X0_ALGO_BUFFER_0; + cc26xx_bank->buffer_addr[1] = CC26X0_ALGO_BUFFER_1; + cc26xx_bank->params_addr[0] = CC26X0_ALGO_PARAMS_0; + cc26xx_bank->params_addr[1] = CC26X0_ALGO_PARAMS_1; + max_sectors = CC26X0_MAX_SECTORS; + break; + case CC13X2_CC26X2_ICEPICK_ID: + default: + /* Agama family device */ + cc26xx_bank->algo_code = cc26x2_algo; + cc26xx_bank->algo_size = sizeof(cc26x2_algo); + cc26xx_bank->algo_working_size = CC26X2_WORKING_SIZE; + cc26xx_bank->buffer_addr[0] = CC26X2_ALGO_BUFFER_0; + cc26xx_bank->buffer_addr[1] = CC26X2_ALGO_BUFFER_1; + cc26xx_bank->params_addr[0] = CC26X2_ALGO_PARAMS_0; + cc26xx_bank->params_addr[1] = CC26X2_ALGO_PARAMS_1; + max_sectors = CC26X2_MAX_SECTORS; + break; + } + + retval = target_read_u32(target, CC26XX_FLASH_SIZE_INFO, &value); + if (ERROR_OK != retval) + return retval; + num_sectors = value & 0xff; + if (num_sectors > max_sectors) + num_sectors = max_sectors; + + bank->sectors = malloc(sizeof(struct flash_sector) * num_sectors); + if (NULL == bank->sectors) + return ERROR_FAIL; + + bank->base = CC26XX_FLASH_BASE_ADDR; + bank->num_sectors = num_sectors; + bank->size = num_sectors * sector_length; + bank->write_start_alignment = 0; + bank->write_end_alignment = 0; + cc26xx_bank->sector_length = sector_length; + + for (int i = 0; i < num_sectors; i++) { + bank->sectors[i].offset = i * sector_length; + bank->sectors[i].size = sector_length; + bank->sectors[i].is_erased = -1; + bank->sectors[i].is_protected = 0; + } + + /* We've successfully determined the stats on the flash bank */ + cc26xx_bank->probed = true; + + /* If we fall through to here, then all went well */ + + return ERROR_OK; +} + +static int cc26xx_auto_probe(struct flash_bank *bank) +{ + struct cc26xx_bank *cc26xx_bank = bank->driver_priv; + + int retval = ERROR_OK; + + if (bank->bank_number != 0) { + /* Invalid bank number somehow */ + return ERROR_FAIL; + } + + if (!cc26xx_bank->probed) + retval = cc26xx_probe(bank); + + return retval; +} + +static int cc26xx_protect_check(struct flash_bank *bank) +{ + return ERROR_OK; +} + +static int cc26xx_info(struct flash_bank *bank, char *buf, int buf_size) +{ + struct cc26xx_bank *cc26xx_bank = bank->driver_priv; + int printed = 0; + const char *device; + + switch (cc26xx_bank->device_type) { + case CC26X0_TYPE: + device = "CC26x0"; + break; + case CC26X1_TYPE: + device = "CC26x1"; + break; + case CC13X0_TYPE: + device = "CC13x0"; + break; + case CC13X2_TYPE: + device = "CC13x2"; + break; + case CC26X2_TYPE: + device = "CC26x2"; + break; + case CC26XX_NO_TYPE: + default: + device = "Unrecognized"; + break; + } + + printed = snprintf(buf, buf_size, + "%s device: ICEPick ID 0x%08x, USER ID 0x%08x\n", + device, cc26xx_bank->icepick_id, cc26xx_bank->user_id); + + if (printed >= buf_size) + return ERROR_BUF_TOO_SMALL; + + return ERROR_OK; +} + +struct flash_driver cc26xx_flash = { + .name = "cc26xx", + .flash_bank_command = cc26xx_flash_bank_command, + .erase = cc26xx_erase, + .protect = cc26xx_protect, + .write = cc26xx_write, + .read = default_flash_read, + .probe = cc26xx_probe, + .auto_probe = cc26xx_auto_probe, + .erase_check = default_flash_blank_check, + .protect_check = cc26xx_protect_check, + .info = cc26xx_info, + .free_driver_priv = default_flash_free_driver_priv, +}; diff --git a/src/flash/nor/cc26xx.h b/src/flash/nor/cc26xx.h new file mode 100644 index 000000000..51a09f19b --- /dev/null +++ b/src/flash/nor/cc26xx.h @@ -0,0 +1,101 @@ +/*************************************************************************** + * Copyright (C) 2017 by Texas Instruments, Inc. * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program. If not, see . * + ***************************************************************************/ + +#ifndef OPENOCD_FLASH_NOR_CC26XX_H +#define OPENOCD_FLASH_NOR_CC26XX_H + +/* Addresses of FCFG1 registers to access ICEPick Device ID and User ID */ +#define FCFG1_ICEPICK_ID 0x50001318 +#define FCFG1_USER_ID 0x50001294 + +/* ICEPick device ID mask and values */ +#define ICEPICK_ID_MASK 0x0fffffff +#define ICEPICK_REV_MASK 0xf0000000 +#define CC26X0_ICEPICK_ID 0x0b99a02f +#define CC26X1_ICEPICK_ID 0x0b9bd02f +#define CC13X0_ICEPICK_ID 0x0b9be02f +#define CC13X2_CC26X2_ICEPICK_ID 0x0bb4102f + +/* User ID mask for Agama CC13x2 vs CC26x2 */ +#define USER_ID_CC13_MASK 0x00800000 + +/* Common CC26xx/CC13xx flash and memory parameters */ +#define CC26XX_FLASH_BASE_ADDR 0x00000000 +#define CC26XX_FLASH_SIZE_INFO 0x4003002c +#define CC26XX_SRAM_SIZE_INFO 0x40082250 +#define CC26XX_ALGO_BASE_ADDRESS 0x20000000 + +/* Chameleon CC26x0/CC13x0 specific parameters */ +#define CC26X0_MAX_SECTORS 32 +#define CC26X0_SECTOR_LENGTH 0x1000 +#define CC26X0_ALGO_BUFFER_0 0x20001c00 +#define CC26X0_ALGO_BUFFER_1 0x20002c00 +#define CC26X0_ALGO_PARAMS_0 0x20001bd8 +#define CC26X0_ALGO_PARAMS_1 0x20001bec +#define CC26X0_WORKING_SIZE (CC26X0_ALGO_BUFFER_1 + CC26X0_SECTOR_LENGTH - \ + CC26XX_ALGO_BASE_ADDRESS) + +/* Agama CC26x2/CC13x2 specific parameters */ +#define CC26X2_MAX_SECTORS 128 +#define CC26X2_SECTOR_LENGTH 0x2000 +#define CC26X2_ALGO_BUFFER_0 0x20002000 +#define CC26X2_ALGO_BUFFER_1 0x20004000 +#define CC26X2_ALGO_PARAMS_0 0x20001fd8 +#define CC26X2_ALGO_PARAMS_1 0x20001fec +#define CC26X2_WORKING_SIZE (CC26X2_ALGO_BUFFER_1 + CC26X2_SECTOR_LENGTH - \ + CC26XX_ALGO_BASE_ADDRESS) + +/* CC26xx flash helper algorithm buffer flags */ +#define CC26XX_BUFFER_EMPTY 0x00000000 +#define CC26XX_BUFFER_FULL 0xffffffff + +/* CC26XX flash helper algorithm commands */ +#define CC26XX_CMD_NO_ACTION 0 +#define CC26XX_CMD_ERASE_ALL 1 +#define CC26XX_CMD_PROGRAM 2 +#define CC26XX_CMD_ERASE_AND_PROGRAM 3 +#define CC26XX_CMD_ERASE_AND_PROGRAM_WITH_RETAIN 4 +#define CC26XX_CMD_ERASE_SECTORS 5 + +/* CC26xx and CC13xx device types */ +#define CC26XX_NO_TYPE 0 /* Device type not determined yet */ +#define CC26X0_TYPE 1 /* CC26x0 Chameleon device */ +#define CC26X1_TYPE 2 /* CC26x1 Chameleon device */ +#define CC26X2_TYPE 3 /* CC26x2 Agama device */ +#define CC13X0_TYPE 4 /* CC13x0 Chameleon device */ +#define CC13X2_TYPE 5 /* CC13x2 Agama device */ + +/* Flash helper algorithm parameter block struct */ +#define CC26XX_STATUS_OFFSET 0x0c +struct cc26xx_algo_params { + uint8_t address[4]; + uint8_t length[4]; + uint8_t command[4]; + uint8_t status[4]; +}; + +/* Flash helper algorithm for CC26x0 Chameleon targets */ +const uint8_t cc26x0_algo[] = { +#include "../../../contrib/loaders/flash/cc26xx/cc26x0_algo.inc" +}; + +/* Flash helper algorithm for CC26x2 Agama targets */ +const uint8_t cc26x2_algo[] = { +#include "../../../contrib/loaders/flash/cc26xx/cc26x2_algo.inc" +}; + +#endif /* OPENOCD_FLASH_NOR_CC26XX_H */ diff --git a/src/flash/nor/drivers.c b/src/flash/nor/drivers.c index 6e1703b41..4efbdf768 100644 --- a/src/flash/nor/drivers.c +++ b/src/flash/nor/drivers.c @@ -33,6 +33,7 @@ extern struct flash_driver atsamv_flash; extern struct flash_driver avr_flash; extern struct flash_driver bluenrgx_flash; extern struct flash_driver cc3220sf_flash; +extern struct flash_driver cc26xx_flash; extern struct flash_driver cfi_flash; extern struct flash_driver dsp5680xx_flash; extern struct flash_driver efm32_flash; @@ -95,6 +96,7 @@ static struct flash_driver *flash_drivers[] = { &avr_flash, &bluenrgx_flash, &cc3220sf_flash, + &cc26xx_flash, &cfi_flash, &dsp5680xx_flash, &efm32_flash, diff --git a/tcl/board/ti_cc13x0_launchpad.cfg b/tcl/board/ti_cc13x0_launchpad.cfg new file mode 100644 index 000000000..9e1c1ea37 --- /dev/null +++ b/tcl/board/ti_cc13x0_launchpad.cfg @@ -0,0 +1,7 @@ +# +# TI CC13x0 LaunchPad Evaluation Kit +# +source [find interface/xds110.cfg] +transport select jtag +adapter_khz 2500 +source [find target/ti_cc13x0.cfg] diff --git a/tcl/board/ti_cc13x2_launchpad.cfg b/tcl/board/ti_cc13x2_launchpad.cfg new file mode 100644 index 000000000..18c5ce51c --- /dev/null +++ b/tcl/board/ti_cc13x2_launchpad.cfg @@ -0,0 +1,7 @@ +# +# TI CC13x2 LaunchPad Evaluation Kit +# +source [find interface/xds110.cfg] +adapter_khz 2500 +transport select jtag +source [find target/ti_cc13x2.cfg] diff --git a/tcl/board/ti_cc26x0_launchpad.cfg b/tcl/board/ti_cc26x0_launchpad.cfg new file mode 100644 index 000000000..3613a47f7 --- /dev/null +++ b/tcl/board/ti_cc26x0_launchpad.cfg @@ -0,0 +1,7 @@ +# +# TI CC26x0 LaunchPad Evaluation Kit +# +source [find interface/xds110.cfg] +adapter_khz 2500 +transport select jtag +source [find target/ti_cc26x0.cfg] diff --git a/tcl/board/ti_cc26x2_launchpad.cfg b/tcl/board/ti_cc26x2_launchpad.cfg new file mode 100644 index 000000000..2f2b34b4b --- /dev/null +++ b/tcl/board/ti_cc26x2_launchpad.cfg @@ -0,0 +1,7 @@ +# +# TI CC26x2 LaunchPad Evaluation Kit +# +source [find interface/xds110.cfg] +adapter_khz 2500 +transport select jtag +source [find target/ti_cc26x2.cfg] diff --git a/tcl/target/ti_cc13x0.cfg b/tcl/target/ti_cc13x0.cfg new file mode 100644 index 000000000..6ea9bd807 --- /dev/null +++ b/tcl/target/ti_cc13x0.cfg @@ -0,0 +1,11 @@ +# +# Texas Instruments CC13x0 - ARM Cortex-M3 +# +# http://www.ti.com +# + +set CHIPNAME cc13x0 +set JRC_TAPID 0x0B9BE02F +set WORKAREASIZE 0x4000 + +source [find target/ti_cc26x0.cfg] diff --git a/tcl/target/ti_cc13x2.cfg b/tcl/target/ti_cc13x2.cfg new file mode 100644 index 000000000..280eef45f --- /dev/null +++ b/tcl/target/ti_cc13x2.cfg @@ -0,0 +1,11 @@ +# +# Texas Instruments CC13x2 - ARM Cortex-M4 +# +# http://www.ti.com +# + +set CHIPNAME cc13x2 +set JRC_TAPID 0x0BB4102F +set WORKAREASIZE 0x7000 + +source [find target/ti_cc26x0.cfg] diff --git a/tcl/target/cc26xx.cfg b/tcl/target/ti_cc26x0.cfg old mode 100755 new mode 100644 similarity index 57% rename from tcl/target/cc26xx.cfg rename to tcl/target/ti_cc26x0.cfg index c3ac8470a..7efecb666 --- a/tcl/target/cc26xx.cfg +++ b/tcl/target/ti_cc26x0.cfg @@ -1,23 +1,25 @@ -# Config for Texas Instruments low power SoC CC26xx family - -adapter_khz 100 +# +# Texas Instruments CC26x0 - ARM Cortex-M3 +# +# http://www.ti.com +# source [find target/icepick.cfg] source [find target/ti-cjtag.cfg] if { [info exists CHIPNAME] } { - set _CHIPNAME $CHIPNAME + set _CHIPNAME $CHIPNAME } else { - set _CHIPNAME cc26xx + set _CHIPNAME cc26x0 } # # Main DAP # if { [info exists DAP_TAPID] } { - set _DAP_TAPID $DAP_TAPID + set _DAP_TAPID $DAP_TAPID } else { - set _DAP_TAPID 0x4BA00477 + set _DAP_TAPID 0x4BA00477 } jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_DAP_TAPID -disable jtag configure $_CHIPNAME.cpu -event tap-enable "icepick_c_tapenable $_CHIPNAME.jrc 0" @@ -26,19 +28,29 @@ jtag configure $_CHIPNAME.cpu -event tap-enable "icepick_c_tapenable $_CHIPNAME. # ICEpick-C (JTAG route controller) # if { [info exists JRC_TAPID] } { - set _JRC_TAPID $JRC_TAPID + set _JRC_TAPID $JRC_TAPID } else { - set _JRC_TAPID 0x1B99A02F + set _JRC_TAPID 0x0B99A02F } jtag newtap $_CHIPNAME jrc -irlen 6 -ircapture 0x1 -irmask 0x3f -expected-id $_JRC_TAPID -ignore-version -# A start sequence is needed to change from cJTAG (Compact JTAG) to -# 4-pin JTAG before talking via JTAG commands jtag configure $_CHIPNAME.jrc -event setup "jtag tapenable $_CHIPNAME.cpu" +# A start sequence is needed to change from 2-pin cJTAG to 4-pin JTAG jtag configure $_CHIPNAME.jrc -event post-reset "ti_cjtag_to_4pin_jtag $_CHIPNAME.jrc" -# -# Cortex-M3 target -# set _TARGETNAME $_CHIPNAME.cpu dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu target create $_TARGETNAME cortex_m -dap $_CHIPNAME.dap + +if { [info exists WORKAREASIZE] } { + set _WORKAREASIZE $WORKAREASIZE +} else { + set _WORKAREASIZE 0x4000 +} + +$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0 + +set _FLASHNAME $_CHIPNAME.flash +flash bank $_FLASHNAME cc26xx 0 0 0 0 $_TARGETNAME + +reset_config srst_only +adapter_nsrst_delay 100 diff --git a/tcl/target/ti_cc26x2.cfg b/tcl/target/ti_cc26x2.cfg new file mode 100644 index 000000000..ecee3fab5 --- /dev/null +++ b/tcl/target/ti_cc26x2.cfg @@ -0,0 +1,11 @@ +# +# Texas Instruments CC26x2 - ARM Cortex-M4 +# +# http://www.ti.com +# + +set CHIPNAME cc26x2 +set JRC_TAPID 0x0BB4102F +set WORKAREASIZE 0x7000 + +source [find target/ti_cc26x0.cfg]