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cortex_a8: -Wshadow warning fixes 

Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
This commit is contained in:
Øyvind Harboe 2010-06-15 23:23:16 +02:00
parent 4bd415d01b
commit 78b7a571e9
1 changed files with 9 additions and 9 deletions
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18
src/target/cortex_a8.c
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@ -473,7 +473,7 @@ static int cortex_a8_instr_read_data_r0(struct arm_dpm *dpm,
return cortex_a8_read_dcc(a8, data, &dscr); return cortex_a8_read_dcc(a8, data, &dscr);
} }
static int cortex_a8_bpwp_enable(struct arm_dpm *dpm, unsigned index, static int cortex_a8_bpwp_enable(struct arm_dpm *dpm, unsigned index_t,
uint32_t addr, uint32_t control) uint32_t addr, uint32_t control)
{ {
struct cortex_a8_common *a8 = dpm_to_a8(dpm); struct cortex_a8_common *a8 = dpm_to_a8(dpm);
@ -481,7 +481,7 @@ static int cortex_a8_bpwp_enable(struct arm_dpm *dpm, unsigned index,
uint32_t cr = a8->armv7a_common.debug_base; uint32_t cr = a8->armv7a_common.debug_base;
int retval; int retval;
switch (index) { switch (index_t) {
case 0 ... 15: /* breakpoints */ case 0 ... 15: /* breakpoints */
vr += CPUDBG_BVR_BASE; vr += CPUDBG_BVR_BASE;
cr += CPUDBG_BCR_BASE; cr += CPUDBG_BCR_BASE;
@ -489,13 +489,13 @@ static int cortex_a8_bpwp_enable(struct arm_dpm *dpm, unsigned index,
case 16 ... 31: /* watchpoints */ case 16 ... 31: /* watchpoints */
vr += CPUDBG_WVR_BASE; vr += CPUDBG_WVR_BASE;
cr += CPUDBG_WCR_BASE; cr += CPUDBG_WCR_BASE;
index -= 16; index_t -= 16;
break; break;
default: default:
return ERROR_FAIL; return ERROR_FAIL;
} }
vr += 4 * index; vr += 4 * index_t;
cr += 4 * index; cr += 4 * index_t;
LOG_DEBUG("A8: bpwp enable, vr %08x cr %08x", LOG_DEBUG("A8: bpwp enable, vr %08x cr %08x",
(unsigned) vr, (unsigned) cr); (unsigned) vr, (unsigned) cr);
@ -509,23 +509,23 @@ static int cortex_a8_bpwp_enable(struct arm_dpm *dpm, unsigned index,
return retval; return retval;
} }
static int cortex_a8_bpwp_disable(struct arm_dpm *dpm, unsigned index) static int cortex_a8_bpwp_disable(struct arm_dpm *dpm, unsigned index_t)
{ {
struct cortex_a8_common *a8 = dpm_to_a8(dpm); struct cortex_a8_common *a8 = dpm_to_a8(dpm);
uint32_t cr; uint32_t cr;
switch (index) { switch (index_t) {
case 0 ... 15: case 0 ... 15:
cr = a8->armv7a_common.debug_base + CPUDBG_BCR_BASE; cr = a8->armv7a_common.debug_base + CPUDBG_BCR_BASE;
break; break;
case 16 ... 31: case 16 ... 31:
cr = a8->armv7a_common.debug_base + CPUDBG_WCR_BASE; cr = a8->armv7a_common.debug_base + CPUDBG_WCR_BASE;
index -= 16; index_t -= 16;
break; break;
default: default:
return ERROR_FAIL; return ERROR_FAIL;
} }
cr += 4 * index; cr += 4 * index_t;
LOG_DEBUG("A8: bpwp disable, cr %08x", (unsigned) cr); LOG_DEBUG("A8: bpwp disable, cr %08x", (unsigned) cr);