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Merge pull request #992 from en-sc/en-sc/remove-hart-count 

target/riscv: remove `riscv_hart_count()`
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Jan Matyas 2024-01-18 09:12:40 +01:00 committed by GitHub
parent 80f219ae89 ecb983a464
commit 78a719fad3
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GPG Key ID: B5690EEEBB952194
3 changed files with 1 additions and 26 deletions
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11
src/target/riscv/riscv-013.c
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@ -2163,8 +2163,7 @@ static int examine(struct target *target)
/* Some regression suites rely on seeing 'Examined RISC-V core' to know /* Some regression suites rely on seeing 'Examined RISC-V core' to know
* when they can connect with gdb/telnet. * when they can connect with gdb/telnet.
* We will need to update those suites if we want to change that text. */ * We will need to update those suites if we want to change that text. */
LOG_TARGET_INFO(target, "Examined RISC-V core; found %d harts", LOG_TARGET_INFO(target, "Examined RISC-V core");
riscv_count_harts(target));
LOG_TARGET_INFO(target, " XLEN=%d, misa=0x%" PRIx64, r->xlen, r->misa); LOG_TARGET_INFO(target, " XLEN=%d, misa=0x%" PRIx64, r->xlen, r->misa);
return ERROR_OK; return ERROR_OK;
} }
@ -2216,13 +2215,6 @@ static int riscv013_authdata_write(struct target *target, uint32_t value, unsign
return ERROR_OK; return ERROR_OK;
} }
static int riscv013_hart_count(struct target *target)
{
dm013_info_t *dm = get_dm(target);
assert(dm);
return dm->hart_count;
}
/* Try to find out the widest memory access size depending on the selected memory access methods. */ /* Try to find out the widest memory access size depending on the selected memory access methods. */
static unsigned riscv013_data_bits(struct target *target) static unsigned riscv013_data_bits(struct target *target)
{ {
@ -2784,7 +2776,6 @@ static int init_target(struct command_context *cmd_ctx,
generic_info->dmi_write = &dmi_write; generic_info->dmi_write = &dmi_write;
generic_info->get_dmi_address = &riscv013_get_dmi_address; generic_info->get_dmi_address = &riscv013_get_dmi_address;
generic_info->read_memory = read_memory; generic_info->read_memory = read_memory;
generic_info->hart_count = &riscv013_hart_count;
generic_info->data_bits = &riscv013_data_bits; generic_info->data_bits = &riscv013_data_bits;
generic_info->print_info = &riscv013_print_info; generic_info->print_info = &riscv013_print_info;

10
src/target/riscv/riscv.c
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@ -5065,16 +5065,6 @@ static void riscv_invalidate_register_cache(struct target *target)
} }
unsigned int riscv_count_harts(struct target *target)
{
if (!target)
return 1;
RISCV_INFO(r);
if (!r || !r->hart_count)
return 1;
return r->hart_count(target);
}
/** /**
* If write is true: * If write is true:
* return true iff we are guaranteed that the register will contain exactly * return true iff we are guaranteed that the register will contain exactly

6
src/target/riscv/riscv.h
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@ -256,8 +256,6 @@ struct riscv_info {
int (*read_memory)(struct target *target, target_addr_t address, int (*read_memory)(struct target *target, target_addr_t address,
uint32_t size, uint32_t count, uint8_t *buffer, uint32_t increment); uint32_t size, uint32_t count, uint8_t *buffer, uint32_t increment);
/* How many harts are attached to the DM that this target is attached to? */
int (*hart_count)(struct target *target);
unsigned (*data_bits)(struct target *target); unsigned (*data_bits)(struct target *target);
COMMAND_HELPER((*print_info), struct target *target); COMMAND_HELPER((*print_info), struct target *target);
@ -400,10 +398,6 @@ unsigned riscv_xlen(const struct target *target);
/*** Support functions for the RISC-V 'RTOS', which provides multihart support /*** Support functions for the RISC-V 'RTOS', which provides multihart support
* without requiring multiple targets. */ * without requiring multiple targets. */
/* Lists the number of harts in the system, which are assumed to be
* consecutive and start with mhartid=0. */
unsigned int riscv_count_harts(struct target *target);
/** /**
* Set the register value. For cacheable registers, only the cache is updated * Set the register value. For cacheable registers, only the cache is updated
* (write-back mode). * (write-back mode).