target/riscv: avoid updating `target` if `ackhavereset` fails
`target`'s `state` and `debug_reason` should not be updated in `deassert_reset` if sending reset acknowledgment fails. Change-Id: I86136fe829e7a7c6b69f718f0cf32322e40341b0 Signed-off-by: Evgeniy Naydanov <evgeniy.naydanov@syntacore.com>
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@ -2902,6 +2902,15 @@ static int deassert_reset(struct target *target)
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riscv_scan_set_delay(&info->learned_delays, RISCV_DELAY_BASE,
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riscv_scan_set_delay(&info->learned_delays, RISCV_DELAY_BASE,
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orig_base_delay);
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orig_base_delay);
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/* Ack reset and clear DM_DMCONTROL_HALTREQ if previously set */
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control = 0;
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control = set_field(control, DM_DMCONTROL_DMACTIVE, 1);
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control = set_field(control, DM_DMCONTROL_ACKHAVERESET, 1);
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control = set_dmcontrol_hartsel(control, info->index);
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result = dm_write(target, DM_DMCONTROL, control);
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if (result != ERROR_OK)
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return result;
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if (target->reset_halt) {
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if (target->reset_halt) {
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target->state = TARGET_HALTED;
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target->state = TARGET_HALTED;
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target->debug_reason = DBG_REASON_DBGRQ;
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target->debug_reason = DBG_REASON_DBGRQ;
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@ -2910,13 +2919,7 @@ static int deassert_reset(struct target *target)
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target->debug_reason = DBG_REASON_NOTHALTED;
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target->debug_reason = DBG_REASON_NOTHALTED;
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}
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}
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info->dcsr_ebreak_is_set = dcsr_ebreak_config_equals_reset_value(target);
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info->dcsr_ebreak_is_set = dcsr_ebreak_config_equals_reset_value(target);
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return ERROR_OK;
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/* Ack reset and clear DM_DMCONTROL_HALTREQ if previously set */
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control = 0;
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control = set_field(control, DM_DMCONTROL_DMACTIVE, 1);
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control = set_field(control, DM_DMCONTROL_ACKHAVERESET, 1);
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control = set_dmcontrol_hartsel(control, info->index);
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return dm_write(target, DM_DMCONTROL, control);
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}
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}
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static int execute_fence(struct target *target)
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static int execute_fence(struct target *target)
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