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cortex_m: handle armv8m cores without security extension 

Cores armv8m, e.g. Cortex-M33, can be instantiated without the
optional Security Extension.
In this case, the secure registers are not present and when GDB
try accessing them it triggers a set of errors.

For armv8m cores without security extension, don't provide to GDB
the description of the secure registers.

Change-Id: I254478a4cf883e85b786df3f62c726b2f40d88d9
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reported-by: Torbjörn SVENSSON <torbjorn.svensson@foss.st.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/7402
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
This commit is contained in:
Antonio Borneo 2022-12-14 15:54:53 +01:00
parent c913e4d5a6
commit 77c281d2df
2 changed files with 20 additions and 1 deletions
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18
src/target/cortex_m.c
View File

@ -2270,6 +2270,22 @@ static void cortex_m_dwt_free(struct target *target)
cm->dwt_cache = NULL;
}
static bool cortex_m_has_tz(struct target *target)
{
struct armv7m_common *armv7m = target_to_armv7m(target);
uint32_t dauthstatus;
if (armv7m->arm.arch != ARM_ARCH_V8M)
return false;
int retval = target_read_u32(target, DAUTHSTATUS, &dauthstatus);
if (retval != ERROR_OK) {
LOG_WARNING("Error reading DAUTHSTATUS register");
return false;
}
return (dauthstatus & DAUTHSTATUS_SID_MASK) != 0;
}
#define MVFR0 0xe000ef40
#define MVFR1 0xe000ef44
@ -2398,7 +2414,7 @@ int cortex_m_examine(struct target *target)
for (size_t idx = ARMV7M_FPU_FIRST_REG; idx <= ARMV7M_FPU_LAST_REG; idx++)
armv7m->arm.core_cache->reg_list[idx].exist = false;
if (armv7m->arm.arch != ARM_ARCH_V8M)
if (!cortex_m_has_tz(target))
for (size_t idx = ARMV8M_FIRST_REG; idx <= ARMV8M_LAST_REG; idx++)
armv7m->arm.core_cache->reg_list[idx].exist = false;

3
src/target/cortex_m.h
View File

@ -68,6 +68,9 @@ struct cortex_m_part_info {
#define DCB_DEMCR 0xE000EDFC
#define DCB_DSCSR 0xE000EE08
#define DAUTHSTATUS 0xE000EFB8
#define DAUTHSTATUS_SID_MASK 0x00000030
#define DCRSR_WNR BIT(16)
#define DWT_CTRL 0xE0001000