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quark_x10xx: cleanup of LOG format specifiers 

Fix for LOG format specifiers, this is a superset of those
exposed by the arm-none-eabi build.

Add 0x prefix for all values printed in hex.

Add LOG messages for error cases when enabling or disabling
paging.

Change-Id: I070c556e0ad31204231a2b572e7b93af22a9bc61
Signed-off-by: Ivan De Cesaris <ivan.de.cesaris@intel.com>
Reviewed-on: http://openocd.zylin.com/2149
Tested-by: jenkins
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
This commit is contained in:
Ivan De Cesaris 2014-05-21 15:20:08 +02:00 committed by Andreas Fritiofson
parent 970a12aef4
commit 74889cf468
4 changed files with 129 additions and 102 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

59
src/target/lakemont.c
View File

@ -342,7 +342,7 @@ static int lakemont_get_core_reg(struct reg *reg)
struct target *t = lakemont_reg->target;
if (check_not_halted(t))
return ERROR_TARGET_NOT_HALTED;
LOG_DEBUG("reg=%s, value=%08" PRIx32, reg->name,
LOG_DEBUG("reg=%s, value=0x%08" PRIx32, reg->name,
buf_get_u32(reg->value, 0, 32));
return retval;
}
@ -352,7 +352,7 @@ static int lakemont_set_core_reg(struct reg *reg, uint8_t *buf)
struct lakemont_core_reg *lakemont_reg = reg->arch_info;
struct target *t = lakemont_reg->target;
uint32_t value = buf_get_u32(buf, 0, 32);
LOG_DEBUG("reg=%s, newval=%08" PRIx32, reg->name, value);
LOG_DEBUG("reg=%s, newval=0x%08" PRIx32, reg->name, value);
if (check_not_halted(t))
return ERROR_TARGET_NOT_HALTED;
buf_set_u32(reg->value, 0, 32, value);
@ -444,7 +444,7 @@ static int enter_probemode(struct target *t)
{
uint32_t tapstatus = 0;
tapstatus = get_tapstatus(t);
LOG_DEBUG("TS before PM enter = %08" PRIx32, tapstatus);
LOG_DEBUG("TS before PM enter = 0x%08" PRIx32, tapstatus);
if (tapstatus & TS_PM_BIT) {
LOG_DEBUG("core already in probemode");
return ERROR_OK;
@ -456,11 +456,11 @@ static int enter_probemode(struct target *t)
if (drscan(t, scan.out, scan.in, 1) != ERROR_OK)
return ERROR_FAIL;
tapstatus = get_tapstatus(t);
LOG_DEBUG("TS after PM enter = %08" PRIx32, tapstatus);
LOG_DEBUG("TS after PM enter = 0x%08" PRIx32, tapstatus);
if ((tapstatus & TS_PM_BIT) && (!(tapstatus & TS_EN_PM_BIT)))
return ERROR_OK;
else {
LOG_ERROR("%s PM enter error, tapstatus = %08" PRIx32
LOG_ERROR("%s PM enter error, tapstatus = 0x%08" PRIx32
, __func__, tapstatus);
return ERROR_FAIL;
}
@ -469,7 +469,7 @@ static int enter_probemode(struct target *t)
static int exit_probemode(struct target *t)
{
uint32_t tapstatus = get_tapstatus(t);
LOG_DEBUG("TS before PM exit = %08" PRIx32, tapstatus);
LOG_DEBUG("TS before PM exit = 0x%08" PRIx32, tapstatus);
if (!(tapstatus & TS_PM_BIT)) {
LOG_USER("core not in PM");
@ -490,16 +490,16 @@ static int halt_prep(struct target *t)
struct x86_32_common *x86_32 = target_to_x86_32(t);
if (write_hw_reg(t, DSB, PM_DSB, 0) != ERROR_OK)
return ERROR_FAIL;
LOG_DEBUG("write %s %08" PRIx32, regs[DSB].name, PM_DSB);
LOG_DEBUG("write %s 0x%08" PRIx32, regs[DSB].name, PM_DSB);
if (write_hw_reg(t, DSL, PM_DSL, 0) != ERROR_OK)
return ERROR_FAIL;
LOG_DEBUG("write %s %08" PRIx32, regs[DSL].name, PM_DSL);
LOG_DEBUG("write %s 0x%08" PRIx32, regs[DSL].name, PM_DSL);
if (write_hw_reg(t, DSAR, PM_DSAR, 0) != ERROR_OK)
return ERROR_FAIL;
LOG_DEBUG("write DSAR %08" PRIx32, PM_DSAR);
LOG_DEBUG("write DSAR 0x%08" PRIx32, PM_DSAR);
if (write_hw_reg(t, DR7, PM_DR7, 0) != ERROR_OK)
return ERROR_FAIL;
LOG_DEBUG("write DR7 %08" PRIx32, PM_DR7);
LOG_DEBUG("write DR7 0x%08" PRIx32, PM_DR7);
uint32_t eflags = buf_get_u32(x86_32->cache->reg_list[EFLAGS].value, 0, 32);
uint32_t csar = buf_get_u32(x86_32->cache->reg_list[CSAR].value, 0, 32);
@ -507,7 +507,7 @@ static int halt_prep(struct target *t)
uint32_t cr0 = buf_get_u32(x86_32->cache->reg_list[CR0].value, 0, 32);
/* clear VM86 and IF bits if they are set */
LOG_DEBUG("EFLAGS = %08" PRIx32 ", VM86 = %d, IF = %d", eflags,
LOG_DEBUG("EFLAGS = 0x%08" PRIx32 ", VM86 = %d, IF = %d", eflags,
eflags & EFLAGS_VM86 ? 1 : 0,
eflags & EFLAGS_IF ? 1 : 0);
if (eflags & EFLAGS_VM86
@ -515,7 +515,7 @@ static int halt_prep(struct target *t)
x86_32->pm_regs[I(EFLAGS)] = eflags & ~(EFLAGS_VM86 | EFLAGS_IF);
if (write_hw_reg(t, EFLAGS, x86_32->pm_regs[I(EFLAGS)], 0) != ERROR_OK)
return ERROR_FAIL;
LOG_DEBUG("EFLAGS now = %08" PRIx32 ", VM86 = %d, IF = %d",
LOG_DEBUG("EFLAGS now = 0x%08" PRIx32 ", VM86 = %d, IF = %d",
x86_32->pm_regs[I(EFLAGS)],
x86_32->pm_regs[I(EFLAGS)] & EFLAGS_VM86 ? 1 : 0,
x86_32->pm_regs[I(EFLAGS)] & EFLAGS_IF ? 1 : 0);
@ -526,23 +526,23 @@ static int halt_prep(struct target *t)
x86_32->pm_regs[I(CSAR)] = csar & ~CSAR_DPL;
if (write_hw_reg(t, CSAR, x86_32->pm_regs[I(CSAR)], 0) != ERROR_OK)
return ERROR_FAIL;
LOG_DEBUG("write CSAR_CPL to 0 %08" PRIx32, x86_32->pm_regs[I(CSAR)]);
LOG_DEBUG("write CSAR_CPL to 0 0x%08" PRIx32, x86_32->pm_regs[I(CSAR)]);
}
if (ssar & SSAR_DPL) {
x86_32->pm_regs[I(SSAR)] = ssar & ~CSAR_DPL;
if (write_hw_reg(t, SSAR, x86_32->pm_regs[I(SSAR)], 0) != ERROR_OK)
return ERROR_FAIL;
LOG_DEBUG("write SSAR_CPL to 0 %08" PRIx32, x86_32->pm_regs[I(SSAR)]);
LOG_DEBUG("write SSAR_CPL to 0 0x%08" PRIx32, x86_32->pm_regs[I(SSAR)]);
}
/* if cache's are enabled, disable and flush */
if (!(cr0 & CR0_CD)) {
LOG_DEBUG("caching enabled CR0 = %08" PRIx32, cr0);
LOG_DEBUG("caching enabled CR0 = 0x%08" PRIx32, cr0);
if (cr0 & CR0_PG) {
x86_32->pm_regs[I(CR0)] = cr0 & ~CR0_PG;
if (write_hw_reg(t, CR0, x86_32->pm_regs[I(CR0)], 0) != ERROR_OK)
return ERROR_FAIL;
LOG_DEBUG("cleared paging CR0_PG = %08" PRIx32, x86_32->pm_regs[I(CR0)]);
LOG_DEBUG("cleared paging CR0_PG = 0x%08" PRIx32, x86_32->pm_regs[I(CR0)]);
/* submit wbinvd to flush cache */
if (submit_reg_pir(t, WBINVD) != ERROR_OK)
return ERROR_FAIL;
@ -550,7 +550,7 @@ static int halt_prep(struct target *t)
x86_32->pm_regs[I(CR0)] | (CR0_CD | CR0_NW | CR0_PG);
if (write_hw_reg(t, CR0, x86_32->pm_regs[I(CR0)], 0) != ERROR_OK)
return ERROR_FAIL;
LOG_DEBUG("set CD, NW and PG, CR0 = %08" PRIx32, x86_32->pm_regs[I(CR0)]);
LOG_DEBUG("set CD, NW and PG, CR0 = 0x%08" PRIx32, x86_32->pm_regs[I(CR0)]);
}
}
return ERROR_OK;
@ -590,7 +590,8 @@ static int do_resume(struct target *t)
static int read_all_core_hw_regs(struct target *t)
{
int err;
uint32_t regval, i;
uint32_t regval;
unsigned i;
struct x86_32_common *x86_32 = target_to_x86_32(t);
for (i = 0; i < (x86_32->cache->num_regs); i++) {
if (NOT_AVAIL_REG == regs[i].pm_idx)
@ -602,14 +603,14 @@ static int read_all_core_hw_regs(struct target *t)
return err;
}
}
LOG_DEBUG("read_all_core_hw_regs read %d registers ok", i);
LOG_DEBUG("read_all_core_hw_regs read %u registers ok", i);
return ERROR_OK;
}
static int write_all_core_hw_regs(struct target *t)
{
int err;
uint32_t i;
unsigned i;
struct x86_32_common *x86_32 = target_to_x86_32(t);
for (i = 0; i < (x86_32->cache->num_regs); i++) {
if (NOT_AVAIL_REG == regs[i].pm_idx)
@ -621,7 +622,7 @@ static int write_all_core_hw_regs(struct target *t)
return err;
}
}
LOG_DEBUG("write_all_core_hw_regs wrote %d registers ok", i);
LOG_DEBUG("write_all_core_hw_regs wrote %u registers ok", i);
return ERROR_OK;
}
@ -652,7 +653,7 @@ static int read_hw_reg(struct target *t, int reg, uint32_t *regval, uint8_t cach
x86_32->cache->reg_list[reg].valid = 1;
x86_32->cache->reg_list[reg].dirty = 0;
}
LOG_DEBUG("reg=%s, op=0x%016" PRIx64 ", val=%08" PRIx32,
LOG_DEBUG("reg=%s, op=0x%016" PRIx64 ", val=0x%08" PRIx32,
x86_32->cache->reg_list[reg].name,
arch_info->op,
*regval);
@ -670,7 +671,7 @@ static int write_hw_reg(struct target *t, int reg, uint32_t regval, uint8_t cach
if (cache)
regval = buf_get_u32(x86_32->cache->reg_list[reg].value, 0, 32);
buf_set_u32(reg_buf, 0, 32, regval);
LOG_DEBUG("reg=%s, op=0x%016" PRIx64 ", val=%08" PRIx32,
LOG_DEBUG("reg=%s, op=0x%016" PRIx64 ", val=0x%08" PRIx32,
x86_32->cache->reg_list[reg].name,
arch_info->op,
regval);
@ -749,7 +750,7 @@ static int transaction_status(struct target *t)
{
uint32_t tapstatus = get_tapstatus(t);
if ((TS_EN_PM_BIT | TS_PRDY_BIT) & tapstatus) {
LOG_ERROR("%s transaction error tapstatus = %08" PRIx32
LOG_ERROR("%s transaction error tapstatus = 0x%08" PRIx32
, __func__, tapstatus);
return ERROR_FAIL;
} else {
@ -865,7 +866,7 @@ int lakemont_poll(struct target *t)
if ((ts & TS_PM_BIT) && (ts & TS_PMCR_BIT)) {
LOG_DEBUG("redirect to PM, tapstatus=%08" PRIx32, get_tapstatus(t));
LOG_DEBUG("redirect to PM, tapstatus=0x%08" PRIx32, get_tapstatus(t));
t->state = TARGET_DEBUG_RUNNING;
if (save_context(t) != ERROR_OK)
@ -893,7 +894,7 @@ int lakemont_poll(struct target *t)
uint32_t dr7 = buf_get_u32(x86_32->cache->reg_list[DR7].value, 0, 32);
uint32_t type = dr7 & (0x03 << (DR7_RW_SHIFT + hwbreakpoint*DR7_RW_LEN_SIZE));
if (type == DR7_BP_EXECUTE) {
LOG_USER("hit hardware breakpoint (hwreg=%d) at 0x%08" PRIx32, hwbreakpoint, eip);
LOG_USER("hit hardware breakpoint (hwreg=%" PRIu32 ") at 0x%08" PRIx32, hwbreakpoint, eip);
} else {
uint32_t address = 0;
switch (hwbreakpoint) {
@ -911,7 +912,7 @@ int lakemont_poll(struct target *t)
address = buf_get_u32(x86_32->cache->reg_list[DR3].value, 0, 32);
break;
}
LOG_USER("hit '%s' watchpoint for 0x%08" PRIx32 " (hwreg=%d) at 0x%08" PRIx32,
LOG_USER("hit '%s' watchpoint for 0x%08" PRIx32 " (hwreg=%" PRIu32 ") at 0x%08" PRIx32,
type == DR7_BP_WRITE ? "write" : "access", address,
hwbreakpoint, eip);
}
@ -1044,11 +1045,11 @@ int lakemont_step(struct target *t, int current,
}
/* Set EFLAGS[TF] and PMCR[IR], exit pm and wait for PRDY# */
LOG_DEBUG("modifying PMCR = %d and EFLAGS = %08" PRIx32, pmcr, eflags);
LOG_DEBUG("modifying PMCR = 0x%08" PRIx32 " and EFLAGS = 0x%08" PRIx32, pmcr, eflags);
eflags = eflags | (EFLAGS_TF | EFLAGS_RF);
buf_set_u32(x86_32->cache->reg_list[EFLAGS].value, 0, 32, eflags);
buf_set_u32(x86_32->cache->reg_list[PMCR].value, 0, 32, 1);
LOG_DEBUG("EFLAGS [TF] [RF] bits set=%08" PRIx32 ", PMCR=%d, EIP=%08" PRIx32,
LOG_DEBUG("EFLAGS [TF] [RF] bits set=0x%08" PRIx32 ", PMCR=0x%08" PRIx32 ", EIP=0x%08" PRIx32,
eflags, pmcr, eip);
tapstatus = get_tapstatus(t);

19
src/target/lakemont.h
View File

@ -32,6 +32,7 @@
#ifndef LAKEMONT_H
#define LAKEMONT_H
#include <jtag/jtag.h>
#include <helper/types.h>
/* The Intel Quark SoC X1000 Core is codenamed lakemont */
@ -59,18 +60,18 @@
/* needed during lakemont probemode */
#define NOT_PMREG 0xfe
#define NOT_AVAIL_REG 0xff
#define PM_DSB 0x00000000
#define PM_DSL 0xFFFFFFFF
#define PM_DSAR 0x004F9300
#define PM_DR7 0x00000400
#define PM_DSB ((uint32_t)0x00000000)
#define PM_DSL ((uint32_t)0xFFFFFFFF)
#define PM_DSAR ((uint32_t)0x004F9300)
#define PM_DR7 ((uint32_t)0x00000400)
#define DELAY_SUBMITPIR 0 /* for now 0 is working */
/* lakemont tapstatus bits */
#define TS_PRDY_BIT 0x00000001
#define TS_EN_PM_BIT 0x00000002
#define TS_PM_BIT 0x00000004
#define TS_PMCR_BIT 0x00000008
#define TS_SBP_BIT 0x00000010
#define TS_PRDY_BIT ((uint32_t)0x00000001)
#define TS_EN_PM_BIT ((uint32_t)0x00000002)
#define TS_PM_BIT ((uint32_t)0x00000004)
#define TS_PMCR_BIT ((uint32_t)0x00000008)
#define TS_SBP_BIT ((uint32_t)0x00000010)
struct lakemont_core_reg {
uint32_t num;

120
src/target/x86_32_common.c
View File

@ -172,14 +172,14 @@ static int read_phys_mem(struct target *t, uint32_t phys_address,
{
int retval = ERROR_OK;
bool pg_disabled = false;
LOG_DEBUG("addr=%08" PRIx32 ", size=%d, count=%d, buf=%p",
LOG_DEBUG("addr=0x%08" PRIx32 ", size=%" PRIu32 ", count=0x%" PRIx32 ", buf=%p",
phys_address, size, count, buffer);
struct x86_32_common *x86_32 = target_to_x86_32(t);
if (check_not_halted(t))
return ERROR_TARGET_NOT_HALTED;
if (!count || !buffer || !phys_address) {
LOG_ERROR("%s invalid params count=%d, buf=%p, addr=%08" PRIx32,
LOG_ERROR("%s invalid params count=0x%" PRIx32 ", buf=%p, addr=0x%08" PRIx32,
__func__, count, buffer, phys_address);
return ERROR_COMMAND_ARGUMENT_INVALID;
}
@ -187,8 +187,10 @@ static int read_phys_mem(struct target *t, uint32_t phys_address,
/* to access physical memory, switch off the CR0.PG bit */
if (x86_32->is_paging_enabled(t)) {
retval = x86_32->disable_paging(t);
if (retval != ERROR_OK)
if (retval != ERROR_OK) {
LOG_ERROR("%s could not disable paging", __func__);
return retval;
}
pg_disabled = true;
}
@ -211,8 +213,10 @@ static int read_phys_mem(struct target *t, uint32_t phys_address,
/* restore CR0.PG bit if needed (regardless of retval) */
if (pg_disabled) {
retval = x86_32->enable_paging(t);
if (retval != ERROR_OK)
if (retval != ERROR_OK) {
LOG_ERROR("%s could not enable paging", __func__);
return retval;
}
pg_disabled = true;
}
/* TODO: After reading memory from target, we must replace
@ -231,7 +235,7 @@ int x86_32_common_write_phys_mem(struct target *t, uint32_t phys_address,
check_not_halted(t);
if (!count || !buffer || !phys_address) {
LOG_ERROR("%s invalid params count=%d, buf=%p, addr=%08" PRIx32,
LOG_ERROR("%s invalid params count=0x%" PRIx32 ", buf=%p, addr=0x%08" PRIx32,
__func__, count, buffer, phys_address);
return ERROR_COMMAND_ARGUMENT_INVALID;
}
@ -272,12 +276,12 @@ static int write_phys_mem(struct target *t, uint32_t phys_address,
int retval = ERROR_OK;
bool pg_disabled = false;
struct x86_32_common *x86_32 = target_to_x86_32(t);
LOG_DEBUG("addr=%08" PRIx32 ", size=%d, count=%d, buf=%p",
LOG_DEBUG("addr=0x%08" PRIx32 ", size=%" PRIu32 ", count=0x%" PRIx32 ", buf=%p",
phys_address, size, count, buffer);
check_not_halted(t);
if (!count || !buffer || !phys_address) {
LOG_ERROR("%s invalid params count=%d, buf=%p, addr=%08" PRIx32,
LOG_ERROR("%s invalid params count=0x%" PRIx32 ", buf=%p, addr=0x%08" PRIx32,
__func__, count, buffer, phys_address);
return ERROR_COMMAND_ARGUMENT_INVALID;
}
@ -290,8 +294,10 @@ static int write_phys_mem(struct target *t, uint32_t phys_address,
/* to access physical memory, switch off the CR0.PG bit */
if (x86_32->is_paging_enabled(t)) {
retval = x86_32->disable_paging(t);
if (retval != ERROR_OK)
if (retval != ERROR_OK) {
LOG_ERROR("%s could not disable paging", __func__);
return retval;
}
pg_disabled = true;
}
for (uint32_t i = 0; i < count; i++) {
@ -313,8 +319,10 @@ static int write_phys_mem(struct target *t, uint32_t phys_address,
/* restore CR0.PG bit if needed (regardless of retval) */
if (pg_disabled) {
retval = x86_32->enable_paging(t);
if (retval != ERROR_OK)
if (retval != ERROR_OK) {
LOG_ERROR("%s could not enable paging", __func__);
return retval;
}
}
return retval;
}
@ -565,11 +573,11 @@ int x86_32_common_read_memory(struct target *t, uint32_t addr,
{
int retval = ERROR_OK;
struct x86_32_common *x86_32 = target_to_x86_32(t);
LOG_DEBUG("addr=%08" PRIx32 ", size=%d, count=%d, buf=%p",
LOG_DEBUG("addr=0x%08" PRIx32 ", size=%" PRIu32 ", count=0x%" PRIx32 ", buf=%p",
addr, size, count, buf);
check_not_halted(t);
if (!count || !buf || !addr) {
LOG_ERROR("%s invalid params count=%d, buf=%p, addr=%08" PRIx32,
LOG_ERROR("%s invalid params count=0x%" PRIx32 ", buf=%p, addr=0x%08" PRIx32,
__func__, count, buf, addr);
return ERROR_COMMAND_ARGUMENT_INVALID;
}
@ -579,8 +587,10 @@ int x86_32_common_read_memory(struct target *t, uint32_t addr,
* conversion to physical address space needed
*/
retval = x86_32->disable_paging(t);
if (retval != ERROR_OK)
if (retval != ERROR_OK) {
LOG_ERROR("%s could not disable paging", __func__);
return retval;
}
uint32_t physaddr = 0;
if (calcaddr_pyhsfromlin(t, addr, &physaddr) != ERROR_OK) {
LOG_ERROR("%s failed to calculate physical address from 0x%08" PRIx32, __func__, addr);
@ -598,8 +608,10 @@ int x86_32_common_read_memory(struct target *t, uint32_t addr,
}
/* restore PG bit if it was cleared prior (regardless of retval) */
retval = x86_32->enable_paging(t);
if (retval != ERROR_OK)
if (retval != ERROR_OK) {
LOG_ERROR("%s could not enable paging", __func__);
return retval;
}
} else {
/* paging is off - linear address is physical address */
if (x86_32_common_read_phys_mem(t, addr, size, count, buf) != ERROR_OK) {
@ -616,11 +628,11 @@ int x86_32_common_write_memory(struct target *t, uint32_t addr,
{
int retval = ERROR_OK;
struct x86_32_common *x86_32 = target_to_x86_32(t);
LOG_DEBUG("addr=%08" PRIx32 ", size=%d, count=%d, buf=%p",
LOG_DEBUG("addr=0x%08" PRIx32 ", size=%" PRIu32 ", count=0x%" PRIx32 ", buf=%p",
addr, size, count, buf);
check_not_halted(t);
if (!count || !buf || !addr) {
LOG_ERROR("%s invalid params count=%d, buf=%p, addr=%08" PRIx32,
LOG_ERROR("%s invalid params count=0x%" PRIx32 ", buf=%p, addr=0x%08" PRIx32,
__func__, count, buf, addr);
return ERROR_COMMAND_ARGUMENT_INVALID;
}
@ -629,8 +641,10 @@ int x86_32_common_write_memory(struct target *t, uint32_t addr,
* conversion to physical address space needed
*/
retval = x86_32->disable_paging(t);
if (retval != ERROR_OK)
if (retval != ERROR_OK) {
LOG_ERROR("%s could not disable paging", __func__);
return retval;
}
uint32_t physaddr = 0;
if (calcaddr_pyhsfromlin(t, addr, &physaddr) != ERROR_OK) {
LOG_ERROR("%s failed to calculate physical address from 0x%08" PRIx32,
@ -649,8 +663,10 @@ int x86_32_common_write_memory(struct target *t, uint32_t addr,
}
/* restore PG bit if it was cleared prior (regardless of retval) */
retval = x86_32->enable_paging(t);
if (retval != ERROR_OK)
if (retval != ERROR_OK) {
LOG_ERROR("%s could not enable paging", __func__);
return retval;
}
} else {
/* paging is off - linear address is physical address */
@ -671,7 +687,7 @@ int x86_32_common_read_io(struct target *t, uint32_t addr,
bool use32 = (buf_get_u32(x86_32->cache->reg_list[CSAR].value, 0, 32)) & CSAR_D;
int retval = ERROR_FAIL;
bool pg_disabled = false;
LOG_DEBUG("addr=%08" PRIx32 ", size=%d, buf=%p", addr, size, buf);
LOG_DEBUG("addr=0x%08" PRIx32 ", size=%" PRIu32 ", buf=%p", addr, size, buf);
check_not_halted(t);
if (!buf || !addr) {
LOG_ERROR("%s invalid params buf=%p, addr=%08" PRIx32, __func__, buf, addr);
@ -685,8 +701,10 @@ int x86_32_common_read_io(struct target *t, uint32_t addr,
/* to access physical memory, switch off the CR0.PG bit */
if (x86_32->is_paging_enabled(t)) {
retval = x86_32->disable_paging(t);
if (retval != ERROR_OK)
if (retval != ERROR_OK) {
LOG_ERROR("%s could not disable paging", __func__);
return retval;
}
pg_disabled = true;
}
switch (size) {
@ -715,8 +733,10 @@ int x86_32_common_read_io(struct target *t, uint32_t addr,
/* restore CR0.PG bit if needed */
if (pg_disabled) {
retval = x86_32->enable_paging(t);
if (retval != ERROR_OK)
if (retval != ERROR_OK) {
LOG_ERROR("%s could not enable paging", __func__);
return retval;
}
pg_disabled = false;
}
uint32_t regval = 0;
@ -741,12 +761,12 @@ int x86_32_common_write_io(struct target *t, uint32_t addr,
struct x86_32_common *x86_32 = target_to_x86_32(t);
/* if CS.D bit=1 then its a 32 bit code segment, else 16 */
bool use32 = (buf_get_u32(x86_32->cache->reg_list[CSAR].value, 0, 32)) & CSAR_D;
LOG_DEBUG("addr=%08" PRIx32 ", size=%d, buf=%p", addr, size, buf);
LOG_DEBUG("addr=0x%08" PRIx32 ", size=%" PRIu32 ", buf=%p", addr, size, buf);
check_not_halted(t);
int retval = ERROR_FAIL;
bool pg_disabled = false;
if (!buf || !addr) {
LOG_ERROR("%s invalid params buf=%p, addr=%08" PRIx32, __func__, buf, addr);
LOG_ERROR("%s invalid params buf=%p, addr=0x%08" PRIx32, __func__, buf, addr);
return retval;
}
/* no do the write */
@ -766,8 +786,10 @@ int x86_32_common_write_io(struct target *t, uint32_t addr,
/* to access physical memory, switch off the CR0.PG bit */
if (x86_32->is_paging_enabled(t)) {
retval = x86_32->disable_paging(t);
if (retval != ERROR_OK)
if (retval != ERROR_OK) {
LOG_ERROR("%s could not disable paging", __func__);
return retval;
}
pg_disabled = true;
}
switch (size) {
@ -796,8 +818,10 @@ int x86_32_common_write_io(struct target *t, uint32_t addr,
/* restore CR0.PG bit if needed */
if (pg_disabled) {
retval = x86_32->enable_paging(t);
if (retval != ERROR_OK)
if (retval != ERROR_OK) {
LOG_ERROR("%s could not enable paging", __func__);
return retval;
}
pg_disabled = false;
}
retval = x86_32->transaction_status(t);
@ -828,7 +852,7 @@ int x86_32_common_remove_watchpoint(struct target *t, struct watchpoint *wp)
int x86_32_common_add_breakpoint(struct target *t, struct breakpoint *bp)
{
LOG_DEBUG("type=%d, addr=%08" PRIx32, bp->type, bp->address);
LOG_DEBUG("type=%d, addr=0x%08" PRIx32, bp->type, bp->address);
if (check_not_halted(t))
return ERROR_TARGET_NOT_HALTED;
/* set_breakpoint() will return ERROR_TARGET_RESOURCE_NOT_AVAILABLE if all
@ -839,7 +863,7 @@ int x86_32_common_add_breakpoint(struct target *t, struct breakpoint *bp)
int x86_32_common_remove_breakpoint(struct target *t, struct breakpoint *bp)
{
LOG_DEBUG("type=%d, addr=%08" PRIx32, bp->type, bp->address);
LOG_DEBUG("type=%d, addr=0x%08" PRIx32, bp->type, bp->address);
if (check_not_halted(t))
return ERROR_TARGET_NOT_HALTED;
if (bp->set)
@ -852,7 +876,7 @@ static int set_debug_regs(struct target *t, uint32_t address,
uint8_t bp_num, uint8_t bp_type, uint8_t bp_length)
{
struct x86_32_common *x86_32 = target_to_x86_32(t);
LOG_DEBUG("addr=%08" PRIx32 ", bp_num=%d, bp_type=%d, pb_length=%d",
LOG_DEBUG("addr=0x%08" PRIx32 ", bp_num=%" PRIu8 ", bp_type=%" PRIu8 ", pb_length=%" PRIu8,
address, bp_num, bp_type, bp_length);
/* DR7 - set global enable */
@ -912,14 +936,14 @@ static int set_debug_regs(struct target *t, uint32_t address,
static int unset_debug_regs(struct target *t, uint8_t bp_num)
{
struct x86_32_common *x86_32 = target_to_x86_32(t);
LOG_DEBUG("bp_num=%d", bp_num);
LOG_DEBUG("bp_num=%" PRIu8, bp_num);
uint32_t dr7 = buf_get_u32(x86_32->cache->reg_list[DR7].value, 0, 32);
if (!(DR7_BP_FREE(dr7, bp_num))) {
DR7_GLOBAL_DISABLE(dr7, bp_num);
} else {
LOG_ERROR("%s dr7 error, not enabled, val=%08" PRIx32, __func__, dr7);
LOG_ERROR("%s dr7 error, not enabled, val=0x%08" PRIx32, __func__, dr7);
return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
}
/* this will clear rw and len bits */
@ -949,7 +973,7 @@ static int set_hwbp(struct target *t, struct breakpoint *bp)
while (debug_reg_list[hwbp_num].used && (hwbp_num < x86_32->num_hw_bpoints))
hwbp_num++;
if (hwbp_num >= x86_32->num_hw_bpoints) {
LOG_ERROR("%s no free hw breakpoint bpid=%d", __func__, bp->unique_id);
LOG_ERROR("%s no free hw breakpoint bpid=0x%" PRIx32, __func__, bp->unique_id);
return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
}
if (set_debug_regs(t, bp->address, hwbp_num, DR7_BP_EXECUTE, 1) != ERROR_OK)
@ -957,7 +981,7 @@ static int set_hwbp(struct target *t, struct breakpoint *bp)
bp->set = hwbp_num + 1;
debug_reg_list[hwbp_num].used = 1;
debug_reg_list[hwbp_num].bp_value = bp->address;
LOG_USER("%s hardware breakpoint %d set at 0x%08" PRIx32 " (hwreg=%d)", __func__,
LOG_USER("%s hardware breakpoint %" PRIu32 " set at 0x%08" PRIx32 " (hwreg=%" PRIu8 ")", __func__,
bp->unique_id, debug_reg_list[hwbp_num].bp_value, hwbp_num);
return ERROR_OK;
}
@ -969,7 +993,7 @@ static int unset_hwbp(struct target *t, struct breakpoint *bp)
int hwbp_num = bp->set - 1;
if ((hwbp_num < 0) || (hwbp_num >= x86_32->num_hw_bpoints)) {
LOG_ERROR("%s invalid breakpoint number=%d, bpid=%d",
LOG_ERROR("%s invalid breakpoint number=%d, bpid=%" PRIu32,
__func__, hwbp_num, bp->unique_id);
return ERROR_OK;
}
@ -979,7 +1003,7 @@ static int unset_hwbp(struct target *t, struct breakpoint *bp)
debug_reg_list[hwbp_num].used = 0;
debug_reg_list[hwbp_num].bp_value = 0;
LOG_USER("%s hardware breakpoint %d removed from 0x%08" PRIx32 " (hwreg=%d)",
LOG_USER("%s hardware breakpoint %" PRIu32 " removed from 0x%08" PRIx32 " (hwreg=%d)",
__func__, bp->unique_id, bp->address, hwbp_num);
return ERROR_OK;
}
@ -987,7 +1011,7 @@ static int unset_hwbp(struct target *t, struct breakpoint *bp)
static int set_swbp(struct target *t, struct breakpoint *bp)
{
struct x86_32_common *x86_32 = target_to_x86_32(t);
LOG_DEBUG("id %d", bp->unique_id);
LOG_DEBUG("id %" PRIx32, bp->unique_id);
uint32_t physaddr;
uint8_t opcode = SW_BP_OPCODE;
uint8_t readback;
@ -997,7 +1021,7 @@ static int set_swbp(struct target *t, struct breakpoint *bp)
if (read_phys_mem(t, physaddr, 1, 1, bp->orig_instr))
return ERROR_FAIL;
LOG_DEBUG("set software breakpoint - orig byte=%02" PRIx8 "", *bp->orig_instr);
LOG_DEBUG("set software breakpoint - orig byte=0x%02" PRIx8 "", *bp->orig_instr);
/* just write the instruction trap byte */
if (write_phys_mem(t, physaddr, 1, 1, &opcode))
@ -1010,7 +1034,7 @@ static int set_swbp(struct target *t, struct breakpoint *bp)
if (readback != SW_BP_OPCODE) {
LOG_ERROR("%s software breakpoint error at 0x%08" PRIx32 ", check memory",
__func__, bp->address);
LOG_ERROR("%s readback=%02" PRIx8 " orig=%02" PRIx8 "",
LOG_ERROR("%s readback=0x%02" PRIx8 " orig=0x%02" PRIx8 "",
__func__, readback, *bp->orig_instr);
return ERROR_FAIL;
}
@ -1035,7 +1059,7 @@ static int set_swbp(struct target *t, struct breakpoint *bp)
addto = addto->next;
addto->next = new_patch;
}
LOG_USER("%s software breakpoint %d set at 0x%08" PRIx32,
LOG_USER("%s software breakpoint %" PRIu32 " set at 0x%08" PRIx32,
__func__, bp->unique_id, bp->address);
return ERROR_OK;
}
@ -1043,7 +1067,7 @@ static int set_swbp(struct target *t, struct breakpoint *bp)
static int unset_swbp(struct target *t, struct breakpoint *bp)
{
struct x86_32_common *x86_32 = target_to_x86_32(t);
LOG_DEBUG("id %d", bp->unique_id);
LOG_DEBUG("id %" PRIx32, bp->unique_id);
uint32_t physaddr;
uint8_t current_instr;
@ -1059,7 +1083,7 @@ static int unset_swbp(struct target *t, struct breakpoint *bp)
} else {
LOG_ERROR("%s software breakpoint remove error at 0x%08" PRIx32 ", check memory",
__func__, bp->address);
LOG_ERROR("%s current=%02" PRIx8 " orig=%02" PRIx8 "",
LOG_ERROR("%s current=0x%02" PRIx8 " orig=0x%02" PRIx8 "",
__func__, current_instr, *bp->orig_instr);
return ERROR_FAIL;
}
@ -1083,7 +1107,7 @@ static int unset_swbp(struct target *t, struct breakpoint *bp)
}
}
LOG_USER("%s software breakpoint %d removed from 0x%08" PRIx32,
LOG_USER("%s software breakpoint %" PRIu32 " removed from 0x%08" PRIx32,
__func__, bp->unique_id, bp->address);
return ERROR_OK;
}
@ -1092,7 +1116,7 @@ static int set_breakpoint(struct target *t, struct breakpoint *bp)
{
int error = ERROR_OK;
struct x86_32_common *x86_32 = target_to_x86_32(t);
LOG_DEBUG("type=%d, addr=%08" PRIx32, bp->type, bp->address);
LOG_DEBUG("type=%d, addr=0x%08" PRIx32, bp->type, bp->address);
if (bp->set) {
LOG_ERROR("breakpoint already set");
return error;
@ -1123,7 +1147,7 @@ static int set_breakpoint(struct target *t, struct breakpoint *bp)
static int unset_breakpoint(struct target *t, struct breakpoint *bp)
{
LOG_DEBUG("type=%d, addr=%08" PRIx32, bp->type, bp->address);
LOG_DEBUG("type=%d, addr=0x%08" PRIx32, bp->type, bp->address);
if (!bp->set) {
LOG_WARNING("breakpoint not set");
return ERROR_OK;
@ -1151,7 +1175,7 @@ static int set_watchpoint(struct target *t, struct watchpoint *wp)
struct x86_32_common *x86_32 = target_to_x86_32(t);
struct x86_32_dbg_reg *debug_reg_list = x86_32->hw_break_list;
int wp_num = 0;
LOG_DEBUG("type=%d, addr=%08" PRIx32, wp->rw, wp->address);
LOG_DEBUG("type=%d, addr=0x%08" PRIx32, wp->rw, wp->address);
if (wp->set) {
LOG_ERROR("%s watchpoint already set", __func__);
@ -1196,7 +1220,7 @@ static int set_watchpoint(struct target *t, struct watchpoint *wp)
wp->set = wp_num + 1;
debug_reg_list[wp_num].used = 1;
debug_reg_list[wp_num].bp_value = wp->address;
LOG_USER("'%s' watchpoint %d set at 0x%08" PRIx32 " with length %d (hwreg=%d)",
LOG_USER("'%s' watchpoint %d set at 0x%08" PRIx32 " with length %" PRIu32 " (hwreg=%d)",
wp->rw == WPT_READ ? "read" : wp->rw == WPT_WRITE ?
"write" : wp->rw == WPT_ACCESS ? "access" : "?",
wp->unique_id, wp->address, wp->length, wp_num);
@ -1207,7 +1231,7 @@ static int unset_watchpoint(struct target *t, struct watchpoint *wp)
{
struct x86_32_common *x86_32 = target_to_x86_32(t);
struct x86_32_dbg_reg *debug_reg_list = x86_32->hw_break_list;
LOG_DEBUG("type=%d, addr=%08" PRIx32, wp->rw, wp->address);
LOG_DEBUG("type=%d, addr=0x%08" PRIx32, wp->rw, wp->address);
if (!wp->set) {
LOG_WARNING("watchpoint not set");
return ERROR_OK;
@ -1225,7 +1249,7 @@ static int unset_watchpoint(struct target *t, struct watchpoint *wp)
debug_reg_list[wp_num].bp_value = 0;
wp->set = 0;
LOG_USER("'%s' watchpoint %d removed from 0x%08" PRIx32 " with length %d (hwreg=%d)",
LOG_USER("'%s' watchpoint %d removed from 0x%08" PRIx32 " with length %" PRIu32 " (hwreg=%d)",
wp->rw == WPT_READ ? "read" : wp->rw == WPT_WRITE ?
"write" : wp->rw == WPT_ACCESS ? "access" : "?",
wp->unique_id, wp->address, wp->length, wp_num);
@ -1334,7 +1358,7 @@ COMMAND_HANDLER(handle_iod_command)
uint32_t address;
COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], address);
if (address > 0xffff) {
LOG_ERROR("%s IA-32 I/O space is 2^16, %08" PRIx32 " exceeds max", __func__, address);
LOG_ERROR("%s IA-32 I/O space is 2^16, 0x%08" PRIx32 " exceeds max", __func__, address);
return ERROR_COMMAND_SYNTAX_ERROR;
}
@ -1368,7 +1392,7 @@ static int target_fill_io(struct target *target,
/* value */
uint32_t b)
{
LOG_DEBUG("address=%08X, data_size=%d, b=%08X",
LOG_DEBUG("address=0x%08" PRIx32 ", data_size=%u, b=0x%08" PRIx32,
address, data_size, b);
uint8_t target_buf[data_size];
switch (data_size) {

33
src/target/x86_32_common.h
View File

@ -34,6 +34,7 @@
#include <jtag/jtag.h>
#include <helper/command.h>
#include <helper/types.h>
extern const struct command_registration x86_32_command_handlers[];
@ -42,27 +43,27 @@ extern const struct command_registration x86_32_command_handlers[];
#define WORD 2
#define DWORD 4
#define EFLAGS_TF 0x00000100 /* Trap Flag */
#define EFLAGS_IF 0x00000200 /* Interrupt Flag */
#define EFLAGS_RF 0x00010000 /* Resume Flag */
#define EFLAGS_VM86 0x00020000 /* Virtual 8086 Mode */
#define EFLAGS_TF ((uint32_t)0x00000100) /* Trap Flag */
#define EFLAGS_IF ((uint32_t)0x00000200) /* Interrupt Flag */
#define EFLAGS_RF ((uint32_t)0x00010000) /* Resume Flag */
#define EFLAGS_VM86 ((uint32_t)0x00020000) /* Virtual 8086 Mode */
#define CSAR_DPL 0x00006000
#define CSAR_D 0x00400000
#define SSAR_DPL 0x00006000
#define CSAR_DPL ((uint32_t)0x00006000)
#define CSAR_D ((uint32_t)0x00400000)
#define SSAR_DPL ((uint32_t)0x00006000)
#define CR0_PE 0x00000001 /* Protected Mode Enable */
#define CR0_NW 0x20000000 /* Non Write-Through */
#define CR0_CD 0x40000000 /* Cache Disable */
#define CR0_PG 0x80000000 /* Paging Enable */
#define CR0_PE ((uint32_t)0x00000001) /* Protected Mode Enable */
#define CR0_NW ((uint32_t)0x20000000) /* Non Write-Through */
#define CR0_CD ((uint32_t)0x40000000) /* Cache Disable */
#define CR0_PG ((uint32_t)0x80000000) /* Paging Enable */
/* TODO - move back to PM specific file */
#define PM_DR6 0xFFFF0FF0
#define PM_DR6 ((uint32_t)0xFFFF0FF0)
#define DR6_BRKDETECT_0 0x00000001 /* B0 through B3 */
#define DR6_BRKDETECT_1 0x00000002 /* breakpoint condition detected */
#define DR6_BRKDETECT_2 0x00000004
#define DR6_BRKDETECT_3 0x00000008
#define DR6_BRKDETECT_0 ((uint32_t)0x00000001) /* B0 through B3 */
#define DR6_BRKDETECT_1 ((uint32_t)0x00000002) /* breakpoint condition detected */
#define DR6_BRKDETECT_2 ((uint32_t)0x00000004)
#define DR6_BRKDETECT_3 ((uint32_t)0x00000008)
enum {
/* general purpose registers */