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stlink: fix vector catch not being cleared 

Seems after a reset the stlink is not clearing the vector catch (VC_CORERESET)
in the Debug Control Register.

This has the side effect if the user presses an external reset the core will
halt, this patch fixes that.

Change-Id: Ic3b2c3991b79cacbbd901c02b79613c2e204e71f
Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk>
Reviewed-on: http://openocd.zylin.com/905
Tested-by: jenkins
Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
This commit is contained in:
Spencer Oliver 2012-10-08 10:05:45 +01:00 committed by Freddie Chopin
parent 98a41bca6e
commit 7165e05cf6
1 changed files with 10 additions and 1 deletions
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11
src/target/stm32_stlink.c
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@ -325,6 +325,7 @@ static int stm32_stlink_load_context(struct target *target)
static int stlink_debug_entry(struct target *target) static int stlink_debug_entry(struct target *target)
{ {
struct stlink_interface_s *stlink_if = target_to_stlink(target);
struct armv7m_common *armv7m = target_to_armv7m(target); struct armv7m_common *armv7m = target_to_armv7m(target);
struct arm *arm = &armv7m->arm; struct arm *arm = &armv7m->arm;
struct reg *r; struct reg *r;
@ -337,6 +338,9 @@ static int stlink_debug_entry(struct target *target)
stm32_stlink_load_context(target); stm32_stlink_load_context(target);
/* make sure we clear the vector catch bit */
stlink_if->layout->api->write_debug_reg(stlink_if->fd, DCB_DEMCR, 0);
r = armv7m->core_cache->reg_list + ARMV7M_xPSR; r = armv7m->core_cache->reg_list + ARMV7M_xPSR;
xPSR = buf_get_u32(r->value, 0, 32); xPSR = buf_get_u32(r->value, 0, 32);
@ -427,7 +431,12 @@ static int stm32_stlink_assert_reset(struct target *target)
} }
stlink_if->layout->api->write_debug_reg(stlink_if->fd, DCB_DHCSR, DBGKEY|C_DEBUGEN); stlink_if->layout->api->write_debug_reg(stlink_if->fd, DCB_DHCSR, DBGKEY|C_DEBUGEN);
stlink_if->layout->api->write_debug_reg(stlink_if->fd, DCB_DEMCR, VC_CORERESET);
/* only set vector catch if halt is requested */
if (target->reset_halt)
stlink_if->layout->api->write_debug_reg(stlink_if->fd, DCB_DEMCR, VC_CORERESET);
else
stlink_if->layout->api->write_debug_reg(stlink_if->fd, DCB_DEMCR, 0);
if (jtag_reset_config & RESET_HAS_SRST) { if (jtag_reset_config & RESET_HAS_SRST) {
if (!srst_asserted) { if (!srst_asserted) {