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ARM11: use shared DSCR bit names 

For the bits now defined in "arm_dpm.h", switch to the
shared DSCR_* symbol and remove the ARM11_DSCR_* version.

Define DSCR_INT_DIS and use it instead of the ARM11_DSCR_*
sibling symbol.  (Note:  for both ARM11 and Cortex-A8, this
should arguably be enabled by default when single stepping.)

Remove some other unused declarations in "arm11.h".

Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
This commit is contained in:
David Brownell 2009-12-03 16:08:04 -08:00
parent eb6c880ddc
commit 6eee0729d7
3 changed files with 24 additions and 42 deletions
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42
src/target/arm11.c
View File

@ -40,6 +40,10 @@
#define _DEBUG_INSTRUCTION_EXECUTION_ #define _DEBUG_INSTRUCTION_EXECUTION_
#endif #endif
/* FIXME none of these flags should be global to all ARM11 cores!
* Most of them shouldn't exist at all, once the code works...
*/
static bool arm11_config_memwrite_burst = true; static bool arm11_config_memwrite_burst = true;
static bool arm11_config_memwrite_error_fatal = true; static bool arm11_config_memwrite_error_fatal = true;
static uint32_t arm11_vcr = 0; static uint32_t arm11_vcr = 0;
@ -59,18 +63,18 @@ static int arm11_check_init(struct arm11_common *arm11)
CHECK_RETVAL(arm11_read_DSCR(arm11)); CHECK_RETVAL(arm11_read_DSCR(arm11));
LOG_DEBUG("DSCR %08x", (unsigned) arm11->dscr); LOG_DEBUG("DSCR %08x", (unsigned) arm11->dscr);
if (!(arm11->dscr & ARM11_DSCR_MODE_SELECT)) if (!(arm11->dscr & DSCR_HALT_DBG_MODE))
{ {
LOG_DEBUG("Bringing target into debug mode"); LOG_DEBUG("Bringing target into debug mode");
arm11->dscr |= ARM11_DSCR_MODE_SELECT; /* Halt debug-mode */ arm11->dscr |= DSCR_HALT_DBG_MODE;
arm11_write_DSCR(arm11, arm11->dscr); arm11_write_DSCR(arm11, arm11->dscr);
/* add further reset initialization here */ /* add further reset initialization here */
arm11->simulate_reset_on_next_halt = true; arm11->simulate_reset_on_next_halt = true;
if (arm11->dscr & ARM11_DSCR_CORE_HALTED) if (arm11->dscr & DSCR_CORE_HALTED)
{ {
/** \todo TODO: this needs further scrutiny because /** \todo TODO: this needs further scrutiny because
* arm11_debug_entry() never gets called. (WHY NOT?) * arm11_debug_entry() never gets called. (WHY NOT?)
@ -113,7 +117,7 @@ static int arm11_debug_entry(struct arm11_common *arm11)
/* See e.g. ARM1136 TRM, "14.8.4 Entering Debug state" */ /* See e.g. ARM1136 TRM, "14.8.4 Entering Debug state" */
/* maybe save wDTR (pending DCC write to debug SW, e.g. libdcc) */ /* maybe save wDTR (pending DCC write to debug SW, e.g. libdcc) */
arm11->is_wdtr_saved = !!(arm11->dscr & ARM11_DSCR_WDTR_FULL); arm11->is_wdtr_saved = !!(arm11->dscr & DSCR_DTR_TX_FULL);
if (arm11->is_wdtr_saved) if (arm11->is_wdtr_saved)
{ {
arm11_add_debug_SCAN_N(arm11, 0x05, ARM11_TAP_DEFAULT); arm11_add_debug_SCAN_N(arm11, 0x05, ARM11_TAP_DEFAULT);
@ -131,15 +135,13 @@ static int arm11_debug_entry(struct arm11_common *arm11)
} }
/* DSCR: set ARM11_DSCR_EXECUTE_ARM_INSTRUCTION_ENABLE /* DSCR: set the Execute ARM instruction enable bit.
* *
* ARM1176 spec says this is needed only for wDTR/rDTR's "ITR mode", * ARM1176 spec says this is needed only for wDTR/rDTR's "ITR mode",
* but not to issue ITRs. ARM1136 seems to require this to issue * but not to issue ITRs(?). The ARMv7 arch spec says it's required
* ITR's as well... * for executing instructions via ITR.
*/ */
arm11_write_DSCR(arm11, DSCR_ITR_EN | arm11->dscr);
arm11_write_DSCR(arm11, ARM11_DSCR_EXECUTE_ARM_INSTRUCTION_ENABLE
| arm11->dscr);
/* From the spec: /* From the spec:
@ -188,7 +190,7 @@ static int arm11_debug_entry(struct arm11_common *arm11)
return retval; return retval;
/* maybe save rDTR (pending DCC read from debug SW, e.g. libdcc) */ /* maybe save rDTR (pending DCC read from debug SW, e.g. libdcc) */
arm11->is_rdtr_saved = !!(arm11->dscr & ARM11_DSCR_RDTR_FULL); arm11->is_rdtr_saved = !!(arm11->dscr & DSCR_DTR_RX_FULL);
if (arm11->is_rdtr_saved) if (arm11->is_rdtr_saved)
{ {
/* MRC p14,0,R0,c0,c5,0 (move rDTR -> r0 (-> wDTR -> local var)) */ /* MRC p14,0,R0,c0,c5,0 (move rDTR -> r0 (-> wDTR -> local var)) */
@ -248,7 +250,7 @@ static int arm11_leave_debug_state(struct arm11_common *arm11, bool bpwp)
{ {
CHECK_RETVAL(arm11_read_DSCR(arm11)); CHECK_RETVAL(arm11_read_DSCR(arm11));
if (arm11->dscr & (ARM11_DSCR_RDTR_FULL | ARM11_DSCR_WDTR_FULL)) if (arm11->dscr & (DSCR_DTR_RX_FULL | DSCR_DTR_TX_FULL))
{ {
/* /*
The wDTR/rDTR two registers that are used to send/receive data to/from The wDTR/rDTR two registers that are used to send/receive data to/from
@ -324,7 +326,7 @@ static int arm11_poll(struct target *target)
CHECK_RETVAL(arm11_check_init(arm11)); CHECK_RETVAL(arm11_check_init(arm11));
if (arm11->dscr & ARM11_DSCR_CORE_HALTED) if (arm11->dscr & DSCR_CORE_HALTED)
{ {
if (target->state != TARGET_HALTED) if (target->state != TARGET_HALTED)
{ {
@ -401,7 +403,7 @@ static int arm11_halt(struct target *target)
{ {
CHECK_RETVAL(arm11_read_DSCR(arm11)); CHECK_RETVAL(arm11_read_DSCR(arm11));
if (arm11->dscr & ARM11_DSCR_CORE_HALTED) if (arm11->dscr & DSCR_CORE_HALTED)
break; break;
@ -529,7 +531,7 @@ static int arm11_resume(struct target *target, int current,
LOG_DEBUG("DSCR %08x", (unsigned) arm11->dscr); LOG_DEBUG("DSCR %08x", (unsigned) arm11->dscr);
if (arm11->dscr & ARM11_DSCR_CORE_RESTARTED) if (arm11->dscr & DSCR_CORE_RESTARTED)
break; break;
@ -674,9 +676,9 @@ static int arm11_step(struct target *target, int current,
if (arm11_config_step_irq_enable) if (arm11_config_step_irq_enable)
/* this disable should be redundant ... */ /* this disable should be redundant ... */
arm11->dscr &= ~ARM11_DSCR_INTERRUPTS_DISABLE; arm11->dscr &= ~DSCR_INT_DIS;
else else
arm11->dscr |= ARM11_DSCR_INTERRUPTS_DISABLE; arm11->dscr |= DSCR_INT_DIS;
CHECK_RETVAL(arm11_leave_debug_state(arm11, handle_breakpoints)); CHECK_RETVAL(arm11_leave_debug_state(arm11, handle_breakpoints));
@ -690,8 +692,8 @@ static int arm11_step(struct target *target, int current,
while (1) while (1)
{ {
const uint32_t mask = ARM11_DSCR_CORE_RESTARTED const uint32_t mask = DSCR_CORE_RESTARTED
| ARM11_DSCR_CORE_HALTED; | DSCR_CORE_HALTED;
CHECK_RETVAL(arm11_read_DSCR(arm11)); CHECK_RETVAL(arm11_read_DSCR(arm11));
LOG_DEBUG("DSCR %08x e", (unsigned) arm11->dscr); LOG_DEBUG("DSCR %08x e", (unsigned) arm11->dscr);
@ -722,7 +724,7 @@ static int arm11_step(struct target *target, int current,
CHECK_RETVAL(arm11_debug_entry(arm11)); CHECK_RETVAL(arm11_debug_entry(arm11));
/* restore default state */ /* restore default state */
arm11->dscr &= ~ARM11_DSCR_INTERRUPTS_DISABLE; arm11->dscr &= ~DSCR_INT_DIS;
} }

23
src/target/arm11.h
View File

@ -38,6 +38,7 @@
} \ } \
} while (0) } while (0)
/* bits from ARMv7 DIDR */
enum arm11_debug_version enum arm11_debug_version
{ {
ARM11_DEBUG_V6 = 0x01, ARM11_DEBUG_V6 = 0x01,
@ -95,8 +96,6 @@ enum arm11_instructions
enum arm11_dscr enum arm11_dscr
{ {
ARM11_DSCR_CORE_HALTED = 1 << 0,
ARM11_DSCR_CORE_RESTARTED = 1 << 1,
ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_MASK = 0x0F << 2, ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_MASK = 0x0F << 2,
ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_HALT = 0x00 << 2, ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_HALT = 0x00 << 2,
@ -105,20 +104,6 @@ enum arm11_dscr
ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_BKPT_INSTRUCTION = 0x03 << 2, ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_BKPT_INSTRUCTION = 0x03 << 2,
ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_EDBGRQ = 0x04 << 2, ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_EDBGRQ = 0x04 << 2,
ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_VECTOR_CATCH = 0x05 << 2, ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_VECTOR_CATCH = 0x05 << 2,
ARM11_DSCR_STICKY_PRECISE_DATA_ABORT = 1 << 6,
ARM11_DSCR_STICKY_IMPRECISE_DATA_ABORT = 1 << 7,
ARM11_DSCR_INTERRUPTS_DISABLE = 1 << 11,
ARM11_DSCR_EXECUTE_ARM_INSTRUCTION_ENABLE = 1 << 13,
ARM11_DSCR_MODE_SELECT = 1 << 14,
ARM11_DSCR_WDTR_FULL = 1 << 29,
ARM11_DSCR_RDTR_FULL = 1 << 30,
};
enum arm11_cpsr
{
ARM11_CPSR_T = 1 << 5,
ARM11_CPSR_J = 1 << 24,
}; };
enum arm11_sc7 enum arm11_sc7
@ -132,10 +117,4 @@ enum arm11_sc7
ARM11_SC7_WCR0 = 112, ARM11_SC7_WCR0 = 112,
}; };
struct arm11_reg_state
{
uint32_t def_index;
struct target * target;
};
#endif /* ARM11_H */ #endif /* ARM11_H */

1
src/target/arm_dpm.h
View File

@ -141,6 +141,7 @@ void arm_dpm_report_wfar(struct arm_dpm *, uint32_t wfar);
*/ */
#define DSCR_CORE_HALTED (1 << 0) #define DSCR_CORE_HALTED (1 << 0)
#define DSCR_CORE_RESTARTED (1 << 1) #define DSCR_CORE_RESTARTED (1 << 1)
#define DSCR_INT_DIS (1 << 11)
#define DSCR_ITR_EN (1 << 13) #define DSCR_ITR_EN (1 << 13)
#define DSCR_HALT_DBG_MODE (1 << 14) #define DSCR_HALT_DBG_MODE (1 << 14)
#define DSCR_MON_DBG_MODE (1 << 15) #define DSCR_MON_DBG_MODE (1 << 15)