Fix: Prevent segfault in riscv_invalidate_register_cache for non-examined targets. (#692)

The segfault could be triggered if:

- At least one target failed to get examined (therefore does not have the
  register cache set up yet),

- and "reset" TCL command was issued, which internally tries to
  invalidate the register cache.

Minor cleanup: "registers_initialized" member removed from riscv_info_t
because it is not used anywhere.

Change-Id: I6288c0d4343ef6a330fb2a6b49d388e7eafa32a2
Signed-off-by: Jan Matyas <matyas@codasip.com>
This commit is contained in:
Jan Matyas 2022-06-16 18:58:45 +02:00 committed by GitHub
parent d85a4e8098
commit 6d359afde4
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2 changed files with 4 additions and 7 deletions

View File

@ -3519,7 +3519,6 @@ void riscv_info_init(struct target *target, riscv_info_t *r)
{
memset(r, 0, sizeof(*r));
r->dtm_version = 1;
r->registers_initialized = false;
r->current_hartid = target->coreid;
r->version_specific = NULL;
@ -3664,7 +3663,10 @@ int riscv_set_current_hartid(struct target *target, int hartid)
void riscv_invalidate_register_cache(struct target *target)
{
RISCV_INFO(r);
/* Do not invalidate the register cache if it is not yet set up
* (e.g. when the target failed to get examined). */
if (!target->reg_cache)
return;
LOG_DEBUG("[%d]", target->coreid);
register_cache_invalidate(target->reg_cache);
@ -3672,8 +3674,6 @@ void riscv_invalidate_register_cache(struct target *target)
struct reg *reg = &target->reg_cache->reg_list[i];
reg->valid = false;
}
r->registers_initialized = true;
}
int riscv_current_hartid(const struct target *target)

View File

@ -131,9 +131,6 @@ typedef struct {
/* The number of entries in the debug buffer. */
int debug_buffer_size;
/* This avoids invalidating the register cache too often. */
bool registers_initialized;
/* This hart contains an implicit ebreak at the end of the program buffer. */
bool impebreak;