cortex a8: added timeout handling
Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
This commit is contained in:
parent
6a237c23c1
commit
6c573df11d
|
@ -136,6 +136,7 @@ static int cortex_a8_exec_opcode(struct target *target,
|
||||||
LOG_DEBUG("exec opcode 0x%08" PRIx32, opcode);
|
LOG_DEBUG("exec opcode 0x%08" PRIx32, opcode);
|
||||||
|
|
||||||
/* Wait for InstrCompl bit to be set */
|
/* Wait for InstrCompl bit to be set */
|
||||||
|
long long then = timeval_ms();
|
||||||
while ((dscr & DSCR_INSTR_COMP) == 0)
|
while ((dscr & DSCR_INSTR_COMP) == 0)
|
||||||
{
|
{
|
||||||
retval = mem_ap_read_atomic_u32(swjdp,
|
retval = mem_ap_read_atomic_u32(swjdp,
|
||||||
|
@ -145,12 +146,18 @@ static int cortex_a8_exec_opcode(struct target *target,
|
||||||
LOG_ERROR("Could not read DSCR register, opcode = 0x%08" PRIx32, opcode);
|
LOG_ERROR("Could not read DSCR register, opcode = 0x%08" PRIx32, opcode);
|
||||||
return retval;
|
return retval;
|
||||||
}
|
}
|
||||||
|
if (timeval_ms() > then + 1000)
|
||||||
|
{
|
||||||
|
LOG_ERROR("Timeout waiting for cortex_a8_exec_opcode");
|
||||||
|
return ERROR_FAIL;
|
||||||
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
retval = mem_ap_write_u32(swjdp, armv7a->debug_base + CPUDBG_ITR, opcode);
|
retval = mem_ap_write_u32(swjdp, armv7a->debug_base + CPUDBG_ITR, opcode);
|
||||||
if (retval != ERROR_OK)
|
if (retval != ERROR_OK)
|
||||||
return retval;
|
return retval;
|
||||||
|
|
||||||
|
then = timeval_ms();
|
||||||
do
|
do
|
||||||
{
|
{
|
||||||
retval = mem_ap_read_atomic_u32(swjdp,
|
retval = mem_ap_read_atomic_u32(swjdp,
|
||||||
|
@ -160,6 +167,11 @@ static int cortex_a8_exec_opcode(struct target *target,
|
||||||
LOG_ERROR("Could not read DSCR register");
|
LOG_ERROR("Could not read DSCR register");
|
||||||
return retval;
|
return retval;
|
||||||
}
|
}
|
||||||
|
if (timeval_ms() > then + 1000)
|
||||||
|
{
|
||||||
|
LOG_ERROR("Timeout waiting for cortex_a8_exec_opcode");
|
||||||
|
return ERROR_FAIL;
|
||||||
|
}
|
||||||
}
|
}
|
||||||
while ((dscr & DSCR_INSTR_COMP) == 0); /* Wait for InstrCompl bit to be set */
|
while ((dscr & DSCR_INSTR_COMP) == 0); /* Wait for InstrCompl bit to be set */
|
||||||
|
|
||||||
|
@ -248,12 +260,18 @@ static int cortex_a8_dap_read_coreregister_u32(struct target *target,
|
||||||
}
|
}
|
||||||
|
|
||||||
/* Wait for DTRRXfull then read DTRRTX */
|
/* Wait for DTRRXfull then read DTRRTX */
|
||||||
|
long long then = timeval_ms();
|
||||||
while ((dscr & DSCR_DTR_TX_FULL) == 0)
|
while ((dscr & DSCR_DTR_TX_FULL) == 0)
|
||||||
{
|
{
|
||||||
retval = mem_ap_read_atomic_u32(swjdp,
|
retval = mem_ap_read_atomic_u32(swjdp,
|
||||||
armv7a->debug_base + CPUDBG_DSCR, &dscr);
|
armv7a->debug_base + CPUDBG_DSCR, &dscr);
|
||||||
if (retval != ERROR_OK)
|
if (retval != ERROR_OK)
|
||||||
return retval;
|
return retval;
|
||||||
|
if (timeval_ms() > then + 1000)
|
||||||
|
{
|
||||||
|
LOG_ERROR("Timeout waiting for cortex_a8_exec_opcode");
|
||||||
|
return ERROR_FAIL;
|
||||||
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
retval = mem_ap_read_atomic_u32(swjdp,
|
retval = mem_ap_read_atomic_u32(swjdp,
|
||||||
|
@ -394,12 +412,18 @@ static int cortex_a8_read_dcc(struct cortex_a8_common *a8, uint32_t *data,
|
||||||
dscr = *dscr_p;
|
dscr = *dscr_p;
|
||||||
|
|
||||||
/* Wait for DTRRXfull */
|
/* Wait for DTRRXfull */
|
||||||
|
long long then = timeval_ms();
|
||||||
while ((dscr & DSCR_DTR_TX_FULL) == 0) {
|
while ((dscr & DSCR_DTR_TX_FULL) == 0) {
|
||||||
retval = mem_ap_read_atomic_u32(swjdp,
|
retval = mem_ap_read_atomic_u32(swjdp,
|
||||||
a8->armv7a_common.debug_base + CPUDBG_DSCR,
|
a8->armv7a_common.debug_base + CPUDBG_DSCR,
|
||||||
&dscr);
|
&dscr);
|
||||||
if (retval != ERROR_OK)
|
if (retval != ERROR_OK)
|
||||||
return retval;
|
return retval;
|
||||||
|
if (timeval_ms() > then + 1000)
|
||||||
|
{
|
||||||
|
LOG_ERROR("Timeout waiting for read dcc");
|
||||||
|
return ERROR_FAIL;
|
||||||
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
retval = mem_ap_read_atomic_u32(swjdp,
|
retval = mem_ap_read_atomic_u32(swjdp,
|
||||||
|
@ -1086,8 +1110,6 @@ static int cortex_a8_step(struct target *target, int current, uint32_t address,
|
||||||
struct reg *r;
|
struct reg *r;
|
||||||
int retval;
|
int retval;
|
||||||
|
|
||||||
int timeout = 100;
|
|
||||||
|
|
||||||
if (target->state != TARGET_HALTED)
|
if (target->state != TARGET_HALTED)
|
||||||
{
|
{
|
||||||
LOG_WARNING("target not halted");
|
LOG_WARNING("target not halted");
|
||||||
|
@ -1132,12 +1154,13 @@ static int cortex_a8_step(struct target *target, int current, uint32_t address,
|
||||||
if (retval != ERROR_OK)
|
if (retval != ERROR_OK)
|
||||||
return retval;
|
return retval;
|
||||||
|
|
||||||
|
long long then = timeval_ms();
|
||||||
while (target->state != TARGET_HALTED)
|
while (target->state != TARGET_HALTED)
|
||||||
{
|
{
|
||||||
retval = cortex_a8_poll(target);
|
retval = cortex_a8_poll(target);
|
||||||
if (retval != ERROR_OK)
|
if (retval != ERROR_OK)
|
||||||
return retval;
|
return retval;
|
||||||
if (--timeout == 0)
|
if (timeval_ms() > then + 1000)
|
||||||
{
|
{
|
||||||
LOG_ERROR("timeout waiting for target halt");
|
LOG_ERROR("timeout waiting for target halt");
|
||||||
return ERROR_FAIL;
|
return ERROR_FAIL;
|
||||||
|
@ -1145,8 +1168,8 @@ static int cortex_a8_step(struct target *target, int current, uint32_t address,
|
||||||
}
|
}
|
||||||
|
|
||||||
cortex_a8_unset_breakpoint(target, &stepbreakpoint);
|
cortex_a8_unset_breakpoint(target, &stepbreakpoint);
|
||||||
if (timeout > 0)
|
|
||||||
target->debug_reason = DBG_REASON_BREAKPOINT;
|
target->debug_reason = DBG_REASON_BREAKPOINT;
|
||||||
|
|
||||||
if (breakpoint)
|
if (breakpoint)
|
||||||
cortex_a8_set_breakpoint(target, breakpoint, 0);
|
cortex_a8_set_breakpoint(target, breakpoint, 0);
|
||||||
|
|
Loading…
Reference in New Issue