diff --git a/src/target/riscv/encoding.h b/src/target/riscv/encoding.h index 81018ece2..cdbc70cba 100644 --- a/src/target/riscv/encoding.h +++ b/src/target/riscv/encoding.h @@ -2931,6 +2931,7 @@ #define CSR_MISELECT 0x350 #define CSR_MIREG 0x351 #define CSR_MTOPEI 0x35c +#define CSR_WORDGUARD 0x390 #define CSR_PMPCFG0 0x3a0 #define CSR_PMPCFG1 0x3a1 #define CSR_PMPCFG2 0x3a2 @@ -3213,26 +3214,86 @@ #define CSR_MHPMCOUNTER31H 0xb9f /* === TEE CSR Registers === */ -#define CSR_SPMPCFG0 0x1a0 -#define CSR_SPMPCFG1 0x1a1 -#define CSR_SPMPCFG2 0x1a2 -#define CSR_SPMPCFG3 0x1a3 -#define CSR_SPMPADDR0 0x1b0 -#define CSR_SPMPADDR1 0x1b1 -#define CSR_SPMPADDR2 0x1b2 -#define CSR_SPMPADDR3 0x1b3 -#define CSR_SPMPADDR4 0x1b4 -#define CSR_SPMPADDR5 0x1b5 -#define CSR_SPMPADDR6 0x1b6 -#define CSR_SPMPADDR7 0x1b7 -#define CSR_SPMPADDR8 0x1b8 -#define CSR_SPMPADDR9 0x1b9 -#define CSR_SPMPADDR10 0x1ba -#define CSR_SPMPADDR11 0x1bb -#define CSR_SPMPADDR12 0x1bc -#define CSR_SPMPADDR13 0x1bd -#define CSR_SPMPADDR14 0x1be -#define CSR_SPMPADDR15 0x1bf +#define CSR_SMPUCFG0 0x1a0 +#define CSR_SMPUCFG1 0x1a1 +#define CSR_SMPUCFG2 0x1a2 +#define CSR_SMPUCFG3 0x1a3 +#define CSR_SMPUCFG4 0x1a4 +#define CSR_SMPUCFG5 0x1a5 +#define CSR_SMPUCFG6 0x1a6 +#define CSR_SMPUCFG7 0x1a7 +#define CSR_SMPUCFG8 0x1a8 +#define CSR_SMPUCFG9 0x1a9 +#define CSR_SMPUCFG10 0x1aa +#define CSR_SMPUCFG11 0x1ab +#define CSR_SMPUCFG12 0x1ac +#define CSR_SMPUCFG13 0x1ad +#define CSR_SMPUCFG14 0x1ae +#define CSR_SMPUCFG15 0x1af +#define CSR_SMPUADDR0 0x1b0 +#define CSR_SMPUADDR1 0x1b1 +#define CSR_SMPUADDR2 0x1b2 +#define CSR_SMPUADDR3 0x1b3 +#define CSR_SMPUADDR4 0x1b4 +#define CSR_SMPUADDR5 0x1b5 +#define CSR_SMPUADDR6 0x1b6 +#define CSR_SMPUADDR7 0x1b7 +#define CSR_SMPUADDR8 0x1b8 +#define CSR_SMPUADDR9 0x1b9 +#define CSR_SMPUADDR10 0x1ba +#define CSR_SMPUADDR11 0x1bb +#define CSR_SMPUADDR12 0x1bc +#define CSR_SMPUADDR13 0x1bd +#define CSR_SMPUADDR14 0x1be +#define CSR_SMPUADDR15 0x1bf +#define CSR_SMPUADDR16 0x1c0 +#define CSR_SMPUADDR17 0x1c1 +#define CSR_SMPUADDR18 0x1c2 +#define CSR_SMPUADDR19 0x1c3 +#define CSR_SMPUADDR20 0x1c4 +#define CSR_SMPUADDR21 0x1c5 +#define CSR_SMPUADDR22 0x1c6 +#define CSR_SMPUADDR23 0x1c7 +#define CSR_SMPUADDR24 0x1c8 +#define CSR_SMPUADDR25 0x1c9 +#define CSR_SMPUADDR26 0x1ca +#define CSR_SMPUADDR27 0x1cb +#define CSR_SMPUADDR28 0x1cc +#define CSR_SMPUADDR29 0x1cd +#define CSR_SMPUADDR30 0x1ce +#define CSR_SMPUADDR31 0x1cf +#define CSR_SMPUADDR32 0x1d0 +#define CSR_SMPUADDR33 0x1d1 +#define CSR_SMPUADDR34 0x1d2 +#define CSR_SMPUADDR35 0x1d3 +#define CSR_SMPUADDR36 0x1d4 +#define CSR_SMPUADDR37 0x1d5 +#define CSR_SMPUADDR38 0x1d6 +#define CSR_SMPUADDR39 0x1d7 +#define CSR_SMPUADDR40 0x1d8 +#define CSR_SMPUADDR41 0x1d9 +#define CSR_SMPUADDR42 0x1da +#define CSR_SMPUADDR43 0x1db +#define CSR_SMPUADDR44 0x1dc +#define CSR_SMPUADDR45 0x1dd +#define CSR_SMPUADDR46 0x1de +#define CSR_SMPUADDR47 0x1df +#define CSR_SMPUADDR48 0x1e0 +#define CSR_SMPUADDR49 0x1e1 +#define CSR_SMPUADDR50 0x1e2 +#define CSR_SMPUADDR51 0x1e3 +#define CSR_SMPUADDR52 0x1e4 +#define CSR_SMPUADDR53 0x1e5 +#define CSR_SMPUADDR54 0x1e6 +#define CSR_SMPUADDR55 0x1e7 +#define CSR_SMPUADDR56 0x1e8 +#define CSR_SMPUADDR57 0x1e9 +#define CSR_SMPUADDR58 0x1ea +#define CSR_SMPUADDR59 0x1eb +#define CSR_SMPUADDR60 0x1ec +#define CSR_SMPUADDR61 0x1ed +#define CSR_SMPUADDR62 0x1ee +#define CSR_SMPUADDR63 0x1ef #define CSR_SMPUSWITCH0 0x170 #define CSR_SMPUSWITCH1 0x171 @@ -3273,6 +3334,12 @@ #define CSR_MATTRI3_MASK 0x7fc #define CSR_MATTRI4_BASE 0x7fd #define CSR_MATTRI4_MASK 0x7fe +#define CSR_MATTRI5_BASE 0xbe0 +#define CSR_MATTRI5_MASK 0xbe1 +#define CSR_MATTRI6_BASE 0xbe2 +#define CSR_MATTRI6_MASK 0xbe3 +#define CSR_MATTRI7_BASE 0xbe4 +#define CSR_MATTRI7_MASK 0xbe5 #define CSR_MIRGB_INFO 0x7f7 #define CSR_SLEEPVALUE 0x811 #define CSR_TXEVT 0x812 @@ -3302,12 +3369,6 @@ #define CSR_MTIMECMP 0xbd9 #define CSR_MTIME 0xbda #define CSR_MSTOP 0xbdb -#define CSR_MATTRI5_BASE 0xbe0 -#define CSR_MATTRI5_MASK 0xbe1 -#define CSR_MATTRI6_BASE 0xbe2 -#define CSR_MATTRI6_MASK 0xbe3 -#define CSR_MATTRI7_BASE 0xbe4 -#define CSR_MATTRI7_MASK 0xbe5 /* === P-Extension Registers === */ #define CSR_UCODE 0x801 @@ -4824,6 +4885,7 @@ DECLARE_CSR(mtval2, CSR_MTVAL2) DECLARE_CSR(miselect, CSR_MISELECT) DECLARE_CSR(mireg, CSR_MIREG) DECLARE_CSR(mtopei, CSR_MTOPEI) +DECLARE_CSR(wordguard, CSR_WORDGUARD) DECLARE_CSR(pmpcfg0, CSR_PMPCFG0) DECLARE_CSR(pmpcfg1, CSR_PMPCFG1) DECLARE_CSR(pmpcfg2, CSR_PMPCFG2) @@ -5106,26 +5168,86 @@ DECLARE_CSR(mhpmcounter30h, CSR_MHPMCOUNTER30H) DECLARE_CSR(mhpmcounter31h, CSR_MHPMCOUNTER31H) /* === TEE CSR Registers === */ -DECLARE_CSR(spmpcfg0, CSR_SPMPCFG0) -DECLARE_CSR(spmpcfg1, CSR_SPMPCFG1) -DECLARE_CSR(spmpcfg2, CSR_SPMPCFG2) -DECLARE_CSR(spmpcfg3, CSR_SPMPCFG3) -DECLARE_CSR(spmpaddr0, CSR_SPMPADDR0) -DECLARE_CSR(spmpaddr1, CSR_SPMPADDR1) -DECLARE_CSR(spmpaddr2, CSR_SPMPADDR2) -DECLARE_CSR(spmpaddr3, CSR_SPMPADDR3) -DECLARE_CSR(spmpaddr4, CSR_SPMPADDR4) -DECLARE_CSR(spmpaddr5, CSR_SPMPADDR5) -DECLARE_CSR(spmpaddr6, CSR_SPMPADDR6) -DECLARE_CSR(spmpaddr7, CSR_SPMPADDR7) -DECLARE_CSR(spmpaddr8, CSR_SPMPADDR8) -DECLARE_CSR(spmpaddr9, CSR_SPMPADDR9) -DECLARE_CSR(spmpaddr10, CSR_SPMPADDR10) -DECLARE_CSR(spmpaddr11, CSR_SPMPADDR11) -DECLARE_CSR(spmpaddr12, CSR_SPMPADDR12) -DECLARE_CSR(spmpaddr13, CSR_SPMPADDR13) -DECLARE_CSR(spmpaddr14, CSR_SPMPADDR14) -DECLARE_CSR(spmpaddr15, CSR_SPMPADDR15) +DECLARE_CSR(smpucfg0, CSR_SMPUCFG0) +DECLARE_CSR(smpucfg1, CSR_SMPUCFG1) +DECLARE_CSR(smpucfg2, CSR_SMPUCFG2) +DECLARE_CSR(smpucfg3, CSR_SMPUCFG3) +DECLARE_CSR(smpucfg4, CSR_SMPUCFG4) +DECLARE_CSR(smpucfg5, CSR_SMPUCFG5) +DECLARE_CSR(smpucfg6, CSR_SMPUCFG6) +DECLARE_CSR(smpucfg7, CSR_SMPUCFG7) +DECLARE_CSR(smpucfg8, CSR_SMPUCFG8) +DECLARE_CSR(smpucfg9, CSR_SMPUCFG9) +DECLARE_CSR(smpucfg10, CSR_SMPUCFG10) +DECLARE_CSR(smpucfg11, CSR_SMPUCFG11) +DECLARE_CSR(smpucfg12, CSR_SMPUCFG12) +DECLARE_CSR(smpucfg13, CSR_SMPUCFG13) +DECLARE_CSR(smpucfg14, CSR_SMPUCFG14) +DECLARE_CSR(smpucfg15, CSR_SMPUCFG15) +DECLARE_CSR(smpuaddr0, CSR_SMPUADDR0) +DECLARE_CSR(smpuaddr1, CSR_SMPUADDR1) +DECLARE_CSR(smpuaddr2, CSR_SMPUADDR2) +DECLARE_CSR(smpuaddr3, CSR_SMPUADDR3) +DECLARE_CSR(smpuaddr4, CSR_SMPUADDR4) +DECLARE_CSR(smpuaddr5, CSR_SMPUADDR5) +DECLARE_CSR(smpuaddr6, CSR_SMPUADDR6) +DECLARE_CSR(smpuaddr7, CSR_SMPUADDR7) +DECLARE_CSR(smpuaddr8, CSR_SMPUADDR8) +DECLARE_CSR(smpuaddr9, CSR_SMPUADDR9) +DECLARE_CSR(smpuaddr10, CSR_SMPUADDR10) +DECLARE_CSR(smpuaddr11, CSR_SMPUADDR11) +DECLARE_CSR(smpuaddr12, CSR_SMPUADDR12) +DECLARE_CSR(smpuaddr13, CSR_SMPUADDR13) +DECLARE_CSR(smpuaddr14, CSR_SMPUADDR14) +DECLARE_CSR(smpuaddr15, CSR_SMPUADDR15) +DECLARE_CSR(smpuaddr16, CSR_SMPUADDR16) +DECLARE_CSR(smpuaddr17, CSR_SMPUADDR17) +DECLARE_CSR(smpuaddr18, CSR_SMPUADDR18) +DECLARE_CSR(smpuaddr19, CSR_SMPUADDR19) +DECLARE_CSR(smpuaddr20, CSR_SMPUADDR20) +DECLARE_CSR(smpuaddr21, CSR_SMPUADDR21) +DECLARE_CSR(smpuaddr22, CSR_SMPUADDR22) +DECLARE_CSR(smpuaddr23, CSR_SMPUADDR23) +DECLARE_CSR(smpuaddr24, CSR_SMPUADDR24) +DECLARE_CSR(smpuaddr25, CSR_SMPUADDR25) +DECLARE_CSR(smpuaddr26, CSR_SMPUADDR26) +DECLARE_CSR(smpuaddr27, CSR_SMPUADDR27) +DECLARE_CSR(smpuaddr28, CSR_SMPUADDR28) +DECLARE_CSR(smpuaddr29, CSR_SMPUADDR29) +DECLARE_CSR(smpuaddr30, CSR_SMPUADDR30) +DECLARE_CSR(smpuaddr31, CSR_SMPUADDR31) +DECLARE_CSR(smpuaddr32, CSR_SMPUADDR32) +DECLARE_CSR(smpuaddr33, CSR_SMPUADDR33) +DECLARE_CSR(smpuaddr34, CSR_SMPUADDR34) +DECLARE_CSR(smpuaddr35, CSR_SMPUADDR35) +DECLARE_CSR(smpuaddr36, CSR_SMPUADDR36) +DECLARE_CSR(smpuaddr37, CSR_SMPUADDR37) +DECLARE_CSR(smpuaddr38, CSR_SMPUADDR38) +DECLARE_CSR(smpuaddr39, CSR_SMPUADDR39) +DECLARE_CSR(smpuaddr40, CSR_SMPUADDR40) +DECLARE_CSR(smpuaddr41, CSR_SMPUADDR41) +DECLARE_CSR(smpuaddr42, CSR_SMPUADDR42) +DECLARE_CSR(smpuaddr43, CSR_SMPUADDR43) +DECLARE_CSR(smpuaddr44, CSR_SMPUADDR44) +DECLARE_CSR(smpuaddr45, CSR_SMPUADDR45) +DECLARE_CSR(smpuaddr46, CSR_SMPUADDR46) +DECLARE_CSR(smpuaddr47, CSR_SMPUADDR47) +DECLARE_CSR(smpuaddr48, CSR_SMPUADDR48) +DECLARE_CSR(smpuaddr49, CSR_SMPUADDR49) +DECLARE_CSR(smpuaddr50, CSR_SMPUADDR50) +DECLARE_CSR(smpuaddr51, CSR_SMPUADDR51) +DECLARE_CSR(smpuaddr52, CSR_SMPUADDR52) +DECLARE_CSR(smpuaddr53, CSR_SMPUADDR53) +DECLARE_CSR(smpuaddr54, CSR_SMPUADDR54) +DECLARE_CSR(smpuaddr55, CSR_SMPUADDR55) +DECLARE_CSR(smpuaddr56, CSR_SMPUADDR56) +DECLARE_CSR(smpuaddr57, CSR_SMPUADDR57) +DECLARE_CSR(smpuaddr58, CSR_SMPUADDR58) +DECLARE_CSR(smpuaddr59, CSR_SMPUADDR59) +DECLARE_CSR(smpuaddr60, CSR_SMPUADDR60) +DECLARE_CSR(smpuaddr61, CSR_SMPUADDR61) +DECLARE_CSR(smpuaddr62, CSR_SMPUADDR62) +DECLARE_CSR(smpuaddr63, CSR_SMPUADDR63) DECLARE_CSR(smpuswitch0, CSR_SMPUSWITCH0) DECLARE_CSR(smpuswitch1, CSR_SMPUSWITCH1) @@ -5166,6 +5288,12 @@ DECLARE_CSR(mattri3_base, CSR_MATTRI3_BASE) DECLARE_CSR(mattri3_mask, CSR_MATTRI3_MASK) DECLARE_CSR(mattri4_base, CSR_MATTRI4_BASE) DECLARE_CSR(mattri4_mask, CSR_MATTRI4_MASK) +DECLARE_CSR(mattri5_base, CSR_MATTRI5_BASE) +DECLARE_CSR(mattri5_mask, CSR_MATTRI5_MASK) +DECLARE_CSR(mattri6_base, CSR_MATTRI6_BASE) +DECLARE_CSR(mattri6_mask, CSR_MATTRI6_MASK) +DECLARE_CSR(mattri7_base, CSR_MATTRI7_BASE) +DECLARE_CSR(mattri7_mask, CSR_MATTRI7_MASK) DECLARE_CSR(mirgb_info, CSR_MIRGB_INFO) DECLARE_CSR(sleepvalue, CSR_SLEEPVALUE) DECLARE_CSR(txevt, CSR_TXEVT) @@ -5195,12 +5323,6 @@ DECLARE_CSR(msip, CSR_MSIP) DECLARE_CSR(mtimecmp, CSR_MTIMECMP) DECLARE_CSR(mtime, CSR_MTIME) DECLARE_CSR(mstop, CSR_MSTOP) -DECLARE_CSR(mattri5_base, CSR_MATTRI5_BASE) -DECLARE_CSR(mattri5_mask, CSR_MATTRI5_MASK) -DECLARE_CSR(mattri6_base, CSR_MATTRI6_BASE) -DECLARE_CSR(mattri6_mask, CSR_MATTRI6_MASK) -DECLARE_CSR(mattri7_base, CSR_MATTRI7_BASE) -DECLARE_CSR(mattri7_mask, CSR_MATTRI7_MASK) /* === P-Extension Registers === */ DECLARE_CSR(ucode, CSR_UCODE)