interesting
/
riscv-openocd
mirror of https://github.com/riscv/riscv-openocd.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

aarch64: simplify armv8_set_cpsr() 

Translate from cpsr value to "enum arm_mode" by shifting up 4 bits and
filling the lowest nibble with 0xF.

Change-Id: Ic32186104b0c29578c4f6f99e04840ab88a0017b
Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
This commit is contained in:
Matthias Welwarsky 2016-10-06 16:11:19 +02:00
parent 2b56f4f656
commit 675b0170f2
1 changed files with 3 additions and 29 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

32
src/target/armv8.c
View File

@ -282,36 +282,10 @@ void armv8_set_cpsr(struct arm *arm, uint32_t cpsr)
} }
} }
arm->core_state = state; arm->core_state = state;
if (arm->core_state == ARM_STATE_AARCH64) { if (arm->core_state == ARM_STATE_AARCH64)
switch (mode) { arm->core_mode = (mode << 4) | 0xf;
case SYSTEM_AAR64_MODE_EL0t: else
arm->core_mode = ARMV8_64_EL0T;
break;
case SYSTEM_AAR64_MODE_EL1t:
arm->core_mode = ARMV8_64_EL0T;
break;
case SYSTEM_AAR64_MODE_EL1h:
arm->core_mode = ARMV8_64_EL1H;
break;
case SYSTEM_AAR64_MODE_EL2t:
arm->core_mode = ARMV8_64_EL2T;
break;
case SYSTEM_AAR64_MODE_EL2h:
arm->core_mode = ARMV8_64_EL2H;
break;
case SYSTEM_AAR64_MODE_EL3t:
arm->core_mode = ARMV8_64_EL3T;
break;
case SYSTEM_AAR64_MODE_EL3h:
arm->core_mode = ARMV8_64_EL3H;
break;
default:
LOG_DEBUG("unknow mode 0x%x", (unsigned) (mode));
break;
}
} else {
arm->core_mode = mode; arm->core_mode = mode;
}
LOG_DEBUG("set CPSR %#8.8x: %s mode, %s state", (unsigned) cpsr, LOG_DEBUG("set CPSR %#8.8x: %s mode, %s state", (unsigned) cpsr,
armv8_mode_name(arm->core_mode), armv8_mode_name(arm->core_mode),