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Minimally describe the BSCAN tunnel interface. (#533) 

Change-Id: Ifffa815e6a4a73c551eddf28927583befa743641
Signed-off-by: Tim Newsome <tim@sifive.com>
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Tim Newsome 2020-09-21 14:10:27 -07:00 committed by GitHub
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doc/openocd.texi
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@ -9729,8 +9729,23 @@ and DBUS registers, respectively.
@end deffn
@deffn Command {riscv use_bscan_tunnel} value
Enable or disable use of a BSCAN tunnel to reach DM. Supply the width of
the DM transport TAP's instruction register to enable. Supply a value of 0 to disable.
Enable or disable use of a BSCAN tunnel to reach the Debug Module. Supply the
width of the DM transport TAP's instruction register to enable. Supply a
value of 0 to disable.
This BSCAN tunnel interface is specific to SiFive IP. Anybody may implement
it, but currently there is no good documentation on it. In a nutshell, this
feature scans USER4 into a Xilinx TAP to select the tunnel device (assuming
hardware is present and it is hooked up to the Xilinx USER4 IR) and
encapsulates a tunneled scan directive into a DR scan into the Xilinx TAP. A
tunneled DR scan consists of:
@enumerate
@item 1 bit that selects IR when 0, or DR when 1
@item 7 bits that encode the width of the desired tunneled scan
@item A width+1 stream of bits for the tunneled TDI. The plus one is because there is a one-clock skew between TDI of Xilinx chain and TDO from tunneled chain.
@item 3 bits of zero that the tunnel uses to go back to idle state.
@end enumerate
@end deffn
@deffn Command {riscv set_ebreakm} on|off