ARM: core DPM support for watchpoints
This is a NOP unless the underlying core exposes two new methods, and neither of the two cores using this (ARM11xx, Cortex-A8) do so yet. This patch only updates those cores so they pass a flag saying whether or not to update breakpoint and watchpoint status before resuming; and removing some now-needless anti-segfault code from ARM11. Cortex-A8 didn't have that code ... yes, it segfaulted when setting watchpoints. NOTE: this uses a slightly different strategy for setting/clearing breakpoints than the ARM7/ARM9/etc code uses. It leaves them alone unless it's *got* to change something, to speed halt/resume cycles (including single stepping). ALSO NOTE: this under-delivers for Cortex-A8, where regions with size up to 2 GBytes can be watched ... it handles watchpoints which ARM11 can also handle (size 1/2/4 bytes). Should get fixed later. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
This commit is contained in:
David Brownell
parent
1c7d3d200c
commit
66ca84b581
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@ -293,12 +293,11 @@ static int arm11_on_enter_debug_state(struct arm11_common *arm11)
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return ERROR_OK;
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}
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/** Restore processor state
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*
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* This is called in preparation for the RESTART function.
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*
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*/
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static int arm11_leave_debug_state(struct arm11_common *arm11)
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/**
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* Restore processor state. This is called in preparation for
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* the RESTART function.
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*/
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static int arm11_leave_debug_state(struct arm11_common *arm11, bool bpwp)
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{
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int retval;
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@ -354,7 +353,7 @@ static int arm11_leave_debug_state(struct arm11_common *arm11)
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/* restore CPSR, PC, and R0 ... after flushing any modified
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* registers.
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*/
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retval = arm_dpm_write_dirty_registers(&arm11->dpm);
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retval = arm_dpm_write_dirty_registers(&arm11->dpm, bpwp);
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register_cache_invalidate(arm11->arm.core_cache);
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@ -598,7 +597,7 @@ static int arm11_resume(struct target *target, int current,
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arm11_sc7_set_vcr(arm11, arm11_vcr);
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}
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arm11_leave_debug_state(arm11);
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arm11_leave_debug_state(arm11, handle_breakpoints);
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arm11_add_IR(arm11, ARM11_RESTART, TAP_IDLE);
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@ -762,7 +761,7 @@ static int arm11_step(struct target *target, int current,
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R(DSCR) |= ARM11_DSCR_INTERRUPTS_DISABLE;
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CHECK_RETVAL(arm11_leave_debug_state(arm11));
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CHECK_RETVAL(arm11_leave_debug_state(arm11, handle_breakpoints));
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arm11_add_IR(arm11, ARM11_RESTART, TAP_IDLE);
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@ -1203,22 +1202,6 @@ static int arm11_remove_breakpoint(struct target *target,
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return ERROR_OK;
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}
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static int arm11_add_watchpoint(struct target *target,
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struct watchpoint *watchpoint)
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{
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LOG_WARNING("Not implemented: %s", __func__);
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return ERROR_FAIL;
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}
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static int arm11_remove_watchpoint(struct target *target,
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struct watchpoint *watchpoint)
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{
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LOG_WARNING("Not implemented: %s", __func__);
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return ERROR_FAIL;
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}
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static int arm11_target_create(struct target *target, Jim_Interp *interp)
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{
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struct arm11_common *arm11;
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@ -1605,8 +1588,6 @@ struct target_type arm11_target = {
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.add_breakpoint = arm11_add_breakpoint,
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.remove_breakpoint = arm11_remove_breakpoint,
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.add_watchpoint = arm11_add_watchpoint,
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.remove_watchpoint = arm11_remove_watchpoint,
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.run_algorithm = armv4_5_run_algorithm,
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@ -25,6 +25,8 @@
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#include "arm_dpm.h"
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#include "jtag.h"
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#include "register.h"
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#include "breakpoints.h"
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#include "target_type.h"
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/**
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@ -34,6 +36,8 @@
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* implementation differences between cores like ARM1136 and Cortex-A8.
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*/
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/*----------------------------------------------------------------------*/
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/*
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* Coprocessor support
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*/
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@ -85,6 +89,8 @@ static int dpm_mcr(struct target *target, int cpnum,
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return retval;
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}
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/*----------------------------------------------------------------------*/
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/*
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* Register access utilities
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*/
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@ -178,7 +184,7 @@ static int dpm_write_reg(struct arm_dpm *dpm, struct reg *r, unsigned regnum)
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switch (regnum) {
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case 0 ... 14:
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/* load register from DCC: "MCR p14, 0, Rnum, c0, c5, 0" */
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/* load register from DCC: "MRC p14, 0, Rnum, c0, c5, 0" */
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retval = dpm->instr_write_data_dcc(dpm,
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ARMV4_5_MRC(14, 0, regnum, 0, 5, 0),
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value);
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@ -256,6 +262,11 @@ int arm_dpm_read_current_registers(struct arm_dpm *dpm)
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/* NOTE: SPSR ignored (if it's even relevant). */
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/* REVISIT the debugger can trigger various exceptions. See the
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* ARMv7A architecture spec, section C5.7, for more info about
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* what defenses are needed; v6 debug has the most issues.
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*/
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fail:
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/* (void) */ dpm->finish(dpm);
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return retval;
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@ -264,8 +275,11 @@ fail:
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/**
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* Writes all modified core registers for all processor modes. In normal
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* operation this is called on exit from halting debug state.
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*
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* @param bpwp: true ensures breakpoints and watchpoints are set,
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* false ensures they are cleared
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*/
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int arm_dpm_write_dirty_registers(struct arm_dpm *dpm)
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int arm_dpm_write_dirty_registers(struct arm_dpm *dpm, bool bpwp)
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{
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struct arm *arm = dpm->arm;
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struct reg_cache *cache = arm->core_cache;
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@ -276,6 +290,53 @@ int arm_dpm_write_dirty_registers(struct arm_dpm *dpm)
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if (retval != ERROR_OK)
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goto done;
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/* enable/disable watchpoints */
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for (unsigned i = 0; i < dpm->nwp; i++) {
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struct dpm_wp *dwp = dpm->dwp + i;
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struct watchpoint *wp = dwp->wp;
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bool disable;
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/* Avoid needless I/O ... leave watchpoints alone
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* unless they're removed, or need updating because
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* of single-stepping or running debugger code.
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*/
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if (!wp) {
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if (!dwp->dirty)
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continue;
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dwp->dirty = false;
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/* removed or startup; we must disable it */
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disable = true;
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} else if (bpwp) {
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if (!dwp->dirty)
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continue;
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/* disabled, but we must set it */
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dwp->dirty = disable = false;
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wp->set = true;
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} else {
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if (!wp->set)
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continue;
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/* set, but we must temporarily disable it */
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dwp->dirty = disable = true;
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wp->set = false;
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}
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if (disable)
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retval = dpm->bpwp_disable(dpm, 16 + i);
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else
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retval = dpm->bpwp_enable(dpm, 16 + i,
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wp->address, dwp->control);
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if (retval != ERROR_OK)
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LOG_ERROR("%s: can't %s HW watchpoint %d",
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target_name(arm->target),
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disable ? "disable" : "enable",
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i);
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}
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/* NOTE: writes to breakpoint and watchpoint registers might
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* be queued, and need (efficient/batched) flushing later.
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*/
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/* Scan the registers until we find one that's both dirty and
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* eligible for flushing. Flush that and everything else that
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* shares the same core mode setting. Typically this won't
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@ -399,6 +460,13 @@ static enum armv4_5_mode dpm_mapmode(struct arm *arm,
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return ARMV4_5_MODE_ANY;
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}
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/*
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* Standard ARM register accessors ... there are three methods
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* in "struct arm", to support individual read/write and bulk read
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* of registers.
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*/
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static int arm_dpm_read_core_reg(struct target *target, struct reg *r,
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int regnum, enum armv4_5_mode mode)
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{
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@ -544,9 +612,141 @@ done:
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return retval;
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}
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/*----------------------------------------------------------------------*/
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/*
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* Breakpoint and Watchpoint support.
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*
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* Hardware {break,watch}points are usually left active, to minimize
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* debug entry/exit costs. When they are set or cleared, it's done in
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* batches. Also, DPM-conformant hardware can update debug registers
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* regardless of whether the CPU is running or halted ... though that
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* fact isn't currently leveraged.
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*/
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static int dpm_watchpoint_setup(struct arm_dpm *dpm, unsigned index,
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struct watchpoint *wp)
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{
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uint32_t addr = wp->address;
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uint32_t control;
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/* this hardware doesn't support data value matching or masking */
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if (wp->value || wp->mask != ~(uint32_t)0) {
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LOG_DEBUG("watchpoint values and masking not supported");
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return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
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}
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control = (1 << 0) /* enable */
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| (3 << 1); /* both user and privileged access */
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switch (wp->rw) {
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case WPT_READ:
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control |= 1 << 3;
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break;
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case WPT_WRITE:
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control |= 2 << 3;
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break;
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case WPT_ACCESS:
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control |= 3 << 3;
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break;
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}
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/* Match 1, 2, or all 4 byte addresses in this word.
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*
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* FIXME: v7 hardware allows lengths up to 2 GB, and has eight
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* byte address select bits. Support larger wp->length, if addr
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* is suitably aligned.
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*/
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switch (wp->length) {
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case 1:
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control |= (1 << (addr & 3)) << 5;
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addr &= ~3;
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break;
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case 2:
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/* require 2-byte alignment */
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if (!(addr & 1)) {
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control |= (3 << (addr & 2)) << 5;
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break;
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}
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/* FALL THROUGH */
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case 4:
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/* require 4-byte alignment */
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if (!(addr & 3)) {
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control |= 0xf << 5;
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break;
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}
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/* FALL THROUGH */
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default:
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LOG_DEBUG("bad watchpoint length or alignment");
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return ERROR_INVALID_ARGUMENTS;
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}
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/* other control bits:
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* bits 9:12 == 0 ... only checking up to four byte addresses (v7 only)
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* bits 15:14 == 0 ... both secure and nonsecure states (v6.1+ only)
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* bit 20 == 0 ... not linked to a context ID
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* bit 28:24 == 0 ... not ignoring N LSBs (v7 only)
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*/
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dpm->dwp[index].wp = wp;
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dpm->dwp[index].control = control;
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dpm->dwp[index].dirty = true;
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/* hardware is updated in write_dirty_registers() */
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return ERROR_OK;
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}
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static int dpm_add_watchpoint(struct target *target, struct watchpoint *wp)
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{
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struct arm *arm = target_to_arm(target);
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struct arm_dpm *dpm = arm->dpm;
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int retval = ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
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if (dpm->bpwp_enable) {
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for (unsigned i = 0; i < dpm->nwp; i++) {
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if (!dpm->dwp[i].wp) {
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retval = dpm_watchpoint_setup(dpm, i, wp);
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break;
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}
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}
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}
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return retval;
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}
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static int dpm_remove_watchpoint(struct target *target, struct watchpoint *wp)
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{
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struct arm *arm = target_to_arm(target);
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struct arm_dpm *dpm = arm->dpm;
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int retval = ERROR_INVALID_ARGUMENTS;
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for (unsigned i = 0; i < dpm->nwp; i++) {
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if (dpm->dwp[i].wp == wp) {
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dpm->dwp[i].wp = NULL;
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dpm->dwp[i].dirty = true;
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/* hardware is updated in write_dirty_registers() */
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retval = ERROR_OK;
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break;
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}
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}
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return retval;
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}
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/*----------------------------------------------------------------------*/
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/*
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* Setup and management support.
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*/
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/**
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* Hooks up this DPM to its associated target; call only once.
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* Initially this only covers the register cache.
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*
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* Oh, and watchpoints. Yeah.
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*/
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int arm_dpm_setup(struct arm_dpm *dpm)
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{
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@ -556,6 +756,7 @@ int arm_dpm_setup(struct arm_dpm *dpm)
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arm->dpm = dpm;
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/* register access setup */
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arm->full_context = arm_dpm_full_context;
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arm->read_core_reg = arm_dpm_read_core_reg;
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arm->write_core_reg = arm_dpm_write_core_reg;
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@ -566,9 +767,48 @@ int arm_dpm_setup(struct arm_dpm *dpm)
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*register_get_last_cache_p(&target->reg_cache) = cache;
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/* coprocessor access setup */
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arm->mrc = dpm_mrc;
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arm->mcr = dpm_mcr;
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/* breakpoint and watchpoint setup */
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target->type->add_watchpoint = dpm_add_watchpoint;
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target->type->remove_watchpoint = dpm_remove_watchpoint;
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/* FIXME add breakpoint support */
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/* FIXME add vector catch support */
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dpm->nbp = 1 + ((dpm->didr >> 24) & 0xf);
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dpm->dbp = calloc(dpm->nbp, sizeof *dpm->dbp);
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dpm->nwp = 1 + ((dpm->didr >> 28) & 0xf);
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dpm->dwp = calloc(dpm->nwp, sizeof *dpm->dwp);
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if (!dpm->dbp || !dpm->dwp) {
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free(dpm->dbp);
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free(dpm->dwp);
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return ERROR_FAIL;
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}
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/* Disable all breakpoints and watchpoints at startup. */
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if (dpm->bpwp_disable) {
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unsigned i;
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for (i = 0; i < dpm->nbp; i++)
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(void) dpm->bpwp_disable(dpm, i);
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for (i = 0; i < dpm->nwp; i++)
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(void) dpm->bpwp_disable(dpm, 16 + i);
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} else
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LOG_WARNING("%s: can't disable breakpoints and watchpoints",
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target_name(target));
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LOG_INFO("%s: hardware has %d breakpoints, %d watchpoints",
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target_name(target), dpm->nbp, dpm->nwp);
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/* REVISIT ... and some of those breakpoints could match
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* execution context IDs...
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*/
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return ERROR_OK;
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}
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@ -31,6 +31,26 @@
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* registers are compatible.
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*/
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struct dpm_bp {
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struct breakpoint *bp;
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/* bp->address == breakpoint value register
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* control == breakpoint control register
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*/
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uint32_t control;
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/* true if hardware state needs flushing */
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bool dirty;
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};
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struct dpm_wp {
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struct watchpoint *wp;
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/* wp->address == watchpoint value register
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* control == watchpoint control register
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*/
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uint32_t control;
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/* true if hardware state needs flushing */
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bool dirty;
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};
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/**
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* This wraps an implementation of DPM primitives. Each interface
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* provider supplies a structure like this, which is the glue between
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@ -74,9 +94,33 @@ struct arm_dpm {
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int (*instr_read_data_r0)(struct arm_dpm *,
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uint32_t opcode, uint32_t *data);
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// FIXME -- add breakpoint support
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/* BREAKPOINT/WATCHPOINT SUPPORT */
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// FIXME -- add watchpoint support (including context-sensitive ones)
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/**
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* Enables one breakpoint or watchpoint by writing to the
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* hardware registers. The specified breakpoint/watchpoint
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* must currently be disabled. Indices 0..15 are used for
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* breakpoints; indices 16..31 are for watchpoints.
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*/
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int (*bpwp_enable)(struct arm_dpm *, unsigned index,
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uint32_t addr, uint32_t control);
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/**
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* Disables one breakpoint or watchpoint by clearing its
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* hardware control registers. Indices are the same ones
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* accepted by bpwp_enable().
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*/
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int (*bpwp_disable)(struct arm_dpm *, unsigned index);
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/* The breakpoint and watchpoint arrays are private to the
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* DPM infrastructure. There are nbp indices in the dbp
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* array. There are nwp indices in the dwp array.
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*/
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unsigned nbp;
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unsigned nwp;
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struct dpm_bp *dbp;
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struct dpm_wp *dwp;
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// FIXME -- read/write DCSR methods and symbols
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};
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@ -85,6 +129,6 @@ int arm_dpm_setup(struct arm_dpm *dpm);
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int arm_dpm_reinitialize(struct arm_dpm *dpm);
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||||
int arm_dpm_read_current_registers(struct arm_dpm *);
|
||||
int arm_dpm_write_dirty_registers(struct arm_dpm *);
|
||||
int arm_dpm_write_dirty_registers(struct arm_dpm *, bool bpwp);
|
||||
|
||||
#endif /* __ARM_DPM_H */
|
||||
|
|
|
|||
|
|
@ -41,7 +41,7 @@
|
|||
|
||||
static int cortex_a8_poll(struct target *target);
|
||||
static int cortex_a8_debug_entry(struct target *target);
|
||||
static int cortex_a8_restore_context(struct target *target);
|
||||
static int cortex_a8_restore_context(struct target *target, bool bpwp);
|
||||
static int cortex_a8_set_breakpoint(struct target *target,
|
||||
struct breakpoint *breakpoint, uint8_t matchmode);
|
||||
static int cortex_a8_unset_breakpoint(struct target *target,
|
||||
|
|
@ -602,11 +602,7 @@ static int cortex_a8_resume(struct target *target, int current,
|
|||
dap_ap_select(swjdp, swjdp_debugap);
|
||||
|
||||
if (!debug_execution)
|
||||
{
|
||||
target_free_all_working_areas(target);
|
||||
// cortex_m3_enable_breakpoints(target);
|
||||
// cortex_m3_enable_watchpoints(target);
|
||||
}
|
||||
|
||||
#if 0
|
||||
if (debug_execution)
|
||||
|
|
@ -661,7 +657,7 @@ static int cortex_a8_resume(struct target *target, int current,
|
|||
armv4_5->core_cache->reg_list[15].dirty = 1;
|
||||
armv4_5->core_cache->reg_list[15].valid = 1;
|
||||
|
||||
cortex_a8_restore_context(target);
|
||||
cortex_a8_restore_context(target, handle_breakpoints);
|
||||
|
||||
#if 0
|
||||
/* the front-end may request us not to handle breakpoints */
|
||||
|
|
@ -952,7 +948,7 @@ static int cortex_a8_step(struct target *target, int current, uint32_t address,
|
|||
return ERROR_OK;
|
||||
}
|
||||
|
||||
static int cortex_a8_restore_context(struct target *target)
|
||||
static int cortex_a8_restore_context(struct target *target, bool bpwp)
|
||||
{
|
||||
struct armv7a_common *armv7a = target_to_armv7a(target);
|
||||
|
||||
|
|
@ -961,7 +957,7 @@ static int cortex_a8_restore_context(struct target *target)
|
|||
if (armv7a->pre_restore_context)
|
||||
armv7a->pre_restore_context(target);
|
||||
|
||||
arm_dpm_write_dirty_registers(&armv7a->dpm);
|
||||
arm_dpm_write_dirty_registers(&armv7a->dpm, bpwp);
|
||||
|
||||
if (armv7a->post_restore_context)
|
||||
armv7a->post_restore_context(target);
|
||||
|
|
|
|||
Loading…
Reference in New Issue