michal smulski <michal.smulski@ooma.com> reset now works
git-svn-id: svn://svn.berlios.de/openocd/trunk@2778 b42882b7-edfa-0310-969c-e2dbd0fdcd60
This commit is contained in:
oharboe
parent
e4de4251fe
commit
642519649e
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@ -1,33 +1,34 @@
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source [find target/c100.cfg]
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source [find c100.cfg]
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# basic register defintion for C100
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source [find target/c100regs.tcl]
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source [find c100regs.tcl]
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# board-config info
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source [find target/c100config.tcl]
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source [find c100config.tcl]
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# C100 helper functions
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source [find target/c100helper.tcl]
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source [find c100helper.tcl]
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# Telo board & C100 support trst and srst
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# however openocd does not support
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# 1. setting srst reset pulse width
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# 2. setting delay between srst pulse and JTAG access
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# This really makes the srst useless for now.
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# Note that libftd2xx.so tries to assert srst
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# which break this script
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# use libftdi.so library instead with this script
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# make the reset asserted to
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# allow RC circuit to discharge for: [ms]
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jtag_nsrst_assert_width 100
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jtag_ntrst_assert_width 100
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# don't talk to JTAG after reset for: [ms]
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jtag_nsrst_delay 100
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jtag_ntrst_delay 100
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reset_config trst_and_srst separate
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# issue telnet: reset init
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# issue gdb: monitor reset init
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$_TARGETNAME configure -event reset-init {
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jtag_khz 100
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# setup GPIO used as control signals for C100
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setupGPIO
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# This will allow acces to lower 8MB or NOR
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lowGPIO5
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# setup NOR size,timing,etc.
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setupNOR
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# setup internals + PLL + DDR2
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initC100
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# this will setup Telo board
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setupTelo
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#turn up the JTAG speed
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jtag_khz 3000
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puts "JTAG speek now 3MHz"
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@ -41,6 +42,11 @@ $_TARGETNAME configure -event reset-deassert-post {
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}
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$_TARGETNAME configure -event reset-assert-post {
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puts "Assering reset"
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#sleep 10
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}
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proc power_restore {} { puts "Sensed power restore. No action." }
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proc srst_deasserted {} { puts "Sensed nSRST deasserted. No action." }
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@ -38,6 +38,20 @@ proc configC100 {} {
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}
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# This should be called for reset init event handler
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proc setupTelo {} {
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# setup GPIO used as control signals for C100
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setupGPIO
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# This will allow acces to lower 8MB or NOR
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lowGPIO5
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# setup NOR size,timing,etc.
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setupNOR
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# setup internals + PLL + DDR2
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initC100
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}
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proc setupNOR {} {
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puts "Setting up NOR: 16MB, 16-bit wide bus, CS0"
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# this is taken from u-boot/boards/mindspeed/ooma-darwin/board.c:nor_hw_init()
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@ -139,6 +153,7 @@ proc boardID {id} {
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return $boardID
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}
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# converted from u-boot/boards/mindspeed/ooma-darwin/board.c:ooma_board_detect()
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# figure out what board revision this is, uses BOOTSTRAP register to read stuffed resistors
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proc ooma_board_detect {} {
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@ -152,12 +167,77 @@ proc ooma_board_detect {} {
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# display board ID
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puts [format "This is %s (0x%x)" [dict get [boardID $gpbt] $gpbt name] $gpbt]
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# show it on serial console
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putsUART0 [format "This is %s (0x%x)\n" [dict get [boardID $gpbt] $gpbt name] $gpbt]
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# return the ddr2 size, used to configure DDR2 on a given board.
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return [dict get [boardID $gpbt] $gpbt ddr2size]
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}
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proc configureDDR2regs_256M {} {
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puts "ConfigureDDR2regs_256M TBD"
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set DENALI_CTL_00_DATA [regs DENALI_CTL_00_DATA]
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set DENALI_CTL_01_DATA [regs DENALI_CTL_01_DATA]
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set DENALI_CTL_02_DATA [regs DENALI_CTL_02_DATA]
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set DENALI_CTL_03_DATA [regs DENALI_CTL_03_DATA]
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set DENALI_CTL_04_DATA [regs DENALI_CTL_04_DATA]
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set DENALI_CTL_05_DATA [regs DENALI_CTL_05_DATA]
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set DENALI_CTL_06_DATA [regs DENALI_CTL_06_DATA]
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set DENALI_CTL_07_DATA [regs DENALI_CTL_07_DATA]
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set DENALI_CTL_08_DATA [regs DENALI_CTL_08_DATA]
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set DENALI_CTL_09_DATA [regs DENALI_CTL_09_DATA]
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set DENALI_CTL_10_DATA [regs DENALI_CTL_10_DATA]
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set DENALI_CTL_11_DATA [regs DENALI_CTL_11_DATA]
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set DENALI_CTL_12_DATA [regs DENALI_CTL_12_DATA]
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set DENALI_CTL_13_DATA [regs DENALI_CTL_13_DATA]
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set DENALI_CTL_14_DATA [regs DENALI_CTL_14_DATA]
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set DENALI_CTL_15_DATA [regs DENALI_CTL_15_DATA]
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set DENALI_CTL_16_DATA [regs DENALI_CTL_16_DATA]
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set DENALI_CTL_17_DATA [regs DENALI_CTL_17_DATA]
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set DENALI_CTL_18_DATA [regs DENALI_CTL_18_DATA]
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set DENALI_CTL_19_DATA [regs DENALI_CTL_19_DATA]
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set DENALI_CTL_20_DATA [regs DENALI_CTL_20_DATA]
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set DENALI_CTL_02_VAL 0x0100000000010100
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set DENALI_CTL_11_VAL 0x433a32164a560a00
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mw64bit $DENALI_CTL_00_DATA 0x0100000101010101
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# 01_DATA mod [40]=1, enable BA2
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mw64bit $DENALI_CTL_01_DATA 0x0100010100000001
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mw64bit $DENALI_CTL_02_DATA $DENALI_CTL_02_VAL
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mw64bit $DENALI_CTL_03_DATA 0x0102020202020201
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mw64bit $DENALI_CTL_04_DATA 0x0000010100000001
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mw64bit $DENALI_CTL_05_DATA 0x0203010300010101
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mw64bit $DENALI_CTL_06_DATA 0x060a020200020202
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mw64bit $DENALI_CTL_07_DATA 0x0000000300000206
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mw64bit $DENALI_CTL_08_DATA 0x6400003f3f0a0209
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mw64bit $DENALI_CTL_09_DATA 0x1a000000001a1a1a
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mw64bit $DENALI_CTL_10_DATA 0x0120202020191a18
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# 11_DATA mod [39-32]=16,more refresh
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mw64bit $DENALI_CTL_11_DATA $DENALI_CTL_11_VAL
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mw64bit $DENALI_CTL_12_DATA 0x0000000000000800
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mw64bit $DENALI_CTL_13_DATA 0x0010002000100040
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mw64bit $DENALI_CTL_14_DATA 0x0010004000100040
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mw64bit $DENALI_CTL_15_DATA 0x04f8000000000000
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mw64bit $DENALI_CTL_16_DATA 0x000000002cca0000
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mw64bit $DENALI_CTL_17_DATA 0x0000000000000000
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mw64bit $DENALI_CTL_18_DATA 0x0302000000000000
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mw64bit $DENALI_CTL_19_DATA 0x00001300c8030600
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mw64bit $DENALI_CTL_20_DATA 0x0000000081fe00c8
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set wr_dqs_shift 0x40
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# start DDRC
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mw64bit $DENALI_CTL_02_DATA [expr $DENALI_CTL_02_VAL | (1 << 32)]
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# wait int_status[2] (DRAM init complete)
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puts -nonewline "Waiting for DDR2 controller to init..."
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set tmp [mrw [expr $DENALI_CTL_08_DATA + 4]]
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while { [expr $tmp & 0x040000] == 0 } {
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sleep 1
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set tmp [mrw [expr $DENALI_CTL_08_DATA + 4]]
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}
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puts "done."
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# do ddr2 training sequence
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# TBD (for now, if you need it, run trainDDR command)
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}
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# converted from u-boot/cpu/arm1136/comcerto/bsp100.c:config_board99()
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@ -222,7 +302,8 @@ proc configureDDR2regs_128M {} {
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sleep 1
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set tmp [mrw [expr $DENALI_CTL_08_DATA + 4]]
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}
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mw64bit $DENALI_CTL_11_DATA [expr ($DENALI_CTL_11_VAL & ~0x00007F0000000000) | ($wr_dqs_shift << 40) ]
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# This is not necessary
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#mw64bit $DENALI_CTL_11_DATA [expr ($DENALI_CTL_11_VAL & ~0x00007F0000000000) | ($wr_dqs_shift << 40) ]
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puts "done."
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# do ddr2 training sequence
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@ -308,7 +389,7 @@ proc trainDDR2 {} {
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resume
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}
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proc flashUBOOT {} {
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proc flashUBOOT {file} {
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# this will update uboot on NOR partition
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set EXP_CS0_BASEADDR [regs EXP_CS0_BASEADDR]
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@ -318,7 +399,14 @@ proc flashUBOOT {} {
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lowGPIO5
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flash probe 0
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puts "Erasing sectors 0-3 for uboot"
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putsUART0 "Erasing sectors 0-3 for uboot\n"
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flash erase_sector 0 0 3
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puts "Programming u-boot, takes about 4-5 min for 256kb"
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flash write_image ./images/u-boot.bin $EXP_CS0_BASEADDR
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puts "Programming u-boot"
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putsUART0 "Programming u-boot..."
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memwrite burst enable
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flash write_image $file $EXP_CS0_BASEADDR
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memwrite burst disable
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putsUART0 "done.\n"
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putsUART0 "Rebooting, please wait!\n"
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reboot
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}
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@ -1,9 +1,60 @@
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source [find c100.cfg]
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# basic register defintion for C100
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source [find c100regs.tcl]
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# board-config info
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source [find c100config.tcl]
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# C100 helper functions
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source [find c100helper.tcl]
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# Telo board & C100 support trst and srst
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# Note that libftd2xx.so tries to assert srst
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# which break this script
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# use libftdi.so library instead with this script
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# make the reset asserted to
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# allow RC circuit to discharge for: [ms]
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jtag_nsrst_assert_width 100
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jtag_ntrst_assert_width 100
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# don't talk to JTAG after reset for: [ms]
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jtag_nsrst_delay 100
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jtag_ntrst_delay 100
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reset_config trst_and_srst separate
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# issue telnet: reset init
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# issue gdb: monitor reset init
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$_TARGETNAME configure -event reset-init {
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jtag_khz 100
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# this will setup Telo board
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setupTelo
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#turn up the JTAG speed
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jtag_khz 3000
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puts "JTAG speek now 3MHz"
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puts "type helpC100 to get help on C100"
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}
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$_TARGETNAME configure -event reset-deassert-post {
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# Force target into ARM state.
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# soft_reset_halt # not implemented on ARM11
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puts "Detected SRSRT asserted on C100.CPU"
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}
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$_TARGETNAME configure -event reset-assert-post {
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puts "Assering reset"
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#sleep 10
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}
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proc power_restore {} { puts "Sensed power restore. No action." }
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proc srst_deasserted {} { puts "Sensed nSRST deasserted. No action." }
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# boots from NOR on CS0: 8 MBytes CFI flash, 16-bit bus
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# it's really 16MB but the upper 8mb is controller via gpio?
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# it's really 16MB but the upper 8mb is controller via gpio
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# openocd does not support 'complex reads/writes' to NOR
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flash bank cfi 0x20000000 0x01000000 2 2 $_TARGETNAME
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#
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gdb_memory_map enable
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# writing data to memory does not work without this
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memwrite burst disable
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