diff --git a/contrib/loaders/flash/npcx/npcx_algo.inc b/contrib/loaders/flash/npcx/npcx_algo.inc index 4312fdb1b..46b79d8d9 100644 --- a/contrib/loaders/flash/npcx/npcx_algo.inc +++ b/contrib/loaders/flash/npcx/npcx_algo.inc @@ -1,60 +1,70 @@ /* Autogenerated with ../../../../src/helper/bin2char.sh */ -0x08,0xb5,0xdf,0xf8,0x08,0xd0,0x00,0xf0,0x2f,0xf9,0x00,0x00,0x48,0x15,0x0c,0x20, -0x03,0x4b,0x18,0x70,0x19,0x72,0x08,0x33,0x1a,0x78,0xd2,0x09,0xfc,0xd1,0x70,0x47, -0x16,0x00,0x02,0x40,0x70,0xb5,0x11,0x4c,0x23,0x78,0x03,0xf0,0xfd,0x03,0x23,0x70, -0xc0,0x21,0x05,0x20,0xff,0xf7,0xec,0xff,0x0d,0x4a,0x0e,0x49,0x6f,0xf0,0x7f,0x43, -0x6f,0xf0,0x2e,0x05,0x10,0x46,0x15,0x70,0x06,0x78,0xf6,0x09,0xfc,0xd1,0x0e,0x78, -0xf6,0x07,0x01,0xd5,0x01,0x3b,0xf6,0xd1,0x22,0x78,0x42,0xf0,0x02,0x02,0x00,0x2b, -0x22,0x70,0x0c,0xbf,0x03,0x20,0x00,0x20,0x70,0xbd,0x00,0xbf,0x1f,0x00,0x02,0x40, +0x08,0xb5,0xdf,0xf8,0x08,0xd0,0x00,0xf0,0x95,0xf9,0x00,0x00,0xec,0x15,0x0c,0x20, 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+0x1b,0xff,0xf2,0xe7,0x01,0x20,0xf2,0xe7,0x00,0x00,0x0c,0x20,0x14,0x00,0x0c,0x20, +0xf0,0xb5,0x83,0x07,0x47,0xd0,0x54,0x1e,0x00,0x2a,0x41,0xd0,0x0d,0x06,0x2d,0x0e, +0x02,0x00,0x03,0x26,0x02,0xe0,0x1a,0x00,0x01,0x3c,0x39,0xd3,0x53,0x1c,0x15,0x70, +0x33,0x42,0xf8,0xd1,0x03,0x2c,0x2a,0xd9,0xff,0x22,0x0a,0x40,0x15,0x02,0x15,0x43, +0x2a,0x04,0x15,0x43,0x0f,0x2c,0x14,0xd9,0x27,0x00,0x1a,0x00,0x10,0x3f,0x3e,0x09, +0x01,0x36,0x36,0x01,0x9e,0x19,0x15,0x60,0x55,0x60,0x95,0x60,0xd5,0x60,0x10,0x32, +0x96,0x42,0xf8,0xd1,0x0f,0x22,0x97,0x43,0x10,0x37,0xdb,0x19,0x14,0x40,0x03,0x2c, +0x0d,0xd9,0x1a,0x00,0x27,0x1f,0xbe,0x08,0x01,0x36,0xb6,0x00,0x9e,0x19,0x20,0xc2, +0xb2,0x42,0xfc,0xd1,0x03,0x22,0x97,0x43,0x04,0x37,0xdb,0x19,0x14,0x40,0x00,0x2c, +0x06,0xd0,0x09,0x06,0x1c,0x19,0x09,0x0e,0x19,0x70,0x01,0x33,0x9c,0x42,0xfb,0xd1, +0xf0,0xbc,0x02,0xbc,0x08,0x47,0x14,0x00,0x03,0x00,0xc3,0xe7, diff --git a/contrib/loaders/flash/npcx/npcx_flash.c b/contrib/loaders/flash/npcx/npcx_flash.c index 7d59123aa..6df01b2d4 100644 --- a/contrib/loaders/flash/npcx/npcx_flash.c +++ b/contrib/loaders/flash/npcx/npcx_flash.c @@ -10,9 +10,29 @@ #include #include "npcx_flash.h" +/* flashloader parameter structure */ +__attribute__ ((section(".buffers.g_cfg"))) +static volatile struct npcx_flash_params g_cfg; +/* data buffer */ +__attribute__ ((section(".buffers.g_buf"))) +static uint8_t g_buf[NPCX_FLASH_LOADER_BUFFER_SIZE]; + /*---------------------------------------------------------------------------- * NPCX flash driver *----------------------------------------------------------------------------*/ +static void flash_init(void) +{ + if (g_cfg.fiu_ver == NPCX_FIU_NPCK) { + /* Set pinmux to SHD flash */ + NPCX_DEVCNT = 0x80; + NPCX_DEVALT(0) = 0xC0; + NPCX_DEVALT(4) = 0x00; + } else { + /* Avoid F_CS0 toggles while programming the internal flash. */ + NPCX_SET_BIT(NPCX_DEVALT(0), NPCX_DEVALT0_NO_F_SPI); + } +} + static void flash_execute_cmd(uint8_t code, uint8_t cts) { /* Set UMA code */ @@ -26,11 +46,26 @@ static void flash_execute_cmd(uint8_t code, uint8_t cts) static void flash_cs_level(uint8_t level) { + int sw_cs = 0; + + if (g_cfg.fiu_ver == NPCX_FIU_NPCX) { + sw_cs = 1; + } else if (g_cfg.fiu_ver == NPCX_FIU_NPCX_V2) { + sw_cs = 0; + } else if (g_cfg.fiu_ver == NPCX_FIU_NPCK) { + sw_cs = 1; + /* Unlock UMA before pulling down CS in NPCK series */ + if (level) + NPCX_CLEAR_BIT(NPCX_FIU_MSR_IE_CFG, NPCX_FIU_MSR_IE_CFG_UMA_BLOCK); + else + NPCX_SET_BIT(NPCX_FIU_MSR_IE_CFG, NPCX_FIU_MSR_IE_CFG_UMA_BLOCK); + } + /* Program chip select pin to high/low level */ if (level) - NPCX_SET_BIT(NPCX_UMA_ECTS, NPCX_UMA_ECTS_SW_CS1); + NPCX_SET_BIT(NPCX_UMA_ECTS, sw_cs); else - NPCX_CLEAR_BIT(NPCX_UMA_ECTS, NPCX_UMA_ECTS_SW_CS1); + NPCX_CLEAR_BIT(NPCX_UMA_ECTS, sw_cs); } static void flash_set_address(uint32_t dest_addr) @@ -38,15 +73,15 @@ static void flash_set_address(uint32_t dest_addr) uint8_t *addr = (uint8_t *)&dest_addr; /* Set target flash address */ - NPCX_UMA_AB2 = addr[2]; - NPCX_UMA_AB1 = addr[1]; - NPCX_UMA_AB0 = addr[0]; + NPCX_UMA_DB0 = addr[2]; + NPCX_UMA_DB1 = addr[1]; + NPCX_UMA_DB2 = addr[0]; } -void delay(uint32_t i) +static void delay(uint32_t i) { while (i--) - ; + __asm__ volatile ("nop"); } static int flash_wait_ready(uint32_t timeout) @@ -104,7 +139,7 @@ static void flash_burst_write(uint32_t dest_addr, uint16_t bytes, /* Set write address */ flash_set_address(dest_addr); /* Start programming */ - flash_execute_cmd(NPCX_CMD_FLASH_PROGRAM, NPCX_MASK_CMD_WR_ADR); + flash_execute_cmd(NPCX_CMD_FLASH_PROGRAM, NPCX_MASK_CMD_WR_3BYTE); for (uint32_t i = 0; i < bytes; i++) { flash_execute_cmd(*data, NPCX_MASK_CMD_WR_ONLY); data++; @@ -114,6 +149,15 @@ static void flash_burst_write(uint32_t dest_addr, uint16_t bytes, flash_cs_level(1); } +static void flash_get_stsreg(uint8_t *reg1, uint8_t *reg2) +{ + /* Read status register 1/2 for checking */ + flash_execute_cmd(NPCX_CMD_READ_STATUS_REG, NPCX_MASK_CMD_RD_1BYTE); + *reg1 = NPCX_UMA_DB0; + flash_execute_cmd(NPCX_CMD_READ_STATUS_REG2, NPCX_MASK_CMD_RD_1BYTE); + *reg2 = NPCX_UMA_DB0; +} + /* The data to write cannot cross 256 Bytes boundary */ static int flash_program_write(uint32_t addr, uint32_t size, const uint8_t *data) @@ -126,7 +170,41 @@ static int flash_program_write(uint32_t addr, uint32_t size, return flash_wait_ready(NPCX_FLASH_ABORT_TIMEOUT); } -int flash_physical_write(uint32_t offset, uint32_t size, const uint8_t *data) +static int flash_physical_clear_stsreg(void) +{ + int status; + uint8_t reg1, reg2; + + /* Read status register 1/2 for checking */ + flash_get_stsreg(®1, ®2); + if (reg1 == 0x00 && reg2 == 0x00) + return NPCX_FLASH_STATUS_OK; + + /* Enable write */ + status = flash_write_enable(); + if (status != NPCX_FLASH_STATUS_OK) + return status; + + NPCX_UMA_DB0 = 0x0; + NPCX_UMA_DB1 = 0x0; + + /* Write status register 1/2 */ + flash_execute_cmd(NPCX_CMD_WRITE_STATUS_REG, NPCX_MASK_CMD_WR_2BYTE); + + /* Wait writing completed */ + status = flash_wait_ready(NPCX_FLASH_ABORT_TIMEOUT); + if (status != NPCX_FLASH_STATUS_OK) + return status; + + /* Read status register 1/2 for checking */ + flash_get_stsreg(®1, ®2); + if (reg1 != 0x00 || reg2 != 0x00) + return NPCX_FLASH_STATUS_FAILED; + + return NPCX_FLASH_STATUS_OK; +} + +static int flash_physical_write(uint32_t offset, uint32_t size, const uint8_t *data) { int status; uint32_t trunk_start = (offset + 0xff) & ~0xff; @@ -135,6 +213,13 @@ int flash_physical_write(uint32_t offset, uint32_t size, const uint8_t *data) uint32_t dest_addr = offset; uint32_t write_len = ((trunk_start - offset) > size) ? size : (trunk_start - offset); + /* Configure fiu and clear status registers if needed */ + flash_init(); + status = flash_physical_clear_stsreg(); + if (status != NPCX_FLASH_STATUS_OK) + return status; + + if (write_len) { status = flash_program_write(dest_addr, write_len, data); if (status != NPCX_FLASH_STATUS_OK) @@ -162,8 +247,16 @@ int flash_physical_write(uint32_t offset, uint32_t size, const uint8_t *data) return NPCX_FLASH_STATUS_OK; } -int flash_physical_erase(uint32_t offset, uint32_t size) +static int flash_physical_erase(uint32_t offset, uint32_t size) { + /* Configure fiu */ + flash_init(); + + /* clear flash status registers */ + int status = flash_physical_clear_stsreg(); + if (status != NPCX_FLASH_STATUS_OK) + return status; + /* Alignment has been checked in upper layer */ for (; size > 0; size -= NPCX_FLASH_ERASE_SIZE, offset += NPCX_FLASH_ERASE_SIZE) { @@ -175,7 +268,7 @@ int flash_physical_erase(uint32_t offset, uint32_t size) /* Set erase address */ flash_set_address(offset); /* Start erase */ - flash_execute_cmd(NPCX_CMD_SECTOR_ERASE, NPCX_MASK_CMD_ADR); + flash_execute_cmd(NPCX_CMD_SECTOR_ERASE, NPCX_MASK_CMD_WR_3BYTE); /* Wait erase completed */ status = flash_wait_ready(NPCX_FLASH_ABORT_TIMEOUT); if (status != NPCX_FLASH_STATUS_OK) @@ -185,10 +278,18 @@ int flash_physical_erase(uint32_t offset, uint32_t size) return NPCX_FLASH_STATUS_OK; } -int flash_physical_erase_all(void) +static int flash_physical_erase_all(void) { + int status; + + /* Configure fiu and clear status register if needed */ + flash_init(); + status = flash_physical_clear_stsreg(); + if (status != NPCX_FLASH_STATUS_OK) + return status; + /* Enable write */ - int status = flash_write_enable(); + status = flash_write_enable(); if (status != NPCX_FLASH_STATUS_OK) return status; @@ -203,37 +304,10 @@ int flash_physical_erase_all(void) return NPCX_FLASH_STATUS_OK; } -int flash_physical_clear_stsreg(void) +static int flash_get_id(uint32_t *id) { - /* Enable write */ - int status = flash_write_enable(); - if (status != NPCX_FLASH_STATUS_OK) - return status; + flash_init(); - NPCX_UMA_DB0 = 0x0; - NPCX_UMA_DB1 = 0x0; - - /* Write status register 1/2 */ - flash_execute_cmd(NPCX_CMD_WRITE_STATUS_REG, NPCX_MASK_CMD_WR_2BYTE); - - /* Wait writing completed */ - status = flash_wait_ready(NPCX_FLASH_ABORT_TIMEOUT); - if (status != NPCX_FLASH_STATUS_OK) - return status; - - /* Read status register 1/2 for checking */ - flash_execute_cmd(NPCX_CMD_READ_STATUS_REG, NPCX_MASK_CMD_RD_1BYTE); - if (NPCX_UMA_DB0 != 0x00) - return NPCX_FLASH_STATUS_FAILED; - flash_execute_cmd(NPCX_CMD_READ_STATUS_REG2, NPCX_MASK_CMD_RD_1BYTE); - if (NPCX_UMA_DB0 != 0x00) - return NPCX_FLASH_STATUS_FAILED; - - return NPCX_FLASH_STATUS_OK; -} - -int flash_get_id(uint32_t *id) -{ flash_execute_cmd(NPCX_CMD_READ_ID, NPCX_MASK_CMD_RD_3BYTE); *id = NPCX_UMA_DB0 << 16 | NPCX_UMA_DB1 << 8 | NPCX_UMA_DB2; @@ -243,7 +317,7 @@ int flash_get_id(uint32_t *id) /*---------------------------------------------------------------------------- * flash loader function *----------------------------------------------------------------------------*/ -uint32_t flashloader_init(struct npcx_flash_params *params) +static uint32_t flashloader_init(struct npcx_flash_params *params) { /* Initialize params buffers */ memset(params, 0, sizeof(struct npcx_flash_params)); @@ -254,30 +328,13 @@ uint32_t flashloader_init(struct npcx_flash_params *params) /*---------------------------------------------------------------------------- * Functions *----------------------------------------------------------------------------*/ -/* flashloader parameter structure */ -__attribute__ ((section(".buffers.g_cfg"))) -volatile struct npcx_flash_params g_cfg; -/* data buffer */ -__attribute__ ((section(".buffers.g_buf"))) -uint8_t g_buf[NPCX_FLASH_LOADER_BUFFER_SIZE]; - -int main(void) +static int main(void) { - uint32_t id; + uint32_t id, status; /* set buffer */ flashloader_init((struct npcx_flash_params *)&g_cfg); - /* Avoid F_CS0 toggles while programming the internal flash. */ - NPCX_SET_BIT(NPCX_DEVALT(0), NPCX_DEVALT0_NO_F_SPI); - - /* clear flash status registers */ - int status = flash_physical_clear_stsreg(); - if (status != NPCX_FLASH_STATUS_OK) { - while (1) - g_cfg.sync = status; - } - while (1) { /* wait command*/ while (g_cfg.sync == NPCX_FLASH_LOADER_WAIT) diff --git a/contrib/loaders/flash/npcx/npcx_flash.h b/contrib/loaders/flash/npcx/npcx_flash.h index cc4f1ad50..48e5d82fd 100644 --- a/contrib/loaders/flash/npcx/npcx_flash.h +++ b/contrib/loaders/flash/npcx/npcx_flash.h @@ -80,6 +80,7 @@ #define NPCX_FIU_DMM_CYC NPCX_HW_BYTE(NPCX_FIU_BASE_ADDR + 0x032) #define NPCX_FIU_EXT_CFG NPCX_HW_BYTE(NPCX_FIU_BASE_ADDR + 0x033) #define NPCX_FIU_UMA_AB0_3 NPCX_HW_DWORD(NPCX_FIU_BASE_ADDR + 0x034) +#define NPCX_FIU_MSR_IE_CFG NPCX_HW_BYTE(NPCX_FIU_BASE_ADDR + 0x043) /* FIU register fields */ #define NPCX_RESP_CFG_IAD_EN 0 @@ -93,6 +94,7 @@ #define NPCX_UMA_ECTS_SW_CS1 1 #define NPCX_UMA_ECTS_SEC_CS 2 #define NPCX_UMA_ECTS_UMA_LOCK 3 +#define NPCX_FIU_MSR_IE_CFG_UMA_BLOCK 3 /* Flash UMA commands for npcx internal SPI flash */ #define NPCX_CMD_READ_ID 0x9F @@ -130,7 +132,6 @@ #define NPCX_SPI_FLASH_SR1_BUSY (1 << 0) #define NPCX_MASK_CMD_ONLY (0xC0) -#define NPCX_MASK_CMD_ADR (0xC0 | 0x08) #define NPCX_MASK_CMD_ADR_WR (0xC0 | 0x20 | 0x08 | 0x01) #define NPCX_MASK_RD_1BYTE (0xC0 | 0x10 | 0x01) #define NPCX_MASK_RD_2BYTE (0xC0 | 0x10 | 0x02) @@ -143,10 +144,12 @@ #define NPCX_MASK_CMD_WR_ONLY (0xC0 | 0x20) #define NPCX_MASK_CMD_WR_1BYTE (0xC0 | 0x20 | 0x10 | 0x01) #define NPCX_MASK_CMD_WR_2BYTE (0xC0 | 0x20 | 0x10 | 0x02) -#define NPCX_MASK_CMD_WR_ADR (0xC0 | 0x20 | 0x08) +#define NPCX_MASK_CMD_WR_3BYTE (0xC0 | 0x20 | 0x10 | 0x03) +#define NPCX_MASK_CMD_WR_4BYTE (0xC0 | 0x20 | 0x10 | 0x04) /* Flash loader parameters */ struct __attribute__((__packed__)) npcx_flash_params { + uint32_t fiu_ver; /* Flash controller unit version */ uint32_t addr; /* Address in flash */ uint32_t len; /* Number of bytes */ uint32_t cmd; /* Command */ @@ -176,4 +179,10 @@ enum npcx_flash_status { NPCX_FLASH_STATUS_FAILED_TIMEOUT, }; +enum npcx_fiu_ver { + NPCX_FIU_NPCX = 0, + NPCX_FIU_NPCX_V2, + NPCX_FIU_NPCK, +}; + #endif /* OPENOCD_LOADERS_FLASH_NPCX_NPCX_FLASH_H */ diff --git a/contrib/loaders/flash/npcx/npcx_flash_config.h b/contrib/loaders/flash/npcx/npcx_flash_config.h index 9ec1c5e33..4abd23e34 100644 --- a/contrib/loaders/flash/npcx/npcx_flash_config.h +++ b/contrib/loaders/flash/npcx/npcx_flash_config.h @@ -18,7 +18,7 @@ /* NPCX flash loader information */ #define NPCX_FLASH_LOADER_WORKING_ADDR 0x200C0000 #define NPCX_FLASH_LOADER_PARAMS_ADDR NPCX_FLASH_LOADER_WORKING_ADDR -#define NPCX_FLASH_LOADER_PARAMS_SIZE 16 +#define NPCX_FLASH_LOADER_PARAMS_SIZE 20 #define NPCX_FLASH_LOADER_BUFFER_ADDR (NPCX_FLASH_LOADER_PARAMS_ADDR + NPCX_FLASH_LOADER_PARAMS_SIZE) #define NPCX_FLASH_LOADER_BUFFER_SIZE NPCX_FLASH_ERASE_SIZE #define NPCX_FLASH_LOADER_PROGRAM_ADDR (NPCX_FLASH_LOADER_BUFFER_ADDR + NPCX_FLASH_LOADER_BUFFER_SIZE) diff --git a/doc/openocd.texi b/doc/openocd.texi index d07188c4b..f6f7a0c29 100644 --- a/doc/openocd.texi +++ b/doc/openocd.texi @@ -7193,10 +7193,16 @@ Show information about flash driver. All versions of the NPCX microcontroller families from Nuvoton include internal flash. The NPCX flash driver supports the NPCX family of devices. The driver automatically recognizes the specific version's flash parameters and -autoconfigures itself. The flash bank starts at address 0x64000000. +autoconfigures itself. The flash bank starts at address 0x64000000. An optional additional +parameter sets the FIU version for the bank, with the default FIU is @var{npcx.fiu}. @example + +flash bank $_FLASHNAME npcx 0x64000000 0 0 0 $_TARGETNAME npcx_v2.fiu + +# FIU defaults to npcx.fiu flash bank $_FLASHNAME npcx 0x64000000 0 0 0 $_TARGETNAME + @end example @end deffn diff --git a/src/flash/nor/npcx.c b/src/flash/nor/npcx.c index bc8475346..7304a6841 100644 --- a/src/flash/nor/npcx.c +++ b/src/flash/nor/npcx.c @@ -4,6 +4,7 @@ * Copyright (C) 2020 by Nuvoton Technology Corporation * Mulin Chao * Wealian Liao + * Luca Hung */ #ifdef HAVE_CONFIG_H @@ -22,7 +23,6 @@ static const uint8_t npcx_algo[] = { }; #define NPCX_FLASH_TIMEOUT_MS 8000 -#define NPCX_FLASH_BASE_ADDR 0x64000000 /* flash list */ enum npcx_flash_device_index { @@ -33,7 +33,6 @@ enum npcx_flash_device_index { }; struct npcx_flash_bank { - const char *family_name; uint32_t sector_length; bool probed; enum npcx_flash_device_index flash; @@ -44,6 +43,7 @@ struct npcx_flash_bank { uint32_t algo_working_size; uint32_t buffer_addr; uint32_t params_addr; + uint32_t fiu_ver; }; struct npcx_flash_info { @@ -90,7 +90,7 @@ static int npcx_init(struct flash_bank *bank) /* Confirm the defined working address is the area we need to use */ if (npcx_bank->working_area->address != NPCX_FLASH_LOADER_WORKING_ADDR) { - LOG_ERROR("%s: Invalid working address", npcx_bank->family_name); + LOG_TARGET_ERROR(target, "Invalid working address"); LOG_INFO("Hint: Use '-work-area-phys 0x%" PRIx32 "' in your target configuration", NPCX_FLASH_LOADER_WORKING_ADDR); target_free_working_area(target, npcx_bank->working_area); @@ -102,8 +102,7 @@ static int npcx_init(struct flash_bank *bank) retval = target_write_buffer(target, NPCX_FLASH_LOADER_PROGRAM_ADDR, npcx_bank->algo_size, npcx_bank->algo_code); if (retval != ERROR_OK) { - LOG_ERROR("%s: Failed to load flash helper algorithm", - npcx_bank->family_name); + LOG_TARGET_ERROR(target, "Failed to load flash helper algorithm"); target_free_working_area(target, npcx_bank->working_area); npcx_bank->working_area = NULL; return retval; @@ -118,8 +117,7 @@ static int npcx_init(struct flash_bank *bank) NPCX_FLASH_LOADER_PROGRAM_ADDR, 0, &npcx_bank->armv7m_info); if (retval != ERROR_OK) { - LOG_ERROR("%s: Failed to start flash helper algorithm", - npcx_bank->family_name); + LOG_TARGET_ERROR(target, "Failed to start flash helper algorithm"); target_free_working_area(target, npcx_bank->working_area); npcx_bank->working_area = NULL; return retval; @@ -154,7 +152,6 @@ static int npcx_quit(struct flash_bank *bank) static int npcx_wait_algo_done(struct flash_bank *bank, uint32_t params_addr) { struct target *target = bank->target; - struct npcx_flash_bank *npcx_bank = bank->driver_priv; uint32_t status_addr = params_addr + offsetof(struct npcx_flash_params, sync); uint32_t status; int64_t start_ms = timeval_ms(); @@ -172,9 +169,7 @@ static int npcx_wait_algo_done(struct flash_bank *bank, uint32_t params_addr) } while (status == NPCX_FLASH_LOADER_EXECUTE); if (status != NPCX_FLASH_LOADER_WAIT) { - LOG_ERROR("%s: Flash operation failed, status=0x%" PRIx32, - npcx_bank->family_name, - status); + LOG_TARGET_ERROR(target, "Flash operation failed, status (%0x" PRIX32 ") ", status); return ERROR_FAIL; } @@ -197,6 +192,7 @@ static enum npcx_flash_device_index npcx_get_flash_id(struct flash_bank *bank, u return retval; /* Set up algorithm parameters for get flash ID command */ + target_buffer_set_u32(target, (uint8_t *)&algo_params.fiu_ver, npcx_bank->fiu_ver); target_buffer_set_u32(target, (uint8_t *)&algo_params.cmd, NPCX_FLASH_CMD_GET_FLASH_ID); target_buffer_set_u32(target, (uint8_t *)&algo_params.sync, NPCX_FLASH_LOADER_WAIT); @@ -250,6 +246,7 @@ static int npcx_probe(struct flash_bank *bank) npcx_bank->buffer_addr = NPCX_FLASH_LOADER_BUFFER_ADDR; npcx_bank->params_addr = NPCX_FLASH_LOADER_PARAMS_ADDR; + int retval = npcx_get_flash_id(bank, &flash_id); if (retval != ERROR_OK) return retval; @@ -264,7 +261,6 @@ static int npcx_probe(struct flash_bank *bank) return ERROR_FAIL; } - bank->base = NPCX_FLASH_BASE_ADDR; bank->num_sectors = num_sectors; bank->size = num_sectors * sector_length; bank->write_start_alignment = 0; @@ -300,7 +296,7 @@ FLASH_BANK_COMMAND_HANDLER(npcx_flash_bank_command) { struct npcx_flash_bank *npcx_bank; - if (CMD_ARGC < 6) + if (CMD_ARGC < 6 || CMD_ARGC > 7) return ERROR_COMMAND_SYNTAX_ERROR; npcx_bank = calloc(1, sizeof(struct npcx_flash_bank)); @@ -309,8 +305,27 @@ FLASH_BANK_COMMAND_HANDLER(npcx_flash_bank_command) return ERROR_FAIL; } + const char *fiu; + if (CMD_ARGC == 6) { + LOG_WARNING("No FIU is selection, using default."); + npcx_bank->fiu_ver = NPCX_FIU_NPCX; + } + + if (CMD_ARGC == 7) { + fiu = CMD_ARGV[6]; + if (strcmp(fiu, "npcx.fiu") == 0) { + npcx_bank->fiu_ver = NPCX_FIU_NPCX; + } else if (strcmp(fiu, "npcx_v2.fiu") == 0) { + npcx_bank->fiu_ver = NPCX_FIU_NPCX_V2; + } else if (strcmp(fiu, "npck.fiu") == 0) { + npcx_bank->fiu_ver = NPCX_FIU_NPCK; + } else { + LOG_ERROR("%s is not a valid fiu", fiu); + return ERROR_TARGET_INVALID; + } + } + /* Initialize private flash information */ - npcx_bank->family_name = "npcx"; npcx_bank->sector_length = NPCX_FLASH_ERASE_SIZE; /* Finish initialization of bank */ @@ -341,6 +356,7 @@ static int npcx_chip_erase(struct flash_bank *bank) return retval; /* Set up algorithm parameters for chip erase command */ + target_buffer_set_u32(target, (uint8_t *)&algo_params.fiu_ver, npcx_bank->fiu_ver); target_buffer_set_u32(target, (uint8_t *)&algo_params.cmd, NPCX_FLASH_CMD_ERASE_ALL); target_buffer_set_u32(target, (uint8_t *)&algo_params.sync, NPCX_FLASH_LOADER_WAIT); @@ -397,6 +413,7 @@ static int npcx_erase(struct flash_bank *bank, unsigned int first, return retval; /* Set up algorithm parameters for erase command */ + target_buffer_set_u32(target, (uint8_t *)&algo_params.fiu_ver, npcx_bank->fiu_ver); target_buffer_set_u32(target, (uint8_t *)&algo_params.addr, address); target_buffer_set_u32(target, (uint8_t *)&algo_params.len, length); target_buffer_set_u32(target, (uint8_t *)&algo_params.cmd, NPCX_FLASH_CMD_ERASE_SECTORS); @@ -464,6 +481,7 @@ static int npcx_write(struct flash_bank *bank, const uint8_t *buffer, } /* Update algo parameters for flash write */ + target_buffer_set_u32(target, (uint8_t *)&algo_params.fiu_ver, npcx_bank->fiu_ver); target_buffer_set_u32(target, (uint8_t *)&algo_params.addr, address); target_buffer_set_u32(target, (uint8_t *)&algo_params.len, size); target_buffer_set_u32(target, (uint8_t *)&algo_params.sync, NPCX_FLASH_LOADER_WAIT); @@ -502,7 +520,7 @@ static int npcx_info(struct flash_bank *bank, struct command_invocation *cmd) struct npcx_flash_bank *npcx_bank = bank->driver_priv; command_print_sameline(cmd, "%s flash: %s\n", - npcx_bank->family_name, + target_name(bank->target), flash_info[npcx_bank->flash].name); return ERROR_OK; diff --git a/tcl/target/npcx.cfg b/tcl/target/npcx.cfg index 1a21e1f7f..84bb0b7a5 100644 --- a/tcl/target/npcx.cfg +++ b/tcl/target/npcx.cfg @@ -9,7 +9,7 @@ source [find target/swj-dp.tcl] if { [info exists CHIPNAME] } { set _CHIPNAME $CHIPNAME } else { - set _CHIPNAME NPCX_M4 + set _CHIPNAME npcx } # SWD DAP ID of Nuvoton NPCX Cortex-M4. @@ -27,6 +27,12 @@ if { [info exists WORKAREASIZE] } { set _WORKAREASIZE 0x8000 } +if { [info exists FIUNAME]} { + set _FIUNAME $FIUNAME +} else { + set _FIUNAME npcx.fiu +} + # Debug Adapter Target Settings swj_newdap $_CHIPNAME cpu -irlen 4 -expected-id $_CPUDAPID dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu @@ -48,4 +54,4 @@ cortex_m reset_config sysresetreq # flash configuration set _FLASHNAME $_CHIPNAME.flash -flash bank $_FLASHNAME npcx 0x64000000 0 0 0 $_TARGETNAME +flash bank $_FLASHNAME npcx 0x64000000 0 0 0 $_TARGETNAME $_FIUNAME