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ARM11: don't expose WDTR 

Don't expose the WDTR register through the register cache any
more.  If anyone wants Tcl scripts to be able to use DCC based
communication with app code in the target, this wouldn't do it.

Bugfix:  don't trust the Tcl-accessible version of DSCR to
flag whether WDTR needs to be restored when resuming.
This commit is contained in:
David Brownell 2009-12-02 22:57:07 -08:00
parent 7e18d96d03
commit 62dd15d78f
2 changed files with 11 additions and 14 deletions
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20
src/target/arm11.c
View File

@ -50,7 +50,6 @@ enum arm11_regtype
{ {
/* debug regs */ /* debug regs */
ARM11_REGISTER_DSCR, ARM11_REGISTER_DSCR,
ARM11_REGISTER_WDTR,
}; };
@ -67,13 +66,11 @@ static const struct arm11_reg_defs arm11_reg_defs[] =
{ {
/* Debug Registers */ /* Debug Registers */
{"dscr", 0, -1, ARM11_REGISTER_DSCR}, {"dscr", 0, -1, ARM11_REGISTER_DSCR},
{"wdtr", 0, -1, ARM11_REGISTER_WDTR},
}; };
enum arm11_regcache_ids enum arm11_regcache_ids
{ {
ARM11_RC_DSCR, ARM11_RC_DSCR,
ARM11_RC_WDTR,
ARM11_RC_MAX, ARM11_RC_MAX,
}; };
@ -171,8 +168,8 @@ static int arm11_debug_entry(struct arm11_common *arm11, uint32_t dscr)
R(DSCR) = dscr; R(DSCR) = dscr;
/* Save wDTR */ /* Save wDTR */
arm11->is_wdtr_saved = !!(dscr & ARM11_DSCR_WDTR_FULL);
if (dscr & ARM11_DSCR_WDTR_FULL) if (arm11->is_wdtr_saved)
{ {
arm11_add_debug_SCAN_N(arm11, 0x05, ARM11_TAP_DEFAULT); arm11_add_debug_SCAN_N(arm11, 0x05, ARM11_TAP_DEFAULT);
@ -180,17 +177,13 @@ static int arm11_debug_entry(struct arm11_common *arm11, uint32_t dscr)
struct scan_field chain5_fields[3]; struct scan_field chain5_fields[3];
arm11_setup_field(arm11, 32, NULL, &R(WDTR), chain5_fields + 0); arm11_setup_field(arm11, 32, NULL,
&arm11->saved_wdtr, chain5_fields + 0);
arm11_setup_field(arm11, 1, NULL, NULL, chain5_fields + 1); arm11_setup_field(arm11, 1, NULL, NULL, chain5_fields + 1);
arm11_setup_field(arm11, 1, NULL, NULL, chain5_fields + 2); arm11_setup_field(arm11, 1, NULL, NULL, chain5_fields + 2);
arm11_add_dr_scan_vc(ARRAY_SIZE(chain5_fields), chain5_fields, TAP_DRPAUSE); arm11_add_dr_scan_vc(ARRAY_SIZE(chain5_fields), chain5_fields, TAP_DRPAUSE);
} }
else
{
arm11->reg_list[ARM11_RC_WDTR].valid = 0;
}
/* DSCR: set ARM11_DSCR_EXECUTE_ARM_INSTRUCTION_ENABLE /* DSCR: set ARM11_DSCR_EXECUTE_ARM_INSTRUCTION_ENABLE
* *
@ -328,14 +321,15 @@ static int arm11_leave_debug_state(struct arm11_common *arm11, bool bpwp)
} }
/* maybe restore original wDTR */ /* maybe restore original wDTR */
if ((R(DSCR) & ARM11_DSCR_WDTR_FULL) || arm11->reg_list[ARM11_RC_WDTR].dirty) if (arm11->is_wdtr_saved)
{ {
retval = arm11_run_instr_data_prepare(arm11); retval = arm11_run_instr_data_prepare(arm11);
if (retval != ERROR_OK) if (retval != ERROR_OK)
return retval; return retval;
/* MCR p14,0,R0,c0,c5,0 */ /* MCR p14,0,R0,c0,c5,0 */
retval = arm11_run_instr_data_to_core_via_r0(arm11, 0xee000e15, R(WDTR)); retval = arm11_run_instr_data_to_core_via_r0(arm11,
0xee000e15, arm11->saved_wdtr);
if (retval != ERROR_OK) if (retval != ERROR_OK)
return retval; return retval;

5
src/target/arm11.h
View File

@ -26,7 +26,7 @@
#include "armv4_5.h" #include "armv4_5.h"
#include "arm_dpm.h" #include "arm_dpm.h"
#define ARM11_REGCACHE_COUNT 2 #define ARM11_REGCACHE_COUNT 1
#define ARM11_TAP_DEFAULT TAP_INVALID #define ARM11_TAP_DEFAULT TAP_INVALID
@ -63,8 +63,11 @@ struct arm11_common
Use only for debug message generation */ Use only for debug message generation */
uint32_t saved_rdtr; uint32_t saved_rdtr;
uint32_t saved_wdtr;
bool is_rdtr_saved; bool is_rdtr_saved;
bool is_wdtr_saved;
bool simulate_reset_on_next_halt; /**< Perform cleanups of the ARM state on next halt */ bool simulate_reset_on_next_halt; /**< Perform cleanups of the ARM state on next halt */
/** \name Shadow registers to save debug state */ /** \name Shadow registers to save debug state */