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target/xtensa: invalidate register cache on reset 

Resolves issues where registers are accessed when poll() logic is inactive or has not yet been triggered.

Signed-off-by: Ian Thompson <ianst@cadence.com>
Change-Id: If7a4d00938fb188b008325249627f7773c3484c5
Reviewed-on: https://review.openocd.org/c/openocd/+/7197
Tested-by: jenkins
Reviewed-by: Erhan Kurubas <erhan.kurubas@espressif.com>
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
This commit is contained in:
Ian Thompson 2022-09-15 14:14:15 -07:00 committed by Antonio Borneo
parent 27e7f5df5f
commit 61d0757acf
1 changed files with 5 additions and 2 deletions
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7
src/target/xtensa/xtensa.c
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@ -959,7 +959,6 @@ int xtensa_assert_reset(struct target *target)
struct xtensa *xtensa = target_to_xtensa(target); struct xtensa *xtensa = target_to_xtensa(target);
LOG_TARGET_DEBUG(target, "target_number=%i, begin", target->target_number); LOG_TARGET_DEBUG(target, "target_number=%i, begin", target->target_number);
target->state = TARGET_RESET;
xtensa_queue_pwr_reg_write(xtensa, xtensa_queue_pwr_reg_write(xtensa,
XDMREG_PWRCTL, XDMREG_PWRCTL,
PWRCTL_JTAGDEBUGUSE(xtensa) | PWRCTL_DEBUGWAKEUP(xtensa) | PWRCTL_MEMWAKEUP(xtensa) | PWRCTL_JTAGDEBUGUSE(xtensa) | PWRCTL_DEBUGWAKEUP(xtensa) | PWRCTL_MEMWAKEUP(xtensa) |
@ -968,8 +967,12 @@ int xtensa_assert_reset(struct target *target)
int res = xtensa_dm_queue_execute(&xtensa->dbg_mod); int res = xtensa_dm_queue_execute(&xtensa->dbg_mod);
if (res != ERROR_OK) if (res != ERROR_OK)
return res; return res;
/* registers are now invalid */
xtensa->reset_asserted = true; xtensa->reset_asserted = true;
return res; register_cache_invalidate(xtensa->core_cache);
target->state = TARGET_RESET;
return ERROR_OK;
} }
int xtensa_deassert_reset(struct target *target) int xtensa_deassert_reset(struct target *target)