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icepick.cfg: add cancel reset bit to TAP register writes 

The Agama family of devices (CC26x2/CC13x2) required an
additional bit to be set when adding the core's TAP into
the scan chain. The cancel reset bit 0x10000 tells the
ICEPick to take the bus out of reset so that the other
bits will take effect. This bit is a NOP on other devices
and ICEPicks, so the change shouldn't adversely affect
other devices.

Change-Id: I9245eef0936ea7eea28ae84ab5e8ce05fa63af40
Signed-off-by: Edward Fewell <efewell@ti.com>
Reviewed-on: http://openocd.zylin.com/4789
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
This commit is contained in:
Edward Fewell 2018-12-05 17:54:42 -06:00 committed by Tomas Vanek
parent 615a066629
commit 5fd1cb0e5b
1 changed files with 3 additions and 3 deletions
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6
tcl/target/icepick.cfg
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@ -90,18 +90,18 @@ proc icepick_c_tapenable {jrc port} {
# And never to enter RESET, which will disable the TAPs.
# first enable power and clock for TAP
icepick_c_router $jrc 1 0x2 $port 0x100048
icepick_c_router $jrc 1 0x2 $port 0x110048
# TRM states that the register should be read back here, skipped for now
# enable debug "default" mode
icepick_c_router $jrc 1 0x2 $port 0x102048
icepick_c_router $jrc 1 0x2 $port 0x112048
# TRM states that debug enable and debug mode should be read back and
# confirmed - skipped for now
# Finally select the tap
icepick_c_router $jrc 1 0x2 $port 0x102148
icepick_c_router $jrc 1 0x2 $port 0x112148
# Enter the bypass state
irscan $jrc [CONST IR_BYPASS] -endstate RUN/IDLE