interesting
/
riscv-openocd
mirror of https://github.com/riscv/riscv-openocd.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

Hide supervisor registers if there is no S mode. 

Also update encoding.h.

Change-Id: I275be7de0aa1af64d13ea191b9f4ff391cfb16dc
This commit is contained in:
Tim Newsome 2017-12-14 13:43:14 -08:00
parent f55d1a2030
commit 5f86f7208d
2 changed files with 32 additions and 28 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

40
src/target/riscv/encoding.h
View File

@ -113,19 +113,19 @@
#define PRV_H 2 #define PRV_H 2
#define PRV_M 3 #define PRV_M 3
#define SPTBR32_MODE 0x80000000 #define SATP32_MODE 0x80000000
#define SPTBR32_ASID 0x7FC00000 #define SATP32_ASID 0x7FC00000
#define SPTBR32_PPN 0x003FFFFF #define SATP32_PPN 0x003FFFFF
#define SPTBR64_MODE 0xF000000000000000 #define SATP64_MODE 0xF000000000000000
#define SPTBR64_ASID 0x0FFFF00000000000 #define SATP64_ASID 0x0FFFF00000000000
#define SPTBR64_PPN 0x00000FFFFFFFFFFF #define SATP64_PPN 0x00000FFFFFFFFFFF
#define SPTBR_MODE_OFF 0 #define SATP_MODE_OFF 0
#define SPTBR_MODE_SV32 1 #define SATP_MODE_SV32 1
#define SPTBR_MODE_SV39 8 #define SATP_MODE_SV39 8
#define SPTBR_MODE_SV48 9 #define SATP_MODE_SV48 9
#define SPTBR_MODE_SV57 10 #define SATP_MODE_SV57 10
#define SPTBR_MODE_SV64 11 #define SATP_MODE_SV64 11
#define PMP_R 0x01 #define PMP_R 0x01
#define PMP_W 0x02 #define PMP_W 0x02
@ -177,12 +177,12 @@
# define MSTATUS_SD MSTATUS64_SD # define MSTATUS_SD MSTATUS64_SD
# define SSTATUS_SD SSTATUS64_SD # define SSTATUS_SD SSTATUS64_SD
# define RISCV_PGLEVEL_BITS 9 # define RISCV_PGLEVEL_BITS 9
# define SPTBR_MODE SPTBR64_MODE # define SATP_MODE SATP64_MODE
#else #else
# define MSTATUS_SD MSTATUS32_SD # define MSTATUS_SD MSTATUS32_SD
# define SSTATUS_SD SSTATUS32_SD # define SSTATUS_SD SSTATUS32_SD
# define RISCV_PGLEVEL_BITS 10 # define RISCV_PGLEVEL_BITS 10
# define SPTBR_MODE SPTBR32_MODE # define SATP_MODE SATP32_MODE
#endif #endif
#define RISCV_PGSHIFT 12 #define RISCV_PGSHIFT 12
#define RISCV_PGSIZE (1 << RISCV_PGSHIFT) #define RISCV_PGSIZE (1 << RISCV_PGSHIFT)
@ -790,9 +790,9 @@
#define CSR_SSCRATCH 0x140 #define CSR_SSCRATCH 0x140
#define CSR_SEPC 0x141 #define CSR_SEPC 0x141
#define CSR_SCAUSE 0x142 #define CSR_SCAUSE 0x142
#define CSR_SBADADDR 0x143 #define CSR_STVAL 0x143
#define CSR_SIP 0x144 #define CSR_SIP 0x144
#define CSR_SPTBR 0x180 #define CSR_SATP 0x180
#define CSR_MSTATUS 0x300 #define CSR_MSTATUS 0x300
#define CSR_MISA 0x301 #define CSR_MISA 0x301
#define CSR_MEDELEG 0x302 #define CSR_MEDELEG 0x302
@ -803,7 +803,7 @@
#define CSR_MSCRATCH 0x340 #define CSR_MSCRATCH 0x340
#define CSR_MEPC 0x341 #define CSR_MEPC 0x341
#define CSR_MCAUSE 0x342 #define CSR_MCAUSE 0x342
#define CSR_MBADADDR 0x343 #define CSR_MTVAL 0x343
#define CSR_MIP 0x344 #define CSR_MIP 0x344
#define CSR_PMPCFG0 0x3a0 #define CSR_PMPCFG0 0x3a0
#define CSR_PMPCFG1 0x3a1 #define CSR_PMPCFG1 0x3a1
@ -1282,9 +1282,9 @@ DECLARE_CSR(scounteren, CSR_SCOUNTEREN)
DECLARE_CSR(sscratch, CSR_SSCRATCH) DECLARE_CSR(sscratch, CSR_SSCRATCH)
DECLARE_CSR(sepc, CSR_SEPC) DECLARE_CSR(sepc, CSR_SEPC)
DECLARE_CSR(scause, CSR_SCAUSE) DECLARE_CSR(scause, CSR_SCAUSE)
DECLARE_CSR(sbadaddr, CSR_SBADADDR) DECLARE_CSR(stval, CSR_STVAL)
DECLARE_CSR(sip, CSR_SIP) DECLARE_CSR(sip, CSR_SIP)
DECLARE_CSR(sptbr, CSR_SPTBR) DECLARE_CSR(satp, CSR_SATP)
DECLARE_CSR(mstatus, CSR_MSTATUS) DECLARE_CSR(mstatus, CSR_MSTATUS)
DECLARE_CSR(misa, CSR_MISA) DECLARE_CSR(misa, CSR_MISA)
DECLARE_CSR(medeleg, CSR_MEDELEG) DECLARE_CSR(medeleg, CSR_MEDELEG)
@ -1295,7 +1295,7 @@ DECLARE_CSR(mcounteren, CSR_MCOUNTEREN)
DECLARE_CSR(mscratch, CSR_MSCRATCH) DECLARE_CSR(mscratch, CSR_MSCRATCH)
DECLARE_CSR(mepc, CSR_MEPC) DECLARE_CSR(mepc, CSR_MEPC)
DECLARE_CSR(mcause, CSR_MCAUSE) DECLARE_CSR(mcause, CSR_MCAUSE)
DECLARE_CSR(mbadaddr, CSR_MBADADDR) DECLARE_CSR(mtval, CSR_MTVAL)
DECLARE_CSR(mip, CSR_MIP) DECLARE_CSR(mip, CSR_MIP)
DECLARE_CSR(pmpcfg0, CSR_PMPCFG0) DECLARE_CSR(pmpcfg0, CSR_PMPCFG0)
DECLARE_CSR(pmpcfg1, CSR_PMPCFG1) DECLARE_CSR(pmpcfg1, CSR_PMPCFG1)

20
src/target/riscv/riscv.c
View File

@ -1894,20 +1894,24 @@ int riscv_init_registers(struct target *target)
switch (csr_number) { switch (csr_number) {
case CSR_FFLAGS: case CSR_FFLAGS:
r->exist = riscv_supports_extension(target, 'F');
r->group = "float";
r->feature = &feature_fpu;
break;
case CSR_FRM: case CSR_FRM:
r->exist = riscv_supports_extension(target, 'F');
r->group = "float";
r->feature = &feature_fpu;
break;
case CSR_FCSR: case CSR_FCSR:
r->exist = riscv_supports_extension(target, 'F'); r->exist = riscv_supports_extension(target, 'F');
r->group = "float"; r->group = "float";
r->feature = &feature_fpu; r->feature = &feature_fpu;
break; break;
case CSR_SSTATUS:
case CSR_STVEC:
case CSR_SIP:
case CSR_SIE:
case CSR_SCOUNTEREN:
case CSR_SSCRATCH:
case CSR_SEPC:
case CSR_SCAUSE:
case CSR_STVAL:
case CSR_SATP:
r->exist = riscv_supports_extension(target, 'S');
break;
} }
} else if (number == GDB_REGNO_PRIV) { } else if (number == GDB_REGNO_PRIV) {
sprintf(reg_name, "priv"); sprintf(reg_name, "priv");