interesting
/
riscv-openocd
mirror of https://github.com/riscv/riscv-openocd.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

Halt target in riscv_examine(). 

Change-Id: I11ab915901f2e75f9b728d6cf72c6498e3950ded
This commit is contained in:
Tim Newsome 2017-02-10 11:31:14 -08:00
parent 075c0e80d1
commit 5e3d9803ab
2 changed files with 45 additions and 30 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

59
src/target/riscv/debug_defines.h
View File

@ -1,25 +1,25 @@
#define ACCESS_REGISTER None
#define ACCESS_REGISTER_PREHALT_OFFSET 23
#define ACCESS_REGISTER_PREHALT_LENGTH 1
#define ACCESS_REGISTER_PREHALT (0x1 << ACCESS_REGISTER_PREHALT_OFFSET)
#define ACCESS_REGISTER_POSTRESUME_OFFSET 22
#define ACCESS_REGISTER_POSTRESUME_LENGTH 1
#define ACCESS_REGISTER_POSTRESUME (0x1 << ACCESS_REGISTER_POSTRESUME_OFFSET)
#define ACCESS_REGISTER_SIZE_OFFSET 19
#define ACCESS_REGISTER_SIZE_LENGTH 3
#define ACCESS_REGISTER_SIZE (0x7 << ACCESS_REGISTER_SIZE_OFFSET)
#define ACCESS_REGISTER_PREEXEC_OFFSET 18
#define ACCESS_REGISTER_PREEXEC_LENGTH 1
#define ACCESS_REGISTER_PREEXEC (0x1 << ACCESS_REGISTER_PREEXEC_OFFSET)
#define ACCESS_REGISTER_POSTEXEC_OFFSET 17
#define ACCESS_REGISTER_POSTEXEC_LENGTH 1
#define ACCESS_REGISTER_POSTEXEC (0x1 << ACCESS_REGISTER_POSTEXEC_OFFSET)
#define ACCESS_REGISTER_WRITE_OFFSET 16
#define ACCESS_REGISTER_WRITE_LENGTH 1
#define ACCESS_REGISTER_WRITE (0x1 << ACCESS_REGISTER_WRITE_OFFSET)
#define ACCESS_REGISTER_REGNO_OFFSET 0
#define ACCESS_REGISTER_REGNO_LENGTH 16
#define ACCESS_REGISTER_REGNO (0xffff << ACCESS_REGISTER_REGNO_OFFSET)
#define AC_ACCESS_REGISTER None
#define AC_ACCESS_REGISTER_PREHALT_OFFSET 23
#define AC_ACCESS_REGISTER_PREHALT_LENGTH 1
#define AC_ACCESS_REGISTER_PREHALT (0x1 << AC_ACCESS_REGISTER_PREHALT_OFFSET)
#define AC_ACCESS_REGISTER_POSTRESUME_OFFSET 22
#define AC_ACCESS_REGISTER_POSTRESUME_LENGTH 1
#define AC_ACCESS_REGISTER_POSTRESUME (0x1 << AC_ACCESS_REGISTER_POSTRESUME_OFFSET)
#define AC_ACCESS_REGISTER_SIZE_OFFSET 19
#define AC_ACCESS_REGISTER_SIZE_LENGTH 3
#define AC_ACCESS_REGISTER_SIZE (0x7 << AC_ACCESS_REGISTER_SIZE_OFFSET)
#define AC_ACCESS_REGISTER_PREEXEC_OFFSET 18
#define AC_ACCESS_REGISTER_PREEXEC_LENGTH 1
#define AC_ACCESS_REGISTER_PREEXEC (0x1 << AC_ACCESS_REGISTER_PREEXEC_OFFSET)
#define AC_ACCESS_REGISTER_POSTEXEC_OFFSET 17
#define AC_ACCESS_REGISTER_POSTEXEC_LENGTH 1
#define AC_ACCESS_REGISTER_POSTEXEC (0x1 << AC_ACCESS_REGISTER_POSTEXEC_OFFSET)
#define AC_ACCESS_REGISTER_WRITE_OFFSET 16
#define AC_ACCESS_REGISTER_WRITE_LENGTH 1
#define AC_ACCESS_REGISTER_WRITE (0x1 << AC_ACCESS_REGISTER_WRITE_OFFSET)
#define AC_ACCESS_REGISTER_REGNO_OFFSET 0
#define AC_ACCESS_REGISTER_REGNO_LENGTH 16
#define AC_ACCESS_REGISTER_REGNO (0xffff << AC_ACCESS_REGISTER_REGNO_OFFSET)
#define CSR_DCSR 0x7b0
#define CSR_DCSR_XDEBUGVER_OFFSET 30
#define CSR_DCSR_XDEBUGVER_LENGTH 2
@ -62,18 +62,21 @@
#define CSR_PRIV_PRV_LENGTH 2
#define CSR_PRIV_PRV (0x3 << CSR_PRIV_PRV_OFFSET)
#define DMI_DMCONTROL 0x00
#define DMI_DMCONTROL_HALT_OFFSET 31
#define DMI_DMCONTROL_HALT_LENGTH 1
#define DMI_DMCONTROL_HALT (0x1 << DMI_DMCONTROL_HALT_OFFSET)
#define DMI_DMCONTROL_HALTREQ_OFFSET 31
#define DMI_DMCONTROL_HALTREQ_LENGTH 1
#define DMI_DMCONTROL_HALTREQ (0x1 << DMI_DMCONTROL_HALTREQ_OFFSET)
#define DMI_DMCONTROL_RESET_OFFSET 30
#define DMI_DMCONTROL_RESET_LENGTH 1
#define DMI_DMCONTROL_RESET (0x1 << DMI_DMCONTROL_RESET_OFFSET)
#define DMI_DMCONTROL_DMACTIVE_OFFSET 29
#define DMI_DMCONTROL_DMACTIVE_LENGTH 1
#define DMI_DMCONTROL_DMACTIVE (0x1 << DMI_DMCONTROL_DMACTIVE_OFFSET)
#define DMI_DMCONTROL_HARTID_OFFSET 16
#define DMI_DMCONTROL_HARTID_LENGTH 10
#define DMI_DMCONTROL_HARTID (0x3ff << DMI_DMCONTROL_HARTID_OFFSET)
#define DMI_DMCONTROL_HARTSTATUS_OFFSET 26
#define DMI_DMCONTROL_HARTSTATUS_LENGTH 2
#define DMI_DMCONTROL_HARTSTATUS (0x3 << DMI_DMCONTROL_HARTSTATUS_OFFSET)
#define DMI_DMCONTROL_HARTSEL_OFFSET 16
#define DMI_DMCONTROL_HARTSEL_LENGTH 10
#define DMI_DMCONTROL_HARTSEL (0x3ff << DMI_DMCONTROL_HARTSEL_OFFSET)
#define DMI_DMCONTROL_AUTHENTICATED_OFFSET 7
#define DMI_DMCONTROL_AUTHENTICATED_LENGTH 1
#define DMI_DMCONTROL_AUTHENTICATED (0x1 << DMI_DMCONTROL_AUTHENTICATED_OFFSET)

16
src/target/riscv/riscv-013.c
View File

@ -1803,10 +1803,11 @@ static int examine(struct target *target)
uint32_t dmcontrol = dbus_read(target, DMI_DMCONTROL);
LOG_DEBUG("dmcontrol: 0x%08x", dmcontrol);
LOG_DEBUG(" halt=%d", get_field(dmcontrol, DMI_DMCONTROL_HALT));
LOG_DEBUG(" haltreq=%d", get_field(dmcontrol, DMI_DMCONTROL_HALTREQ));
LOG_DEBUG(" reset=%d", get_field(dmcontrol, DMI_DMCONTROL_RESET));
LOG_DEBUG(" dmactive=%d", get_field(dmcontrol, DMI_DMCONTROL_DMACTIVE));
LOG_DEBUG(" hartid=0x%x", get_field(dmcontrol, DMI_DMCONTROL_HARTID));
LOG_DEBUG(" hartstatus=%d", get_field(dmcontrol, DMI_DMCONTROL_HARTSTATUS));
LOG_DEBUG(" hartsel=0x%x", get_field(dmcontrol, DMI_DMCONTROL_HARTSEL));
LOG_DEBUG(" authenticated=%d", get_field(dmcontrol, DMI_DMCONTROL_AUTHENTICATED));
LOG_DEBUG(" authbusy=%d", get_field(dmcontrol, DMI_DMCONTROL_AUTHBUSY));
LOG_DEBUG(" authtype=%d", get_field(dmcontrol, DMI_DMCONTROL_AUTHTYPE));
@ -1866,6 +1867,17 @@ static int examine(struct target *target)
value += 0x52534335;
}
dbus_write(target, DMI_DMCONTROL, DMI_DMCONTROL_HALTREQ | DMI_DMCONTROL_DMACTIVE);
for (unsigned i = 0; i < 256; i++) {
dmcontrol = dbus_read(target, DMI_DMCONTROL);
if (get_field(dmcontrol, DMI_DMCONTROL_HARTSTATUS) == 0)
break;
}
if (get_field(dmcontrol, DMI_DMCONTROL_HARTSTATUS) != 0) {
LOG_ERROR("hart didn't halt; dmcontrol=0x%x", dmcontrol);
return ERROR_FAIL;
}
// Figure out XLEN, and test writing all of Debug RAM while we're at it.
cache_set32(target, 0, xori(S1, ZERO, -1));
// 0xffffffff 0xffffffff:ffffffff 0xffffffff:ffffffff:ffffffff:ffffffff