target/arm_disassembler: add exception related disassembly
Add ERET/HVC/SMC disassebly decoding flow, below is testing result > mdw 0x5c 4 0x0000005c: e160006e e1400072 e1600073 ee110f10 > arm disassemble 0x5c 4 0x0000005c 0xe160006e ERET 0x00000060 0xe1400072 HVC 0x0002 0x00000064 0xe1600073 SMC 0x0003 0x00000068 0xee110f10 MRC p15, 0x00, r0, c1, c0, 0x00 > Change-Id: I1beccff885b5b37747edd0b2e9fb2297ce466a00 Signed-off-by: pierre Kuo <vichy.kuo@gmail.com> Reviewed-on: http://openocd.zylin.com/2548 Tested-by: jenkins Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
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@ -1403,17 +1403,46 @@ static int evaluate_misc_instr(uint32_t opcode,
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Rn);
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Rn);
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}
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}
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/* Software breakpoints */
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/* exception return */
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if ((opcode & 0x0000000f0) == 0x00000060) {
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if (((opcode & 0x600000) >> 21) == 3)
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instruction->type = ARM_ERET;
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snprintf(instruction->text,
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128,
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"0x%8.8" PRIx32 "\t0x%8.8" PRIx32 "\tERET",
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address,
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opcode);
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}
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/* exception generate instructions */
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if ((opcode & 0x0000000f0) == 0x00000070) {
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if ((opcode & 0x0000000f0) == 0x00000070) {
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uint32_t immediate;
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uint32_t immediate = 0;
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char *mnemonic = NULL;
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switch ((opcode & 0x600000) >> 21) {
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case 0x1:
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instruction->type = ARM_BKPT;
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instruction->type = ARM_BKPT;
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mnemonic = "BRKT";
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immediate = ((opcode & 0x000fff00) >> 4) | (opcode & 0xf);
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immediate = ((opcode & 0x000fff00) >> 4) | (opcode & 0xf);
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break;
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case 0x2:
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instruction->type = ARM_HVC;
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mnemonic = "HVC";
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immediate = ((opcode & 0x000fff00) >> 4) | (opcode & 0xf);
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break;
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case 0x3:
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instruction->type = ARM_SMC;
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mnemonic = "SMC";
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immediate = (opcode & 0xf);
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break;
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}
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snprintf(instruction->text,
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snprintf(instruction->text,
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128,
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128,
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"0x%8.8" PRIx32 "\t0x%8.8" PRIx32 "\tBKPT 0x%4.4" PRIx32 "",
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"0x%8.8" PRIx32 "\t0x%8.8" PRIx32 "\t%s 0x%4.4" PRIx32 "",
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address,
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address,
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opcode,
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opcode,
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mnemonic,
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immediate);
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immediate);
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}
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}
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@ -84,9 +84,14 @@ enum arm_instruction_type {
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/* Miscellaneous instructions */
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/* Miscellaneous instructions */
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ARM_CLZ,
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ARM_CLZ,
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/* Exception return instructions */
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ARM_ERET,
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/* Exception generating instructions */
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/* Exception generating instructions */
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ARM_BKPT,
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ARM_BKPT,
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ARM_SWI,
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ARM_SWI,
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ARM_HVC,
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ARM_SMC,
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/* Coprocessor instructions */
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/* Coprocessor instructions */
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ARM_CDP,
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ARM_CDP,
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