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target/arm_disassembler: add exception related disassembly 

Add ERET/HVC/SMC disassebly decoding flow, below is testing result

> mdw 0x5c 4
0x0000005c: e160006e e1400072 e1600073 ee110f10
> arm disassemble 0x5c 4
0x0000005c	0xe160006e	ERET
0x00000060	0xe1400072	HVC 0x0002
0x00000064	0xe1600073	SMC 0x0003
0x00000068	0xee110f10	MRC p15, 0x00, r0, c1, c0, 0x00
>

Change-Id: I1beccff885b5b37747edd0b2e9fb2297ce466a00
Signed-off-by: pierre Kuo <vichy.kuo@gmail.com>
Reviewed-on: http://openocd.zylin.com/2548
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
This commit is contained in:
pierre Kuo 2015-02-13 11:27:52 +08:00 committed by Paul Fertser
parent e00a56bede
commit 5e005f4129
2 changed files with 39 additions and 5 deletions
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39
src/target/arm_disassembler.c
View File

@ -1403,17 +1403,46 @@ static int evaluate_misc_instr(uint32_t opcode,
Rn);
}
/* Software breakpoints */
/* exception return */
if ((opcode & 0x0000000f0) == 0x00000060) {
if (((opcode & 0x600000) >> 21) == 3)
instruction->type = ARM_ERET;
snprintf(instruction->text,
128,
"0x%8.8" PRIx32 "\t0x%8.8" PRIx32 "\tERET",
address,
opcode);
}
/* exception generate instructions */
if ((opcode & 0x0000000f0) == 0x00000070) {
uint32_t immediate;
instruction->type = ARM_BKPT;
immediate = ((opcode & 0x000fff00) >> 4) | (opcode & 0xf);
uint32_t immediate = 0;
char *mnemonic = NULL;
switch ((opcode & 0x600000) >> 21) {
case 0x1:
instruction->type = ARM_BKPT;
mnemonic = "BRKT";
immediate = ((opcode & 0x000fff00) >> 4) | (opcode & 0xf);
break;
case 0x2:
instruction->type = ARM_HVC;
mnemonic = "HVC";
immediate = ((opcode & 0x000fff00) >> 4) | (opcode & 0xf);
break;
case 0x3:
instruction->type = ARM_SMC;
mnemonic = "SMC";
immediate = (opcode & 0xf);
break;
}
snprintf(instruction->text,
128,
"0x%8.8" PRIx32 "\t0x%8.8" PRIx32 "\tBKPT 0x%4.4" PRIx32 "",
"0x%8.8" PRIx32 "\t0x%8.8" PRIx32 "\t%s 0x%4.4" PRIx32 "",
address,
opcode,
mnemonic,
immediate);
}

5
src/target/arm_disassembler.h
View File

@ -84,9 +84,14 @@ enum arm_instruction_type {
/* Miscellaneous instructions */
ARM_CLZ,
/* Exception return instructions */
ARM_ERET,
/* Exception generating instructions */
ARM_BKPT,
ARM_SWI,
ARM_HVC,
ARM_SMC,
/* Coprocessor instructions */
ARM_CDP,