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hontor <hontor@126.com> - fix simulation step errors 

git-svn-id: svn://svn.berlios.de/openocd/trunk@1097 b42882b7-edfa-0310-969c-e2dbd0fdcd60
This commit is contained in:
oharboe 2008-10-23 12:55:10 +00:00
parent c3e213a6e1
commit 5df88ed3a1
1 changed files with 9 additions and 3 deletions
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12
src/target/arm_simulator.c
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@ -533,9 +533,12 @@ int arm_simulate_step(target_t *target, u32 *dry_run_pc)
load_address = Rn; load_address = Rn;
} }
if((retval = target_read_u32(target, load_address, &load_value)) != ERROR_OK) if((!dry_run_pc) || (instruction.info.load_store.Rd == 15))
{ {
return retval; if((retval = target_read_u32(target, load_address, &load_value)) != ERROR_OK)
{
return retval;
}
} }
if (dry_run_pc) if (dry_run_pc)
@ -599,7 +602,10 @@ int arm_simulate_step(target_t *target, u32 *dry_run_pc)
{ {
if (instruction.info.load_store_multiple.register_list & (1 << i)) if (instruction.info.load_store_multiple.register_list & (1 << i))
{ {
target_read_u32(target, Rn, &load_values[i]); if((!dry_run_pc) || (i == 15))
{
target_read_u32(target, Rn, &load_values[i]);
}
Rn += 4; Rn += 4;
} }
} }