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cortex_m: add armv8m special registers 

Change-Id: I1942f375a5f4282ad1fe4a2ff3b8f3cbc64d8f7f
Signed-off-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
Reviewed-on: http://openocd.zylin.com/6016
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
This commit is contained in:
Tarek BOCHKATI 2021-01-12 20:11:11 +01:00 committed by Tomas Vanek
parent aa952a1b77
commit 5d9de1c400
3 changed files with 91 additions and 13 deletions
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57
src/target/armv7m.c
View File

@ -125,6 +125,29 @@ static const struct {
{ ARMV7M_FAULTMASK, "faultmask", 1, REG_TYPE_INT8, "system", "org.gnu.gdb.arm.m-system" },
{ ARMV7M_CONTROL, "control", 3, REG_TYPE_INT8, "system", "org.gnu.gdb.arm.m-system" },
/* ARMv8-M specific registers */
{ ARMV8M_MSP_NS, "msp_ns", 32, REG_TYPE_DATA_PTR, "stack", "v8-m.sp" },
{ ARMV8M_PSP_NS, "psp_ns", 32, REG_TYPE_DATA_PTR, "stack", "v8-m.sp" },
{ ARMV8M_MSP_S, "msp_s", 32, REG_TYPE_DATA_PTR, "stack", "v8-m.sp" },
{ ARMV8M_PSP_S, "psp_s", 32, REG_TYPE_DATA_PTR, "stack", "v8-m.sp" },
{ ARMV8M_MSPLIM_S, "msplim_s", 32, REG_TYPE_DATA_PTR, "stack", "v8-m.sp" },
{ ARMV8M_PSPLIM_S, "psplim_s", 32, REG_TYPE_DATA_PTR, "stack", "v8-m.sp" },
{ ARMV8M_MSPLIM_NS, "msplim_ns", 32, REG_TYPE_DATA_PTR, "stack", "v8-m.sp" },
{ ARMV8M_PSPLIM_NS, "psplim_ns", 32, REG_TYPE_DATA_PTR, "stack", "v8-m.sp" },
{ ARMV8M_PMSK_BPRI_FLTMSK_CTRL_S, "pmsk_bpri_fltmsk_ctrl_s", 32, REG_TYPE_INT, NULL, NULL },
{ ARMV8M_PRIMASK_S, "primask_s", 1, REG_TYPE_INT8, "system", "org.gnu.gdb.arm.m-system" },
{ ARMV8M_BASEPRI_S, "basepri_s", 8, REG_TYPE_INT8, "system", "org.gnu.gdb.arm.m-system" },
{ ARMV8M_FAULTMASK_S, "faultmask_s", 1, REG_TYPE_INT8, "system", "org.gnu.gdb.arm.m-system" },
{ ARMV8M_CONTROL_S, "control_s", 3, REG_TYPE_INT8, "system", "org.gnu.gdb.arm.m-system" },
{ ARMV8M_PMSK_BPRI_FLTMSK_CTRL_NS, "pmsk_bpri_fltmsk_ctrl_ns", 32, REG_TYPE_INT, NULL, NULL },
{ ARMV8M_PRIMASK_NS, "primask_ns", 1, REG_TYPE_INT8, "system", "org.gnu.gdb.arm.m-system" },
{ ARMV8M_BASEPRI_NS, "basepri_ns", 8, REG_TYPE_INT8, "system", "org.gnu.gdb.arm.m-system" },
{ ARMV8M_FAULTMASK_NS, "faultmask_ns", 1, REG_TYPE_INT8, "system", "org.gnu.gdb.arm.m-system" },
{ ARMV8M_CONTROL_NS, "control_ns", 3, REG_TYPE_INT8, "system", "org.gnu.gdb.arm.m-system" },
/* FPU registers */
{ ARMV7M_D0, "d0", 64, REG_TYPE_IEEE_DOUBLE, "float", "org.gnu.gdb.arm.vfp" },
{ ARMV7M_D1, "d1", 64, REG_TYPE_IEEE_DOUBLE, "float", "org.gnu.gdb.arm.vfp" },
{ ARMV7M_D2, "d2", 64, REG_TYPE_IEEE_DOUBLE, "float", "org.gnu.gdb.arm.vfp" },
@ -243,6 +266,15 @@ static uint32_t armv7m_map_id_to_regsel(unsigned int arm_reg_id)
case ARMV7M_PMSK_BPRI_FLTMSK_CTRL:
return ARMV7M_REGSEL_PMSK_BPRI_FLTMSK_CTRL;
case ARMV8M_MSP_NS...ARMV8M_PSPLIM_NS:
return arm_reg_id - ARMV8M_MSP_NS + ARMV8M_REGSEL_MSP_NS;
case ARMV8M_PMSK_BPRI_FLTMSK_CTRL_S:
return ARMV8M_REGSEL_PMSK_BPRI_FLTMSK_CTRL_S;
case ARMV8M_PMSK_BPRI_FLTMSK_CTRL_NS:
return ARMV8M_REGSEL_PMSK_BPRI_FLTMSK_CTRL_NS;
case ARMV7M_FPSCR:
return ARMV7M_REGSEL_FPSCR;
@ -258,28 +290,26 @@ static uint32_t armv7m_map_id_to_regsel(unsigned int arm_reg_id)
static bool armv7m_map_reg_packing(unsigned int arm_reg_id,
unsigned int *reg32_id, uint32_t *offset)
{
switch (arm_reg_id) {
case ARMV7M_PRIMASK:
case ARMV7M_PRIMASK...ARMV7M_CONTROL:
*reg32_id = ARMV7M_PMSK_BPRI_FLTMSK_CTRL;
*offset = 0;
*offset = arm_reg_id - ARMV7M_PRIMASK;
return true;
case ARMV7M_BASEPRI:
*reg32_id = ARMV7M_PMSK_BPRI_FLTMSK_CTRL;
*offset = 1;
case ARMV8M_PRIMASK_S...ARMV8M_CONTROL_S:
*reg32_id = ARMV8M_PMSK_BPRI_FLTMSK_CTRL_S;
*offset = arm_reg_id - ARMV8M_PRIMASK_S;
return true;
case ARMV7M_FAULTMASK:
*reg32_id = ARMV7M_PMSK_BPRI_FLTMSK_CTRL;
*offset = 2;
return true;
case ARMV7M_CONTROL:
*reg32_id = ARMV7M_PMSK_BPRI_FLTMSK_CTRL;
*offset = 3;
case ARMV8M_PRIMASK_NS...ARMV8M_CONTROL_NS:
*reg32_id = ARMV8M_PMSK_BPRI_FLTMSK_CTRL_NS;
*offset = arm_reg_id - ARMV8M_PRIMASK_NS;
return true;
default:
return false;
}
}
static int armv7m_read_core_reg(struct target *target, struct reg *r,
@ -743,7 +773,8 @@ struct reg_cache *armv7m_build_reg_cache(struct target *target)
reg_list[i].value = arch_info[i].value;
reg_list[i].dirty = false;
reg_list[i].valid = false;
reg_list[i].hidden = i == ARMV7M_PMSK_BPRI_FLTMSK_CTRL;
reg_list[i].hidden = (i == ARMV7M_PMSK_BPRI_FLTMSK_CTRL ||
i == ARMV8M_PMSK_BPRI_FLTMSK_CTRL_NS || i == ARMV8M_PMSK_BPRI_FLTMSK_CTRL_S);
reg_list[i].type = &armv7m_reg_type;
reg_list[i].arch_info = &arch_info[i];

44
src/target/armv7m.h
View File

@ -60,7 +60,18 @@ enum {
ARMV7M_REGSEL_MSP,
ARMV7M_REGSEL_PSP,
ARMV8M_REGSEL_MSP_NS = 0x18,
ARMV8M_REGSEL_PSP_NS,
ARMV8M_REGSEL_MSP_S,
ARMV8M_REGSEL_PSP_S,
ARMV8M_REGSEL_MSPLIM_S,
ARMV8M_REGSEL_PSPLIM_S,
ARMV8M_REGSEL_MSPLIM_NS,
ARMV8M_REGSEL_PSPLIM_NS,
ARMV7M_REGSEL_PMSK_BPRI_FLTMSK_CTRL = 0x14,
ARMV8M_REGSEL_PMSK_BPRI_FLTMSK_CTRL_S = 0x22,
ARMV8M_REGSEL_PMSK_BPRI_FLTMSK_CTRL_NS = 0x23,
ARMV7M_REGSEL_FPSCR = 0x21,
/* 32bit Floating-point registers */
@ -129,6 +140,8 @@ enum {
/* following indices are arbitrary, do not match DCRSR.REGSEL selectors */
/* A block of container and contained registers follows:
* THE ORDER IS IMPORTANT to the end of the block ! */
/* working register for packing/unpacking special regs, hidden from gdb */
ARMV7M_PMSK_BPRI_FLTMSK_CTRL,
@ -142,6 +155,35 @@ enum {
ARMV7M_BASEPRI,
ARMV7M_FAULTMASK,
ARMV7M_CONTROL,
/* The end of block of container and contained registers */
/* ARMv8-M specific registers */
ARMV8M_MSP_NS,
ARMV8M_PSP_NS,
ARMV8M_MSP_S,
ARMV8M_PSP_S,
ARMV8M_MSPLIM_S,
ARMV8M_PSPLIM_S,
ARMV8M_MSPLIM_NS,
ARMV8M_PSPLIM_NS,
/* A block of container and contained registers follows:
* THE ORDER IS IMPORTANT to the end of the block ! */
ARMV8M_PMSK_BPRI_FLTMSK_CTRL_S,
ARMV8M_PRIMASK_S,
ARMV8M_BASEPRI_S,
ARMV8M_FAULTMASK_S,
ARMV8M_CONTROL_S,
/* The end of block of container and contained registers */
/* A block of container and contained registers follows:
* THE ORDER IS IMPORTANT to the end of the block ! */
ARMV8M_PMSK_BPRI_FLTMSK_CTRL_NS,
ARMV8M_PRIMASK_NS,
ARMV8M_BASEPRI_NS,
ARMV8M_FAULTMASK_NS,
ARMV8M_CONTROL_NS,
/* The end of block of container and contained registers */
/* 64bit Floating-point registers */
ARMV7M_D0,
@ -170,6 +212,8 @@ enum {
ARMV7M_CORE_LAST_REG = ARMV7M_xPSR,
ARMV7M_FPU_FIRST_REG = ARMV7M_D0,
ARMV7M_FPU_LAST_REG = ARMV7M_FPSCR,
ARMV8M_FIRST_REG = ARMV8M_MSP_NS,
ARMV8M_LAST_REG = ARMV8M_CONTROL_NS,
};
enum {

3
src/target/cortex_m.c
View File

@ -2069,6 +2069,9 @@ int cortex_m_examine(struct target *target)
for (size_t idx = ARMV7M_FPU_FIRST_REG; idx <= ARMV7M_FPU_LAST_REG; idx++)
armv7m->arm.core_cache->reg_list[idx].exist = false;
if (!armv7m->arm.is_armv8m)
for (size_t idx = ARMV8M_FIRST_REG; idx <= ARMV8M_LAST_REG; idx++)
armv7m->arm.core_cache->reg_list[idx].exist = false;
if (!armv7m->stlink) {
if (core == 3 || core == 4)