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Use new debug_defines.h (#703) 

* Update debug_defines from the spec.

Now it includes constants for field values, so use them instead of
duplicating that here.

Change-Id: I2fca6e89f25123c39d4bf483b8244e47aefb0f88

* Remove unused #defines

Change-Id: Id20351851c9ed2c3aa82ccf8c04b604bef11692a

* Use debug spec constants in a few more places

Change-Id: Ic4578729c89e3c6a26a72772e1635c5345bd6a52
Signed-off-by: Tim Newsome <tim@sifive.com>

* Use macros for trigger action types.

Which were added with the very latest debug_defines.h.

Change-Id: I47f73e11d2ec529c720f2e1df05f7b0d3026e43a
Signed-off-by: Tim Newsome <tim@sifive.com>
This commit is contained in:
Tim Newsome 2022-05-25 10:08:43 -07:00 committed by GitHub
parent 0fada02494
commit 5c34da1415
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3 changed files with 1487 additions and 1060 deletions
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2414
src/target/riscv/debug_defines.h
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File diff suppressed because it is too large Load Diff

17
src/target/riscv/riscv-013.c
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@ -82,13 +82,6 @@ void read_memory_sba_simple(struct target *target, target_addr_t addr,
#define get_field(reg, mask) (((reg) & (mask)) / ((mask) & ~((mask) << 1))) #define get_field(reg, mask) (((reg) & (mask)) / ((mask) & ~((mask) << 1)))
#define set_field(reg, mask, val) (((reg) & ~(mask)) | (((val) * ((mask) & ~((mask) << 1))) & (mask))) #define set_field(reg, mask, val) (((reg) & ~(mask)) | (((val) * ((mask) & ~((mask) << 1))) & (mask)))
#define CSR_DCSR_CAUSE_SWBP 1
#define CSR_DCSR_CAUSE_TRIGGER 2
#define CSR_DCSR_CAUSE_DEBUGINT 3
#define CSR_DCSR_CAUSE_STEP 4
#define CSR_DCSR_CAUSE_HALT 5
#define CSR_DCSR_CAUSE_GROUP 6
#define RISCV013_INFO(r) riscv013_info_t *r = get_info(target) #define RISCV013_INFO(r) riscv013_info_t *r = get_info(target)
/*** JTAG registers. ***/ /*** JTAG registers. ***/
@ -2569,9 +2562,9 @@ static int modify_privilege(struct target *target, uint64_t *mstatus, uint64_t *
*mstatus_old = *mstatus; *mstatus_old = *mstatus;
/* If we come from m-mode with mprv set, we want to keep mpp */ /* If we come from m-mode with mprv set, we want to keep mpp */
if (get_field(dcsr, DCSR_PRV) < 3) { if (get_field(dcsr, CSR_DCSR_PRV) < 3) {
/* MPP = PRIV */ /* MPP = PRIV */
*mstatus = set_field(*mstatus, MSTATUS_MPP, get_field(dcsr, DCSR_PRV)); *mstatus = set_field(*mstatus, MSTATUS_MPP, get_field(dcsr, CSR_DCSR_PRV));
/* MPRV = 1 */ /* MPRV = 1 */
*mstatus = set_field(*mstatus, MSTATUS_MPRV, 1); *mstatus = set_field(*mstatus, MSTATUS_MPRV, 1);
@ -4306,7 +4299,7 @@ static enum riscv_halt_reason riscv013_halt_reason(struct target *target)
LOG_DEBUG("dcsr.cause: 0x%" PRIx64, get_field(dcsr, CSR_DCSR_CAUSE)); LOG_DEBUG("dcsr.cause: 0x%" PRIx64, get_field(dcsr, CSR_DCSR_CAUSE));
switch (get_field(dcsr, CSR_DCSR_CAUSE)) { switch (get_field(dcsr, CSR_DCSR_CAUSE)) {
case CSR_DCSR_CAUSE_SWBP: case CSR_DCSR_CAUSE_EBREAK:
return RISCV_HALT_BREAKPOINT; return RISCV_HALT_BREAKPOINT;
case CSR_DCSR_CAUSE_TRIGGER: case CSR_DCSR_CAUSE_TRIGGER:
/* We could get here before triggers are enumerated if a trigger was /* We could get here before triggers are enumerated if a trigger was
@ -4317,8 +4310,8 @@ static enum riscv_halt_reason riscv013_halt_reason(struct target *target)
return RISCV_HALT_TRIGGER; return RISCV_HALT_TRIGGER;
case CSR_DCSR_CAUSE_STEP: case CSR_DCSR_CAUSE_STEP:
return RISCV_HALT_SINGLESTEP; return RISCV_HALT_SINGLESTEP;
case CSR_DCSR_CAUSE_DEBUGINT: case CSR_DCSR_CAUSE_HALTREQ:
case CSR_DCSR_CAUSE_HALT: case CSR_DCSR_CAUSE_RESETHALTREQ:
return RISCV_HALT_INTERRUPT; return RISCV_HALT_INTERRUPT;
case CSR_DCSR_CAUSE_GROUP: case CSR_DCSR_CAUSE_GROUP:
return RISCV_HALT_GROUP; return RISCV_HALT_GROUP;

116
src/target/riscv/riscv.c
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@ -28,88 +28,12 @@
#define get_field(reg, mask) (((reg) & (mask)) / ((mask) & ~((mask) << 1))) #define get_field(reg, mask) (((reg) & (mask)) / ((mask) & ~((mask) << 1)))
#define set_field(reg, mask, val) (((reg) & ~(mask)) | (((val) * ((mask) & ~((mask) << 1))) & (mask))) #define set_field(reg, mask, val) (((reg) & ~(mask)) | (((val) * ((mask) & ~((mask) << 1))) & (mask)))
/* Constants for legacy SiFive hardware breakpoints. */
#define CSR_BPCONTROL_X (1<<0)
#define CSR_BPCONTROL_W (1<<1)
#define CSR_BPCONTROL_R (1<<2)
#define CSR_BPCONTROL_U (1<<3)
#define CSR_BPCONTROL_S (1<<4)
#define CSR_BPCONTROL_H (1<<5)
#define CSR_BPCONTROL_M (1<<6)
#define CSR_BPCONTROL_BPMATCH (0xf<<7)
#define CSR_BPCONTROL_BPACTION (0xff<<11)
#define DEBUG_ROM_START 0x800
#define DEBUG_ROM_RESUME (DEBUG_ROM_START + 4)
#define DEBUG_ROM_EXCEPTION (DEBUG_ROM_START + 8)
#define DEBUG_RAM_START 0x400
#define SETHALTNOT 0x10c
/*** JTAG registers. ***/ /*** JTAG registers. ***/
#define DTMCONTROL 0x10 #define DTMCONTROL 0x10
#define DTMCONTROL_DBUS_RESET (1<<16)
#define DTMCONTROL_IDLE (7<<10)
#define DTMCONTROL_ADDRBITS (0xf<<4)
#define DTMCONTROL_VERSION (0xf) #define DTMCONTROL_VERSION (0xf)
#define DBUS 0x11 #define DBUS 0x11
#define DBUS_OP_START 0
#define DBUS_OP_SIZE 2
typedef enum {
DBUS_OP_NOP = 0,
DBUS_OP_READ = 1,
DBUS_OP_WRITE = 2
} dbus_op_t;
typedef enum {
DBUS_STATUS_SUCCESS = 0,
DBUS_STATUS_FAILED = 2,
DBUS_STATUS_BUSY = 3
} dbus_status_t;
#define DBUS_DATA_START 2
#define DBUS_DATA_SIZE 34
#define DBUS_ADDRESS_START 36
typedef enum slot {
SLOT0,
SLOT1,
SLOT_LAST,
} slot_t;
/*** Debug Bus registers. ***/
#define DMCONTROL 0x10
#define DMCONTROL_INTERRUPT (((uint64_t)1)<<33)
#define DMCONTROL_HALTNOT (((uint64_t)1)<<32)
#define DMCONTROL_BUSERROR (7<<19)
#define DMCONTROL_SERIAL (3<<16)
#define DMCONTROL_AUTOINCREMENT (1<<15)
#define DMCONTROL_ACCESS (7<<12)
#define DMCONTROL_HARTID (0x3ff<<2)
#define DMCONTROL_NDRESET (1<<1)
#define DMCONTROL_FULLRESET 1
#define DMINFO 0x11
#define DMINFO_ABUSSIZE (0x7fU<<25)
#define DMINFO_SERIALCOUNT (0xf<<21)
#define DMINFO_ACCESS128 (1<<20)
#define DMINFO_ACCESS64 (1<<19)
#define DMINFO_ACCESS32 (1<<18)
#define DMINFO_ACCESS16 (1<<17)
#define DMINFO_ACCESS8 (1<<16)
#define DMINFO_DRAMSIZE (0x3f<<10)
#define DMINFO_AUTHENTICATED (1<<5)
#define DMINFO_AUTHBUSY (1<<4)
#define DMINFO_AUTHTYPE (3<<2)
#define DMINFO_VERSION 3
/*** Info about the core being debugged. ***/
#define DBUS_ADDRESS_UNKNOWN 0xffff
#define MAX_HWBPS 16
#define DRAM_CACHE_SIZE 16
uint8_t ir_dtmcontrol[4] = {DTMCONTROL}; uint8_t ir_dtmcontrol[4] = {DTMCONTROL};
struct scan_field select_dtmcontrol = { struct scan_field select_dtmcontrol = {
@ -597,28 +521,28 @@ static int maybe_add_trigger_t2(struct target *target,
RISCV_INFO(r); RISCV_INFO(r);
/* tselect is already set */ /* tselect is already set */
if (tdata1 & (MCONTROL_EXECUTE | MCONTROL_STORE | MCONTROL_LOAD)) { if (tdata1 & (CSR_MCONTROL_EXECUTE | CSR_MCONTROL_STORE | CSR_MCONTROL_LOAD)) {
/* Trigger is already in use, presumably by user code. */ /* Trigger is already in use, presumably by user code. */
return ERROR_TARGET_RESOURCE_NOT_AVAILABLE; return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
} }
/* address/data match trigger */ /* address/data match trigger */
tdata1 |= MCONTROL_DMODE(riscv_xlen(target)); tdata1 |= CSR_MCONTROL_DMODE(riscv_xlen(target));
tdata1 = set_field(tdata1, MCONTROL_ACTION, tdata1 = set_field(tdata1, CSR_MCONTROL_ACTION,
MCONTROL_ACTION_DEBUG_MODE); CSR_MCONTROL_ACTION_DEBUG_MODE);
tdata1 = set_field(tdata1, MCONTROL_MATCH, MCONTROL_MATCH_EQUAL); tdata1 = set_field(tdata1, CSR_MCONTROL_MATCH, CSR_MCONTROL_MATCH_EQUAL);
tdata1 |= MCONTROL_M; tdata1 |= CSR_MCONTROL_M;
if (r->misa & (1 << ('S' - 'A'))) if (r->misa & (1 << ('S' - 'A')))
tdata1 |= MCONTROL_S; tdata1 |= CSR_MCONTROL_S;
if (r->misa & (1 << ('U' - 'A'))) if (r->misa & (1 << ('U' - 'A')))
tdata1 |= MCONTROL_U; tdata1 |= CSR_MCONTROL_U;
if (trigger->execute) if (trigger->execute)
tdata1 |= MCONTROL_EXECUTE; tdata1 |= CSR_MCONTROL_EXECUTE;
if (trigger->read) if (trigger->read)
tdata1 |= MCONTROL_LOAD; tdata1 |= CSR_MCONTROL_LOAD;
if (trigger->write) if (trigger->write)
tdata1 |= MCONTROL_STORE; tdata1 |= CSR_MCONTROL_STORE;
riscv_set_register(target, GDB_REGNO_TDATA1, tdata1); riscv_set_register(target, GDB_REGNO_TDATA1, tdata1);
@ -653,10 +577,10 @@ static int maybe_add_trigger_t6(struct target *target,
} }
/* address/data match trigger */ /* address/data match trigger */
tdata1 |= MCONTROL_DMODE(riscv_xlen(target)); tdata1 |= CSR_MCONTROL6_DMODE(riscv_xlen(target));
tdata1 = set_field(tdata1, CSR_MCONTROL6_ACTION, tdata1 = set_field(tdata1, CSR_MCONTROL6_ACTION,
MCONTROL_ACTION_DEBUG_MODE); CSR_MCONTROL6_ACTION_DEBUG_MODE);
tdata1 = set_field(tdata1, CSR_MCONTROL6_MATCH, MCONTROL_MATCH_EQUAL); tdata1 = set_field(tdata1, CSR_MCONTROL6_MATCH, CSR_MCONTROL6_MATCH_EQUAL);
tdata1 |= CSR_MCONTROL6_M; tdata1 |= CSR_MCONTROL6_M;
if (r->misa & (1 << ('H' - 'A'))) if (r->misa & (1 << ('H' - 'A')))
tdata1 |= CSR_MCONTROL6_VS | CSR_MCONTROL6_VU; tdata1 |= CSR_MCONTROL6_VS | CSR_MCONTROL6_VU;
@ -715,7 +639,7 @@ static int add_trigger(struct target *target, struct trigger *trigger)
int result = riscv_get_register(target, &tdata1, GDB_REGNO_TDATA1); int result = riscv_get_register(target, &tdata1, GDB_REGNO_TDATA1);
if (result != ERROR_OK) if (result != ERROR_OK)
return result; return result;
int type = get_field(tdata1, MCONTROL_TYPE(riscv_xlen(target))); int type = get_field(tdata1, CSR_TDATA1_TYPE(riscv_xlen(target)));
result = ERROR_OK; result = ERROR_OK;
switch (type) { switch (type) {
@ -1046,7 +970,7 @@ static int riscv_hit_trigger_hit_bit(struct target *target, uint32_t *unique_id)
uint64_t tdata1; uint64_t tdata1;
if (riscv_get_register(target, &tdata1, GDB_REGNO_TDATA1) != ERROR_OK) if (riscv_get_register(target, &tdata1, GDB_REGNO_TDATA1) != ERROR_OK)
return ERROR_FAIL; return ERROR_FAIL;
int type = get_field(tdata1, MCONTROL_TYPE(riscv_xlen(target))); int type = get_field(tdata1, CSR_TDATA1_TYPE(riscv_xlen(target)));
uint64_t hit_mask = 0; uint64_t hit_mask = 0;
switch (type) { switch (type) {
@ -1447,7 +1371,7 @@ static int disable_triggers(struct target *target, riscv_reg_t *state)
riscv_reg_t tdata1; riscv_reg_t tdata1;
if (riscv_get_register(target, &tdata1, GDB_REGNO_TDATA1) != ERROR_OK) if (riscv_get_register(target, &tdata1, GDB_REGNO_TDATA1) != ERROR_OK)
return ERROR_FAIL; return ERROR_FAIL;
if (tdata1 & MCONTROL_DMODE(riscv_xlen(target))) { if (tdata1 & CSR_TDATA1_DMODE(riscv_xlen(target))) {
state[t] = tdata1; state[t] = tdata1;
if (riscv_set_register(target, GDB_REGNO_TDATA1, 0) != ERROR_OK) if (riscv_set_register(target, GDB_REGNO_TDATA1, 0) != ERROR_OK)
return ERROR_FAIL; return ERROR_FAIL;
@ -4036,7 +3960,7 @@ int riscv_enumerate_triggers(struct target *target)
if (result != ERROR_OK) if (result != ERROR_OK)
return result; return result;
int type = get_field(tdata1, MCONTROL_TYPE(riscv_xlen(target))); int type = get_field(tdata1, CSR_TDATA1_TYPE(riscv_xlen(target)));
if (type == 0) if (type == 0)
break; break;
switch (type) { switch (type) {
@ -4046,11 +3970,11 @@ int riscv_enumerate_triggers(struct target *target)
riscv_set_register(target, GDB_REGNO_TDATA1, 0); riscv_set_register(target, GDB_REGNO_TDATA1, 0);
break; break;
case 2: case 2:
if (tdata1 & MCONTROL_DMODE(riscv_xlen(target))) if (tdata1 & CSR_MCONTROL_DMODE(riscv_xlen(target)))
riscv_set_register(target, GDB_REGNO_TDATA1, 0); riscv_set_register(target, GDB_REGNO_TDATA1, 0);
break; break;
case 6: case 6:
if (tdata1 & MCONTROL_DMODE(riscv_xlen(target))) if (tdata1 & CSR_MCONTROL6_DMODE(riscv_xlen(target)))
riscv_set_register(target, GDB_REGNO_TDATA1, 0); riscv_set_register(target, GDB_REGNO_TDATA1, 0);
break; break;
} }