xscale minor cleanup
Add a header comment referencing useful XScale specs. Make most data static, and the tables readonly. Scrub extra blank lines. Return fault codes from one routine. Remove a needless NOP methood. (BUGFIX) When we update R0, mark R0 as dirty/valid ... not R15/PC! Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
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David Brownell
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a0b1e05b53
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5aba621b55
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@ -35,6 +35,26 @@
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#include "time_support.h"
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#include "image.h"
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/*
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* Important XScale documents available as of October 2009 include:
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*
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* Intel XScale® Core Developer’s Manual, January 2004
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* Order Number: 273473-002
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* This has a chapter detailing debug facilities, and punts some
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* details to chip-specific microarchitecture documentats.
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*
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* Hot-Debug for Intel XScale® Core Debug White Paper, May 2005
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* Document Number: 273539-005
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* Less detailed than the developer's manual, but summarizes those
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* missing details (for most XScales) and gives LOTS of notes about
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* debugger/handler interaction issues. Presents a simpler reset
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* and load-handler sequence than the arch doc. (Note, OpenOCD
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* doesn't currently support "Hot-Debug" as defined there.)
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*
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* Chip-specific microarchitecture documents may also be useful.
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*/
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/* cli handling */
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int xscale_register_commands(struct command_context_s *cmd_ctx);
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@ -53,7 +73,6 @@ int xscale_restore_context(target_t *target);
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int xscale_assert_reset(target_t *target);
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int xscale_deassert_reset(target_t *target);
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int xscale_soft_reset_halt(struct target_s *target);
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int xscale_set_reg_u32(reg_t *reg, uint32_t value);
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@ -92,7 +111,7 @@ target_type_t xscale_target =
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.assert_reset = xscale_assert_reset,
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.deassert_reset = xscale_deassert_reset,
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.soft_reset_halt = xscale_soft_reset_halt,
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.soft_reset_halt = NULL,
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.get_gdb_reg_list = armv4_5_get_gdb_reg_list,
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@ -118,7 +137,7 @@ target_type_t xscale_target =
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.mmu = xscale_mmu
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};
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char* xscale_reg_list[] =
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static char *const xscale_reg_list[] =
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{
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"XSCALE_MAINID", /* 0 */
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"XSCALE_CACHETYPE",
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@ -144,7 +163,7 @@ char* xscale_reg_list[] =
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"XSCALE_TXRXCTRL",
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};
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xscale_reg_t xscale_reg_arch_info[] =
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static const xscale_reg_t xscale_reg_arch_info[] =
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{
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{XSCALE_MAINID, NULL},
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{XSCALE_CACHETYPE, NULL},
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@ -170,7 +189,7 @@ xscale_reg_t xscale_reg_arch_info[] =
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{-1, NULL}, /* TXRXCTRL implicit access via JTAG */
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};
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int xscale_reg_arch_type = -1;
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static int xscale_reg_arch_type = -1;
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int xscale_get_reg(reg_t *reg);
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int xscale_set_reg(reg_t *reg, uint8_t *buf);
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@ -258,7 +277,6 @@ int xscale_read_dcsr(target_t *target)
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fields[1].out_value = NULL;
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fields[1].in_value = xscale->reg_cache->reg_list[XSCALE_DCSR].value;
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fields[2].tap = xscale->jtag_info.tap;
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fields[2].num_bits = 1;
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fields[2].out_value = &field2;
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@ -298,7 +316,7 @@ int xscale_read_dcsr(target_t *target)
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static void xscale_getbuf(jtag_callback_data_t arg)
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{
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uint8_t *in = (uint8_t *)arg;
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uint8_t *in = (uint8_t *)arg;
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*((uint32_t *)in) = buf_get_u32(in, 0, 32);
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}
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@ -458,7 +476,6 @@ int xscale_read_tx(target_t *target, int consume)
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fields[1].out_value = NULL;
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fields[1].in_value = xscale->reg_cache->reg_list[XSCALE_TX].value;
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fields[2].tap = xscale->jtag_info.tap;
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fields[2].num_bits = 1;
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fields[2].out_value = NULL;
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@ -550,7 +567,6 @@ int xscale_write_rx(target_t *target)
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fields[1].out_value = xscale->reg_cache->reg_list[XSCALE_RX].value;
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fields[1].in_value = NULL;
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fields[2].tap = xscale->jtag_info.tap;
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fields[2].num_bits = 1;
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fields[2].out_value = &field2;
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@ -722,7 +738,6 @@ int xscale_write_dcsr(target_t *target, int hold_rst, int ext_dbg_brk)
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fields[1].out_value = xscale->reg_cache->reg_list[XSCALE_DCSR].value;
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fields[1].in_value = NULL;
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fields[2].tap = xscale->jtag_info.tap;
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fields[2].num_bits = 1;
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fields[2].out_value = &field2;
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@ -787,23 +802,13 @@ int xscale_load_ic(target_t *target, int mini, uint32_t va, uint32_t buffer[8])
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fields[0].tap = xscale->jtag_info.tap;
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fields[0].num_bits = 6;
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fields[0].out_value = &cmd;
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fields[0].in_value = NULL;
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fields[1].tap = xscale->jtag_info.tap;
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fields[1].num_bits = 27;
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fields[1].out_value = packet;
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fields[1].in_value = NULL;
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jtag_add_dr_scan(2, fields, jtag_get_end_state());
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fields[0].num_bits = 32;
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@ -823,9 +828,7 @@ int xscale_load_ic(target_t *target, int mini, uint32_t va, uint32_t buffer[8])
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jtag_add_dr_scan(2, fields, jtag_get_end_state());
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}
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jtag_execute_queue();
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return ERROR_OK;
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return jtag_execute_queue();
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}
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int xscale_invalidate_ic_line(target_t *target, uint32_t va)
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@ -849,23 +852,13 @@ int xscale_invalidate_ic_line(target_t *target, uint32_t va)
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fields[0].tap = xscale->jtag_info.tap;
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fields[0].num_bits = 6;
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fields[0].out_value = &cmd;
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fields[0].in_value = NULL;
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fields[1].tap = xscale->jtag_info.tap;
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fields[1].num_bits = 27;
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fields[1].out_value = packet;
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fields[1].in_value = NULL;
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jtag_add_dr_scan(2, fields, jtag_get_end_state());
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return ERROR_OK;
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@ -941,12 +934,12 @@ int xscale_arch_state(struct target_s *target)
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armv4_5_common_t *armv4_5 = target->arch_info;
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xscale_common_t *xscale = armv4_5->arch_info;
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char *state[] =
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static const char *state[] =
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{
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"disabled", "enabled"
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};
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char *arch_dbg_reason[] =
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static const char *arch_dbg_reason[] =
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{
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"", "\n(processor reset)", "\n(trace buffer full)"
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};
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@ -1040,8 +1033,8 @@ int xscale_debug_entry(target_t *target)
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/* move r0 from buffer to register cache */
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buf_set_u32(armv4_5->core_cache->reg_list[0].value, 0, 32, buffer[0]);
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armv4_5->core_cache->reg_list[15].dirty = 1;
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armv4_5->core_cache->reg_list[15].valid = 1;
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armv4_5->core_cache->reg_list[0].dirty = 1;
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armv4_5->core_cache->reg_list[0].valid = 1;
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LOG_DEBUG("r0: 0x%8.8" PRIx32 "", buffer[0]);
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/* move pc from buffer to register cache */
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@ -1148,7 +1141,7 @@ int xscale_debug_entry(target_t *target)
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xscale->arch_debug_reason = XSCALE_DBG_REASON_TB_FULL;
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pc -= 4;
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break;
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case 0x7: /* Reserved */
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case 0x7: /* Reserved (may flag Hot-Debug support) */
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default:
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LOG_ERROR("Method of Entry is 'Reserved'");
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exit(-1);
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@ -1748,11 +1741,6 @@ int xscale_deassert_reset(target_t *target)
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return ERROR_OK;
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}
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int xscale_soft_reset_halt(struct target_s *target)
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{
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return ERROR_OK;
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}
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int xscale_read_core_reg(struct target_s *target, int num, enum armv4_5_mode mode)
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{
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return ERROR_OK;
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