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cortex a8: add timeouts waiting for restart, prepare and halt 

It would previously sit in an infinite loop rather
than reporting an error.

Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
This commit is contained in:
Øyvind Harboe 2010-06-21 14:14:31 +02:00
parent 37cfbe4917
commit 59bf45be1f
1 changed files with 36 additions and 6 deletions
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42
src/target/cortex_a8.c
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@ -39,6 +39,7 @@
#include "target_request.h" #include "target_request.h"
#include "target_type.h" #include "target_type.h"
#include "arm_opcodes.h" #include "arm_opcodes.h"
#include <helper/time_support.h>
static int cortex_a8_poll(struct target *target); static int cortex_a8_poll(struct target *target);
static int cortex_a8_debug_entry(struct target *target); static int cortex_a8_debug_entry(struct target *target);
@ -364,13 +365,22 @@ static int cortex_a8_dpm_prepare(struct arm_dpm *dpm)
int retval; int retval;
/* set up invariant: INSTR_COMP is set after ever DPM operation */ /* set up invariant: INSTR_COMP is set after ever DPM operation */
do { long long then = timeval_ms();
for (;;)
{
retval = mem_ap_read_atomic_u32(swjdp, retval = mem_ap_read_atomic_u32(swjdp,
a8->armv7a_common.debug_base + CPUDBG_DSCR, a8->armv7a_common.debug_base + CPUDBG_DSCR,
&dscr); &dscr);
if (retval != ERROR_OK) if (retval != ERROR_OK)
return retval; return retval;
} while ((dscr & DSCR_INSTR_COMP) == 0); if ((dscr & DSCR_INSTR_COMP) != 0)
break;
if (timeval_ms() > then + 1000)
{
LOG_ERROR("Timeout waiting for dpm prepare");
return ERROR_FAIL;
}
}
/* this "should never happen" ... */ /* this "should never happen" ... */
if (dscr & DSCR_DTR_RX_FULL) { if (dscr & DSCR_DTR_RX_FULL) {
@ -668,12 +678,23 @@ static int cortex_a8_halt(struct target *target)
if (retval != ERROR_OK) if (retval != ERROR_OK)
goto out; goto out;
do { long long then = timeval_ms();
for (;;)
{
retval = mem_ap_read_atomic_u32(swjdp, retval = mem_ap_read_atomic_u32(swjdp,
armv7a->debug_base + CPUDBG_DSCR, &dscr); armv7a->debug_base + CPUDBG_DSCR, &dscr);
if (retval != ERROR_OK) if (retval != ERROR_OK)
goto out; goto out;
} while ((dscr & DSCR_CORE_HALTED) == 0); if ((dscr & DSCR_CORE_HALTED) != 0)
{
break;
}
if (timeval_ms() > then + 1000)
{
LOG_ERROR("Timeout waiting for halt");
return ERROR_FAIL;
}
}
target->debug_reason = DBG_REASON_DBGRQ; target->debug_reason = DBG_REASON_DBGRQ;
@ -776,12 +797,21 @@ static int cortex_a8_resume(struct target *target, int current,
if (retval != ERROR_OK) if (retval != ERROR_OK)
return retval; return retval;
do { long long then = timeval_ms();
for (;;)
{
retval = mem_ap_read_atomic_u32(swjdp, retval = mem_ap_read_atomic_u32(swjdp,
armv7a->debug_base + CPUDBG_DSCR, &dscr); armv7a->debug_base + CPUDBG_DSCR, &dscr);
if (retval != ERROR_OK) if (retval != ERROR_OK)
return retval; return retval;
} while ((dscr & DSCR_CORE_RESTARTED) == 0); if ((dscr & DSCR_CORE_RESTARTED) != 0)
break;
if (timeval_ms() > then + 1000)
{
LOG_ERROR("Timeout waiting for resume");
return ERROR_FAIL;
}
}
target->debug_reason = DBG_REASON_NOTHALTED; target->debug_reason = DBG_REASON_NOTHALTED;
target->state = TARGET_RUNNING; target->state = TARGET_RUNNING;