Michael Bruck:
- Added simulate_reset_on_next_halt that can be extended to do all sorts of cleanups for systems without proper reset. Right now it just writes 0 to the control register to disable caches. - Step skips over Wait for Interrupt instruction - fix for count - fix for printf format errors git-svn-id: svn://svn.berlios.de/openocd/trunk@439 b42882b7-edfa-0310-969c-e2dbd0fdcd60
This commit is contained in:
oharboe
parent
5c2b85dfec
commit
58cccae639
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@ -16,6 +16,7 @@
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* Free Software Foundation, Inc., *
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* 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
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***************************************************************************/
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#ifdef HAVE_CONFIG_H
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#include "config.h"
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#endif
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@ -47,8 +48,8 @@
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static void arm11_on_enter_debug_state(arm11_common_t * arm11);
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int arm11_config_memwrite_burst = 1;
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int arm11_config_memwrite_error_fatal = 1;
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bool arm11_config_memwrite_burst = true;
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bool arm11_config_memwrite_error_fatal = true;
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u32 arm11_vcr = 0;
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@ -404,16 +405,6 @@ static void arm11_on_enter_debug_state(arm11_common_t * arm11)
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arm11_write_DSCR(arm11, new_dscr);
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/* jtag_execute_queue(); */
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/*
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DEBUG("SAVE DSCR %08x", R(DSCR));
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if (R(DSCR) & ARM11_DSCR_WDTR_FULL)
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DEBUG("SAVE wDTR %08x", R(WDTR));
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*/
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/* From the spec:
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Before executing any instruction in debug state you have to drain the write buffer.
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@ -425,7 +416,7 @@ static void arm11_on_enter_debug_state(arm11_common_t * arm11)
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while (1)
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{
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/* MRC p14,0,R0,c5,c10,0 */
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/* arm11_run_instr_no_data1(arm11, /*0xee150e1a*/0xe320f000); */
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// arm11_run_instr_no_data1(arm11, /*0xee150e1a*/0xe320f000);
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/* mcr 15, 0, r0, cr7, cr10, {4} */
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arm11_run_instr_no_data1(arm11, 0xee070f9a);
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@ -502,7 +493,20 @@ static void arm11_on_enter_debug_state(arm11_common_t * arm11)
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arm11->reg_values[ARM11_RC_PC] -= 8;
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}
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/* DEBUG("SAVE PC %08x", R(PC)); */
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if (arm11->simulate_reset_on_next_halt)
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{
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arm11->simulate_reset_on_next_halt = false;
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DEBUG("Reset c1 Control Register");
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/* Write 0 (reset value) to Control register 0 to disable MMU/Cache etc. */
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/* MCR p15,0,R0,c1,c0,0 */
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arm11_run_instr_data_to_core_via_r0(arm11, 0xee010f10, 0);
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}
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arm11_run_instr_data_finish(arm11);
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@ -558,7 +562,7 @@ void arm11_leave_debug_state(arm11_common_t * arm11)
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/* MRC p14,0,r?,c0,c5,0 */
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arm11_run_instr_data_to_core1(arm11, 0xee100e15 | (i << 12), R(RX + i));
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/* DEBUG("RESTORE R%d %08x", i, R(RX + i)); */
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// DEBUG("RESTORE R%d %08x", i, R(RX + i));
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}}
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arm11_run_instr_data_finish(arm11);
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@ -719,6 +723,11 @@ int arm11_halt(struct target_s *target)
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DEBUG("target->state: %s", target_state_strings[target->state]);
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if (target->state == TARGET_UNKNOWN)
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{
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arm11->simulate_reset_on_next_halt = true;
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}
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if (target->state == TARGET_HALTED)
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{
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WARNING("target was already halted");
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@ -727,7 +736,7 @@ int arm11_halt(struct target_s *target)
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if (arm11->trst_active)
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{
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arm11->halt_requested = 1;
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arm11->halt_requested = true;
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return ERROR_OK;
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}
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@ -763,10 +772,8 @@ int arm11_resume(struct target_s *target, int current, u32 address, int handle_b
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{
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FNC_INFO;
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/*
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DEBUG("current %d address %08x handle_breakpoints %d debug_execution %d",
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current, address, handle_breakpoints, debug_execution);
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*/
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// DEBUG("current %d address %08x handle_breakpoints %d debug_execution %d",
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// current, address, handle_breakpoints, debug_execution);
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arm11_common_t * arm11 = target->arch_info;
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@ -820,7 +827,7 @@ int arm11_resume(struct target_s *target, int current, u32 address, int handle_b
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arm11_sc7_run(arm11, brp, asizeof(brp));
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DEBUG("Add BP %d at %08x", brp_num, bp->address);
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DEBUG("Add BP %zd at %08x", brp_num, bp->address);
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brp_num++;
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}
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@ -886,7 +893,7 @@ int arm11_step(struct target_s *target, int current, u32 address, int handle_bre
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arm11_read_memory_word(arm11, R(PC), &next_instruction);
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/** skip over BKPT */
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/* skip over BKPT */
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if ((next_instruction & 0xFFF00070) == 0xe1200070)
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{
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R(PC) += 4;
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@ -894,6 +901,15 @@ int arm11_step(struct target_s *target, int current, u32 address, int handle_bre
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arm11->reg_list[ARM11_RC_PC].dirty = 0;
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INFO("Skipping BKPT");
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}
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/* skip over Wait for interrupt / Standby */
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/* mcr 15, 0, r?, cr7, cr0, {4} */
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else if ((next_instruction & 0xFFFF0FFF) == 0xee070f90)
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{
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R(PC) += 4;
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arm11->reg_list[ARM11_RC_PC].valid = 1;
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arm11->reg_list[ARM11_RC_PC].dirty = 0;
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INFO("Skipping WFI");
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}
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/* ignore B to self */
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else if ((next_instruction & 0xFEFFFFFF) == 0xeafffffe)
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{
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@ -951,7 +967,7 @@ int arm11_step(struct target_s *target, int current, u32 address, int handle_bre
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arm11_on_enter_debug_state(arm11);
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}
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/* target->state = TARGET_HALTED; */
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// target->state = TARGET_HALTED;
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target->debug_reason = DBG_REASON_SINGLESTEP;
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target_call_event_callbacks(target, TARGET_EVENT_HALTED);
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@ -973,7 +989,7 @@ int arm11_assert_reset(struct target_s *target)
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jtag_add_sleep(5000);
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arm11_common_t * arm11 = target->arch_info;
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arm11->trst_active = 1;
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arm11->trst_active = true;
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#endif
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return ERROR_OK;
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@ -1076,7 +1092,8 @@ int arm11_read_memory(struct target_s *target, u32 address, u32 size, u32 count,
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/** \todo TODO: check if dirty is the right choice to force a rewrite on arm11_resume() */
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arm11->reg_list[ARM11_RC_R1].dirty = 1;
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while (count--)
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{size_t i;
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for (i = 0; i < count; i++)
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{
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/* ldrb r1, [r0], #1 */
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arm11_run_instr_no_data1(arm11, 0xe4d01001);
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@ -1086,7 +1103,8 @@ int arm11_read_memory(struct target_s *target, u32 address, u32 size, u32 count,
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arm11_run_instr_data_from_core(arm11, 0xEE001E15, &res, 1);
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*buffer++ = res;
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}
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}}
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break;
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case 2:
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@ -1095,7 +1113,8 @@ int arm11_read_memory(struct target_s *target, u32 address, u32 size, u32 count,
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u16 * buf16 = (u16*)buffer;
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while (count--)
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{size_t i;
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for (i = 0; i < count; i++)
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{
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/* ldrh r1, [r0], #2 */
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arm11_run_instr_no_data1(arm11, 0xe0d010b2);
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@ -1106,7 +1125,8 @@ int arm11_read_memory(struct target_s *target, u32 address, u32 size, u32 count,
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arm11_run_instr_data_from_core(arm11, 0xEE001E15, &res, 1);
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*buf16++ = res;
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}
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}}
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break;
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}
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@ -1138,17 +1158,21 @@ int arm11_write_memory(struct target_s *target, u32 address, u32 size, u32 count
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switch (size)
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{
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case 1:
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{
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arm11->reg_list[ARM11_RC_R1].dirty = 1;
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while (count--)
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{size_t i;
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for (i = 0; i < count; i++)
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{
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/* MRC p14,0,r1,c0,c5,0 */
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arm11_run_instr_data_to_core1(arm11, 0xee101e15, *buffer++);
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/* strb r1, [r0], #1 */
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arm11_run_instr_no_data1(arm11, 0xe4c01001);
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}
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}}
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break;
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}
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case 2:
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{
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@ -1156,14 +1180,16 @@ int arm11_write_memory(struct target_s *target, u32 address, u32 size, u32 count
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u16 * buf16 = (u16*)buffer;
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while (count--)
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{size_t i;
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for (i = 0; i < count; i++)
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{
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/* MRC p14,0,r1,c0,c5,0 */
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arm11_run_instr_data_to_core1(arm11, 0xee101e15, *buf16++);
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/* strh r1, [r0], #2 */
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arm11_run_instr_no_data1(arm11, 0xe0c010b2);
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}
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}}
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break;
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}
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@ -1450,7 +1476,7 @@ int arm11_set_reg(reg_t *reg, u8 *buf)
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target_t * target = ((arm11_reg_state_t *)reg->arch_info)->target;
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arm11_common_t *arm11 = target->arch_info;
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/* const arm11_reg_defs_t * arm11_reg_info = arm11_reg_defs + ((arm11_reg_state_t *)reg->arch_info)->def_index; */
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// const arm11_reg_defs_t * arm11_reg_info = arm11_reg_defs + ((arm11_reg_state_t *)reg->arch_info)->def_index;
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arm11->reg_values[((arm11_reg_state_t *)reg->arch_info)->def_index] = buf_get_u32(buf, 0, 32);
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reg->valid = 1;
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@ -1482,8 +1508,8 @@ void arm11_build_reg_cache(target_t *target)
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reg_cache_t **cache_p = register_get_last_cache_p(&target->reg_cache);
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(*cache_p) = cache;
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/* armv7m->core_cache = cache; */
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/* armv7m->process_context = cache; */
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// armv7m->core_cache = cache;
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// armv7m->process_context = cache;
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size_t i;
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@ -1492,7 +1518,7 @@ void arm11_build_reg_cache(target_t *target)
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ARM11_REGCACHE_COUNT != asizeof(arm11_reg_defs) ||
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ARM11_REGCACHE_COUNT != ARM11_RC_MAX)
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{
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ERROR("arm11->reg_values inconsistent (%d %d %d %d)", ARM11_REGCACHE_COUNT, asizeof(arm11->reg_values), asizeof(arm11_reg_defs), ARM11_RC_MAX);
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ERROR("arm11->reg_values inconsistent (%d %zd %zd %d)", ARM11_REGCACHE_COUNT, asizeof(arm11->reg_values), asizeof(arm11_reg_defs), ARM11_RC_MAX);
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exit(-1);
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}
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@ -1519,7 +1545,7 @@ void arm11_build_reg_cache(target_t *target)
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int arm11_handle_bool(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, int * var, char * name)
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int arm11_handle_bool(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, bool * var, char * name)
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{
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if (argc == 0)
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{
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@ -1537,7 +1563,7 @@ int arm11_handle_bool(struct command_context_s *cmd_ctx, char *cmd, char **args,
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case 'F':
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case 'd': /* disable */
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case 'D':
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*var = 0;
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*var = false;
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break;
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case '1': /* 1 */
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@ -1545,7 +1571,7 @@ int arm11_handle_bool(struct command_context_s *cmd_ctx, char *cmd, char **args,
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case 'T':
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case 'e': /* enable */
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case 'E':
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*var = 1;
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*var = true;
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break;
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}
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@ -16,6 +16,7 @@
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* Free Software Foundation, Inc., *
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* 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
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***************************************************************************/
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#ifndef ARM11_H
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#define ARM11_H
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@ -23,12 +24,13 @@
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#include "register.h"
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#include "embeddedice.h"
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#include "arm_jtag.h"
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#include <stdbool.h>
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#define asizeof(x) (sizeof(x) / sizeof((x)[0]))
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#define NEW(type, variable, items) \
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type * variable = malloc(sizeof(type) * items)
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type * variable = calloc(1, sizeof(type) * items)
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#define ARM11_REGCACHE_MODEREGS 0
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@ -77,8 +79,9 @@ typedef struct arm11_common_s
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u32 last_dscr; /**< Last retrieved DSCR value;
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* Can be used to detect changes */
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u8 trst_active;
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u8 halt_requested;
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bool trst_active;
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bool halt_requested;
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bool simulate_reset_on_next_halt;
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/** \name Shadow registers to save processor state */
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/*@{*/
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@ -254,7 +257,7 @@ int arm11_add_ir_scan_vc(int num_fields, scan_field_t *fields, enum tap_state st
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*/
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typedef struct arm11_sc7_action_s
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{
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int write; /**< Access mode: true for write, false for read. */
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bool write; /**< Access mode: true for write, false for read. */
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u8 address; /**< Register address mode. Use enum #arm11_sc7 */
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u32 value; /**< If write then set this to value to be written.
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In read mode this receives the read value when the
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@ -16,6 +16,7 @@
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* Free Software Foundation, Inc., *
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* 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
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***************************************************************************/
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#ifdef HAVE_CONFIG_H
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#include "config.h"
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#endif
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@ -28,13 +29,9 @@
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#include <string.h>
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#if 0
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#define JTAG_DEBUG(expr ...) \
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do { \
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log_printf (LOG_DEBUG, __FILE__, __LINE__, __FUNCTION__, expr); \
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} while(0)
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#define JTAG_DEBUG(expr ...) DEBUG(expr)
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#else
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#define JTAG_DEBUG(expr ...) \
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do {} while(0)
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#define JTAG_DEBUG(expr ...) do {} while(0)
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#endif
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enum tap_state arm11_move_pi_to_si_via_ci[] =
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@ -727,7 +724,7 @@ void arm11_sc7_clear_vbw(arm11_common_t * arm11)
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{size_t i;
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for (i = 0; i < asizeof(clear_bw); i++)
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{
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clear_bw[i].write = 1;
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clear_bw[i].write = true;
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clear_bw[i].value = 0;
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}}
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