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nds32: modify nds commands implementation 

Modify handle_nds32_memory_access_command: do not use DCache
setting to block user's setting.

Change-Id: I2d33f893773e2a2e3e2f26edde5938ef5902609d
Signed-off-by: Hsiangkai Wang <hsiangkai@gmail.com>
Reviewed-on: http://openocd.zylin.com/1579
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
This commit is contained in:
Hsiangkai Wang 2013-05-31 11:45:17 +08:00 committed by Spencer Oliver
parent 356f8a7412
commit 586575c9dc
1 changed files with 13 additions and 23 deletions
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36
src/target/nds32_cmd.c
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@ -69,6 +69,7 @@ COMMAND_HANDLER(handle_nds32_memory_access_command)
struct target *target = get_current_target(CMD_CTX); struct target *target = get_current_target(CMD_CTX);
struct nds32 *nds32 = target_to_nds32(target); struct nds32 *nds32 = target_to_nds32(target);
struct aice_port_s *aice = target_to_aice(target); struct aice_port_s *aice = target_to_aice(target);
struct nds32_memory *memory = &(nds32->memory);
if (!is_nds32(nds32)) { if (!is_nds32(nds32)) {
command_print(CMD_CTX, "current target isn't an Andes core"); command_print(CMD_CTX, "current target isn't an Andes core");
@ -76,33 +77,22 @@ COMMAND_HANDLER(handle_nds32_memory_access_command)
} }
if (CMD_ARGC > 0) { if (CMD_ARGC > 0) {
if (strcmp(CMD_ARGV[0], "bus") == 0)
memory->access_channel = NDS_MEMORY_ACC_BUS;
else if (strcmp(CMD_ARGV[0], "cpu") == 0)
memory->access_channel = NDS_MEMORY_ACC_CPU;
else /* default access channel is NDS_MEMORY_ACC_CPU */
memory->access_channel = NDS_MEMORY_ACC_CPU;
/* If target has no cache, always use BUS mode LOG_DEBUG("memory access channel is changed to %s",
* to access memory. */ NDS_MEMORY_ACCESS_NAME[memory->access_channel]);
struct nds32_memory *memory = &(nds32->memory);
if (memory->dcache.line_size == 0) { aice_memory_access(aice, memory->access_channel);
/* There is no Dcache. */ } else {
nds32->memory.access_channel = NDS_MEMORY_ACC_BUS; command_print(CMD_CTX, "memory access channel: %s",
} else if (memory->dcache.enable == false) { NDS_MEMORY_ACCESS_NAME[memory->access_channel]);
/* Dcache is disabled. */
nds32->memory.access_channel = NDS_MEMORY_ACC_BUS;
} else {
/* There is Dcache and Dcache is enabled. */
if (strcmp(CMD_ARGV[0], "bus") == 0)
nds32->memory.access_channel = NDS_MEMORY_ACC_BUS;
else if (strcmp(CMD_ARGV[0], "cpu") == 0)
nds32->memory.access_channel = NDS_MEMORY_ACC_CPU;
else /* default access channel is NDS_MEMORY_ACC_CPU */
nds32->memory.access_channel = NDS_MEMORY_ACC_CPU;
}
aice_memory_access(aice, nds32->memory.access_channel);
} }
command_print(CMD_CTX, "memory access channel: %s",
NDS_MEMORY_ACCESS_NAME[nds32->memory.access_channel]);
return ERROR_OK; return ERROR_OK;
} }