diff --git a/src/flash/nor/stm32l4x.c b/src/flash/nor/stm32l4x.c
index 379f1b4b3..9bdc2dbca 100644
--- a/src/flash/nor/stm32l4x.c
+++ b/src/flash/nor/stm32l4x.c
@@ -94,7 +94,7 @@
 /*
  * STM32G4xxx series for reference.
  *
- * RM0440 (STM32G43x/44x/47x/48x)
+ * RM0440 (STM32G43x/44x/47x/48x/49x/4Ax)
  * http://www.st.com/resource/en/reference_manual/dm00355726.pdf
  *
  * Cat. 2 devices have single bank only, page size is 2kByte.
@@ -104,6 +104,8 @@
  *
  * Bank mode is controlled by bit 22 (DBANK) in option bytes register.
  * Both banks are treated as a single OpenOCD bank.
+ *
+ * Cat. 4 devices have single bank only, page size is 2kByte.
  */
 
 /* Erase time can be as high as 25ms, 10x this and assume it's toast... */
@@ -184,6 +186,10 @@ static const struct stm32l4_rev stm32_471_revs[] = {
 	{ 0x1001, "Z" },
 };
 
+static const struct stm32l4_rev stm32_479_revs[] = {
+	{ 0x1000, "A" },
+};
+
 static const struct stm32l4_rev stm32_495_revs[] = {
 	{ 0x2001, "2.1" },
 };
@@ -307,6 +313,16 @@ static const struct stm32l4_part_info stm32l4_parts[] = {
 	  .flash_regs_base       = 0x40022000,
 	  .fsize_addr            = 0x1FFF75E0,
 	},
+	{
+	  .id                    = 0x479,
+	  .revs                  = stm32_479_revs,
+	  .num_revs              = ARRAY_SIZE(stm32_479_revs),
+	  .device_str            = "STM32G49/G4Axx",
+	  .max_flash_size_kb     = 512,
+	  .has_dual_bank         = false,
+	  .flash_regs_base       = 0x40022000,
+	  .fsize_addr            = 0x1FFF75E0,
+	},
 	{
 	  .id                    = 0x495,
 	  .revs                  = stm32_495_revs,
@@ -952,6 +968,7 @@ static int stm32l4_probe(struct flash_bank *bank)
 	case 0x464: /* STM32L41/L42xx */
 	case 0x466: /* STM32G03/G04xx */
 	case 0x468: /* STM32G43/G44xx */
+	case 0x479: /* STM32G49/G4Axx */
 	case 0x497: /* STM32WLEx */
 		/* single bank flash */
 		page_size_kb = 2;