tcl: stm32mp13x: add target and board config files

The stm32mp13x has one core Cortex-A7.

The board Discovery Kit includes an on-board STLink-V3 with SWD
connection.
The webpage of the board is not active yet.

Change-Id: I8836b26612a160ead79766955ebefaf3d21a329c
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/6675
Tested-by: jenkins
Reviewed-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>

tcl/board/stm32mp13x_dk.cfg

@@ -0,0 +1,10 @@
+# board MB1635x
+# http://www.st.com/en/evaluation-tools/stm32mp135f-dk.html
+
+source [find interface/stlink-dap.cfg]
+
+transport select dapdirect_swd
+
+source [find target/stm32mp13x.cfg]
+
+reset_config srst_only

tcl/target/stm32mp13x.cfg

@@ -0,0 +1,100 @@
+# STMicroelectronics STM32MP13x (Single Cortex-A7)
+# http://www.st.com/stm32mp1
+
+# HLA does not support custom CSW nor AP other than 0
+if { [using_hla] } {
+	echo "ERROR: HLA transport cannot work with this target."
+	echo "ERROR: To use STLink switch to DAP mode, as in \"board/stm32mp13x_dk.cfg\"."
+	shutdown
+}
+
+source [find target/swj-dp.tcl]
+
+if { [info exists CHIPNAME] } {
+	set _CHIPNAME $CHIPNAME
+} else {
+	set _CHIPNAME stm32mp13x
+}
+
+if { [info exists CPUTAPID] } {
+	set _CPUTAPID $CPUTAPID
+} else {
+	if { [using_jtag] } {
+		set _CPUTAPID 0x6ba00477
+	} else {
+		set _CPUTAPID 0x6ba02477
+	}
+}
+
+# Chip Level TAP Controller, only in jtag mode
+if { [info exists CLCTAPID] } {
+	set _CLCTAPID $CLCTAPID
+} else {
+	set _CLCTAPID 0x06501041
+}
+
+swj_newdap $_CHIPNAME tap -expected-id $_CPUTAPID -irlen 4
+if { [using_jtag] } {
+	jtag newtap $_CHIPNAME.clc tap -expected-id $_CLCTAPID -irlen 5
+}
+
+dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.tap -ignore-syspwrupack
+
+# NOTE: keep ap-num and dbgbase to speed-up examine after reset
+# NOTE: do not change the order of target create
+target create $_CHIPNAME.ap1 mem_ap -dap $_CHIPNAME.dap -ap-num 1
+target create $_CHIPNAME.axi mem_ap -dap $_CHIPNAME.dap -ap-num 0
+target create $_CHIPNAME.cpu cortex_a -dap $_CHIPNAME.dap -ap-num 1 -coreid 0 -dbgbase 0xE00D0000
+
+$_CHIPNAME.cpu cortex_a maskisr on
+$_CHIPNAME.cpu cortex_a dacrfixup on
+
+# interface does not work while srst is asserted
+# this is target specific, valid for every board
+# srst resets the debug unit, behavior equivalent to "srst_pulls_trst"
+reset_config srst_gates_jtag srst_pulls_trst
+
+adapter speed 5000
+adapter srst pulse_width 200
+# bootrom has an internal timeout of 1 second for detecting the boot flash.
+# wait at least 1 second to guarantee we are out of bootrom
+adapter srst delay 1100
+
+add_help_text axi_secure "Set secure mode for following AXI accesses"
+proc axi_secure {} {
+	$::_CHIPNAME.dap apsel 0
+	$::_CHIPNAME.dap apcsw 0x10006000
+}
+
+add_help_text axi_nsecure "Set non-secure mode for following AXI accesses"
+proc axi_nsecure {} {
+	$::_CHIPNAME.dap apsel 0
+	$::_CHIPNAME.dap apcsw 0x30006000
+}
+
+axi_secure
+
+proc dbgmcu_enable_debug {} {
+	# keep clock enabled in low-power
+	## catch {$::_CHIPNAME.ap1 mww 0xe0081004 0x00000004}
+	# freeze watchdog 1 and 2 on core halted
+	catch {$::_CHIPNAME.ap1 mww 0xe008102c 0x00000004}
+	catch {$::_CHIPNAME.ap1 mww 0xe008104c 0x00000008}
+}
+
+proc toggle_cpu_dbg_claim0 {} {
+	# toggle CPU0 DBG_CLAIM[0]
+	$::_CHIPNAME.ap1 mww 0xe00d0fa0 1
+	$::_CHIPNAME.ap1 mww 0xe00d0fa4 1
+}
+
+# FIXME: most of handlers below will be removed once reset framework get merged
+$_CHIPNAME.ap1 configure -event reset-deassert-pre {
+	adapter deassert srst deassert trst
+	catch {dap init}
+	catch {$::_CHIPNAME.dap apid 1}
+}
+$_CHIPNAME.cpu configure -event reset-deassert-pre  {$::_CHIPNAME.cpu arp_examine}
+$_CHIPNAME.cpu configure -event reset-deassert-post {toggle_cpu_dbg_claim0; dbgmcu_enable_debug}
+$_CHIPNAME.ap1 configure -event examine-start       {dap init}
+$_CHIPNAME.ap1 configure -event examine-end         {dbgmcu_enable_debug}