- add support for hardware breakpoints to mips32 target
git-svn-id: svn://svn.berlios.de/openocd/trunk@1173 b42882b7-edfa-0310-969c-e2dbd0fdcd60
This commit is contained in:
ntfreak
parent
76b3c6ece6
commit
5711203e20
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@ -325,6 +325,10 @@ int mips32_init_arch_info(target_t *target, mips32_common_t *mips32, int chain_p
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target->arch_info = mips32;
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mips32->common_magic = MIPS32_COMMON_MAGIC;
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/* has breakpoint/watchpint unit been scanned */
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mips32->bp_scanned = 0;
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mips32->data_break_list = NULL;
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mips32->ejtag_info.chain_pos = chain_pos;
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mips32->read_core_reg = mips32_read_core_reg;
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mips32->write_core_reg = mips32_write_core_reg;
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@ -342,3 +346,82 @@ int mips32_run_algorithm(struct target_s *target, int num_mem_params, mem_param_
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/*TODO*/
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return ERROR_OK;
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}
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int mips32_examine(struct target_s *target)
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{
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mips32_common_t *mips32 = target->arch_info;
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if (!target->type->examined)
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{
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target->type->examined = 1;
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/* we will configure later */
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mips32->bp_scanned = 0;
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mips32->num_inst_bpoints = 0;
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mips32->num_data_bpoints = 0;
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mips32->num_inst_bpoints_avail = 0;
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mips32->num_data_bpoints_avail = 0;
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}
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return ERROR_OK;
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}
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int mips32_configure_break_unit(struct target_s *target)
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{
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/* get pointers to arch-specific information */
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mips32_common_t *mips32 = target->arch_info;
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int retval;
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u32 dcr, bpinfo;
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int i;
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if (mips32->bp_scanned)
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return ERROR_OK;
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/* get info about breakpoint support */
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if ((retval = target_read_u32(target, EJTAG_DCR, &dcr)) != ERROR_OK)
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return retval;
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if (dcr & (1 << 16))
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{
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/* get number of inst breakpoints */
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if ((retval = target_read_u32(target, EJTAG_IBS, &bpinfo)) != ERROR_OK)
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return retval;
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mips32->num_inst_bpoints = (bpinfo >> 24) & 0x0F;
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mips32->num_inst_bpoints_avail = mips32->num_inst_bpoints;
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mips32->inst_break_list = calloc(mips32->num_inst_bpoints, sizeof(mips32_comparator_t));
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for (i = 0; i < mips32->num_inst_bpoints; i++)
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{
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mips32->inst_break_list[i].reg_address = EJTAG_IBA1 + (0x100 * i);
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}
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/* clear IBIS reg */
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if ((retval = target_write_u32(target, EJTAG_IBS, 0)) != ERROR_OK)
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return retval;
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}
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if (dcr & (1 << 17))
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{
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/* get number of data breakpoints */
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if ((retval = target_read_u32(target, EJTAG_DBS, &bpinfo)) != ERROR_OK)
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return retval;
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mips32->num_data_bpoints = (bpinfo >> 24) & 0x0F;
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mips32->num_data_bpoints_avail = mips32->num_data_bpoints;
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mips32->data_break_list = calloc(mips32->num_data_bpoints, sizeof(mips32_comparator_t));
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for (i = 0; i < mips32->num_data_bpoints; i++)
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{
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mips32->data_break_list[i].reg_address = EJTAG_DBA1 + (0x100 * i);
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}
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/* clear DBIS reg */
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if ((retval = target_write_u32(target, EJTAG_DBS, 0)) != ERROR_OK)
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return retval;
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}
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LOG_DEBUG("DCR 0x%x numinst %i numdata %i", dcr, mips32->num_inst_bpoints, mips32->num_data_bpoints);
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mips32->bp_scanned = 1;
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return ERROR_OK;
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}
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@ -37,6 +37,14 @@ enum
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MIPS32NUMCOREREGS
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};
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typedef struct mips32_comparator_s
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{
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int used;
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//int type;
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u32 bp_value;
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u32 reg_address;
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} mips32_comparator_t;
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typedef struct mips32_common_s
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{
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int common_magic;
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@ -45,6 +53,14 @@ typedef struct mips32_common_s
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mips_ejtag_t ejtag_info;
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u32 core_regs[MIPS32NUMCOREREGS];
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int bp_scanned;
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int num_inst_bpoints;
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int num_data_bpoints;
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int num_inst_bpoints_avail;
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int num_data_bpoints_avail;
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mips32_comparator_t *inst_break_list;
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mips32_comparator_t *data_break_list;
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/* register cache to processor synchronization */
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int (*read_core_reg)(struct target_s *target, int num);
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int (*write_core_reg)(struct target_s *target, int num);
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@ -108,6 +124,8 @@ extern int mips32_restore_context(target_t *target);
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extern int mips32_save_context(target_t *target);
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extern reg_cache_t *mips32_build_reg_cache(target_t *target);
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extern int mips32_run_algorithm(struct target_s *target, int num_mem_params, mem_param_t *mem_params, int num_reg_params, reg_param_t *reg_params, u32 entry_point, u32 exit_point, int timeout_ms, void *arch_info);
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extern int mips32_configure_break_unit(struct target_s *target);
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extern int mips32_examine(struct target_s *target);
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extern int mips32_register_commands(struct command_context_s *cmd_ctx);
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extern int mips32_invalidate_core_regs(target_t *target);
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@ -227,6 +227,7 @@ int mips_ejtag_exit_debug(mips_ejtag_t *ejtag_info, int enable_interrupts)
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int mips_ejtag_read_debug(mips_ejtag_t *ejtag_info, u32* debug_reg)
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{
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/* read ejtag ECR */
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u32 code[] = {
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MIPS32_MTC0(15,31,0), /* move $15 to COP0 DeSave */
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MIPS32_LUI(15,UPPER16(MIPS32_PRACC_STACK)), /* $15 = MIPS32_PRACC_STACK */
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@ -288,6 +289,7 @@ int mips_ejtag_init(mips_ejtag_t *ejtag_info)
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ejtag_info->impcode & (1<<14) ? " noDMA": " DMA",
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ejtag_info->impcode & (1<<0) ? " MIPS64": " MIPS32"
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);
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if((ejtag_info->impcode & (1<<14)) == 0)
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LOG_DEBUG("EJTAG: DMA Access Mode Support Enabled");
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@ -41,7 +41,7 @@
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#define EJTAG_INST_TCBDATA 0x12
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#define EJTAG_INST_BYPASS 0xFF
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/* debug control register bits */
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/* debug control register bits ECR */
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#define EJTAG_CTRL_TOF (1 << 1)
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#define EJTAG_CTRL_TIF (1 << 2)
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#define EJTAG_CTRL_BRKST (1 << 3)
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@ -91,6 +91,13 @@
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#define EJTAG_IMP_NODMA (1 << 14)
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#define EJTAG_IMP_MIPS16 (1 << 16)
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/* breakpoint support */
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#define EJTAG_DCR 0xFF300000
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#define EJTAG_IBS 0xFF301000
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#define EJTAG_IBA1 0xFF301100
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#define EJTAG_DBS 0xFF302000
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#define EJTAG_DBA1 0xFF302100
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typedef struct mips_ejtag_s
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{
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int chain_pos;
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@ -90,28 +90,56 @@ target_type_t mips_m4k_target =
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.quit = mips_m4k_quit
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};
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int mips_m4k_debug_entry(target_t *target)
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{
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u32 debug_reg;
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mips32_common_t *mips32 = target->arch_info;
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mips_ejtag_t *ejtag_info = &mips32->ejtag_info;
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/* read debug register */
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mips_ejtag_read_debug(ejtag_info, &debug_reg);
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int mips_m4k_examine_debug_reason(target_t *target)
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{
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int break_status;
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int retval;
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if ((target->debug_reason != DBG_REASON_DBGRQ)
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&& (target->debug_reason != DBG_REASON_SINGLESTEP))
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{
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// if (cortex_m3->nvic_dfsr & DFSR_BKPT)
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// {
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// target->debug_reason = DBG_REASON_BREAKPOINT;
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// if (cortex_m3->nvic_dfsr & DFSR_DWTTRAP)
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// target->debug_reason = DBG_REASON_WPTANDBKPT;
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// }
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// else if (cortex_m3->nvic_dfsr & DFSR_DWTTRAP)
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// target->debug_reason = DBG_REASON_WATCHPOINT;
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/* get info about inst breakpoint support */
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if ((retval = target_read_u32(target, EJTAG_IBS, &break_status)) != ERROR_OK)
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return retval;
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if (break_status & 0x1f)
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{
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/* we have halted on a breakpoint */
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if ((retval = target_write_u32(target, EJTAG_IBS, 0)) != ERROR_OK)
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return retval;
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target->debug_reason = DBG_REASON_BREAKPOINT;
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}
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/* get info about data breakpoint support */
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if ((retval = target_read_u32(target, 0xFF302000, &break_status)) != ERROR_OK)
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return retval;
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if (break_status & 0x1f)
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{
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/* we have halted on a breakpoint */
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if ((retval = target_write_u32(target, 0xFF302000, 0)) != ERROR_OK)
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return retval;
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target->debug_reason = DBG_REASON_WATCHPOINT;
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}
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}
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return ERROR_OK;
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}
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int mips_m4k_debug_entry(target_t *target)
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{
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mips32_common_t *mips32 = target->arch_info;
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mips_ejtag_t *ejtag_info = &mips32->ejtag_info;
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u32 debug_reg;
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/* read debug register */
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mips_ejtag_read_debug(ejtag_info, &debug_reg);
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/* make sure break uit configured */
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mips32_configure_break_unit(target);
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/* attempt to find halt reason */
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mips_m4k_examine_debug_reason(target);
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/* clear single step if active */
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if (debug_reg & EJTAG_DEBUG_DSS)
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{
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/* stopped due to single step - clear step bit */
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@ -312,6 +340,22 @@ int mips_m4k_soft_reset_halt(struct target_s *target)
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return ERROR_OK;
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}
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int mips_m4k_single_step_core(target_t *target)
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{
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mips32_common_t *mips32 = target->arch_info;
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mips_ejtag_t *ejtag_info = &mips32->ejtag_info;
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/* configure single step mode */
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mips_ejtag_config_step(ejtag_info, 1);
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/* exit debug mode */
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mips_ejtag_exit_debug(ejtag_info, 1);
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mips_m4k_debug_entry(target);
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return ERROR_OK;
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}
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int mips_m4k_resume(struct target_s *target, int current, u32 address, int handle_breakpoints, int debug_execution)
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{
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mips32_common_t *mips32 = target->arch_info;
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@ -352,13 +396,14 @@ int mips_m4k_resume(struct target_s *target, int current, u32 address, int handl
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{
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LOG_DEBUG("unset breakpoint at 0x%8.8x", breakpoint->address);
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mips_m4k_unset_breakpoint(target, breakpoint);
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//mips_m4k_single_step_core(target);
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mips_m4k_single_step_core(target);
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mips_m4k_set_breakpoint(target, breakpoint);
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}
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}
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/* exit debug mode - enable interrupts if required */
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mips_ejtag_exit_debug(ejtag_info, !debug_execution);
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target->debug_reason = DBG_REASON_NOTHALTED;
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/* registers are now invalid */
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mips32_invalidate_core_regs(target);
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@ -443,25 +488,114 @@ void mips_m4k_enable_breakpoints(struct target_s *target)
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int mips_m4k_set_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
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{
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/* TODO */
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mips32_common_t *mips32 = target->arch_info;
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mips32_comparator_t * comparator_list = mips32->inst_break_list;
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if (breakpoint->set)
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{
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LOG_WARNING("breakpoint already set");
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return ERROR_OK;
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}
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if (breakpoint->type == BKPT_HARD)
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{
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int bp_num = 0;
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while(comparator_list[bp_num].used && (bp_num < mips32->num_inst_bpoints))
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bp_num++;
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if (bp_num >= mips32->num_inst_bpoints)
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{
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LOG_DEBUG("ERROR Can not find free FP Comparator");
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LOG_WARNING("ERROR Can not find free FP Comparator");
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exit(-1);
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}
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breakpoint->set = bp_num + 1;
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comparator_list[bp_num].used = 1;
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comparator_list[bp_num].bp_value = breakpoint->address;
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target_write_u32(target, comparator_list[bp_num].reg_address, comparator_list[bp_num].bp_value);
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target_write_u32(target, comparator_list[bp_num].reg_address + 0x08, 0x00000000);
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target_write_u32(target, comparator_list[bp_num].reg_address + 0x18, 1);
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LOG_DEBUG("bp_num %i bp_value 0x%x", bp_num, comparator_list[bp_num].bp_value);
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}
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else if (breakpoint->type == BKPT_SOFT)
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{
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}
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return ERROR_OK;
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}
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int mips_m4k_unset_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
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{
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/* TODO */
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/* get pointers to arch-specific information */
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mips32_common_t *mips32 = target->arch_info;
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mips32_comparator_t * comparator_list = mips32->inst_break_list;
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if (!breakpoint->set)
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{
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LOG_WARNING("breakpoint not set");
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return ERROR_OK;
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}
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if (breakpoint->type == BKPT_HARD)
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{
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int bp_num = breakpoint->set - 1;
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if ((bp_num < 0) || (bp_num >= mips32->num_inst_bpoints))
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{
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LOG_DEBUG("Invalid FP Comparator number in breakpoint");
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return ERROR_OK;
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}
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comparator_list[bp_num].used = 0;
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comparator_list[bp_num].bp_value = 0;
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target_write_u32(target, comparator_list[bp_num].reg_address + 0x18, 0);
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}
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else
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{
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}
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breakpoint->set = 0;
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return ERROR_OK;
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}
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int mips_m4k_add_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
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{
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/* TODO */
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mips32_common_t *mips32 = target->arch_info;
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if (mips32->num_inst_bpoints_avail < 1)
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{
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LOG_INFO("no hardware breakpoint available");
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return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
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}
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/* default to hardware for now */
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breakpoint->type = BKPT_HARD;
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mips32->num_inst_bpoints_avail--;
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mips_m4k_set_breakpoint(target, breakpoint);
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return ERROR_OK;
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}
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int mips_m4k_remove_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
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{
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/* TODO */
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/* get pointers to arch-specific information */
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mips32_common_t *mips32 = target->arch_info;
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if (target->state != TARGET_HALTED)
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{
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LOG_WARNING("target not halted");
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return ERROR_TARGET_NOT_HALTED;
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}
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if (breakpoint->set)
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{
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mips_m4k_unset_breakpoint(target, breakpoint);
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}
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if (breakpoint->type == BKPT_HARD)
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mips32->num_inst_bpoints_avail++;
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return ERROR_OK;
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}
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@ -639,22 +773,26 @@ int mips_m4k_examine(struct target_s *target)
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mips_ejtag_t *ejtag_info = &mips32->ejtag_info;
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u32 idcode = 0;
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target->type->examined = 1;
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mips_ejtag_get_idcode(ejtag_info, &idcode, NULL);
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if (((idcode >> 1) & 0x7FF) == 0x29)
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if (!target->type->examined)
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{
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/* we are using a pic32mx so select ejtag port
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* as it is not selected by default */
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mips_ejtag_set_instr(ejtag_info, 0x05, NULL);
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LOG_DEBUG("PIC32MX Detected - using EJTAG Interface");
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mips_ejtag_get_idcode(ejtag_info, &idcode, NULL);
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if (((idcode >> 1) & 0x7FF) == 0x29)
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{
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/* we are using a pic32mx so select ejtag port
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* as it is not selected by default */
|
||||
mips_ejtag_set_instr(ejtag_info, 0x05, NULL);
|
||||
LOG_DEBUG("PIC32MX Detected - using EJTAG Interface");
|
||||
}
|
||||
}
|
||||
|
||||
/* init rest of ejtag interface */
|
||||
if ((retval = mips_ejtag_init(ejtag_info)) != ERROR_OK)
|
||||
return retval;
|
||||
|
||||
if ((retval = mips32_examine(target)) != ERROR_OK)
|
||||
return retval;
|
||||
|
||||
return ERROR_OK;
|
||||
}
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue