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Matt Hsu <matt@0xlab.org> cortex_a8_exec_opcode is writing the ARM instruction into 

the ITR register but it will only be executed when the DSCR[13]
bit is set. The documentation is a bit weird as it classifies
the DSCR as read-only but the pseudo code is writing to it as
well. This is working on a beagleboard.

git-svn-id: svn://svn.berlios.de/openocd/trunk@2634 b42882b7-edfa-0310-969c-e2dbd0fdcd60
This commit is contained in:
oharboe 2009-08-26 19:21:26 +00:00
parent f36d0083de
commit 56a04a3413
1 changed files with 9 additions and 1 deletions
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10
src/target/cortex_a8.c
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@ -546,7 +546,7 @@ int cortex_a8_resume(struct target_s *target, int current,
int cortex_a8_debug_entry(target_t *target) int cortex_a8_debug_entry(target_t *target)
{ {
int i; int i;
uint32_t regfile[16], pc, cpsr; uint32_t regfile[16], pc, cpsr, dscr;
int retval = ERROR_OK; int retval = ERROR_OK;
working_area_t *regfile_working_area = NULL; working_area_t *regfile_working_area = NULL;
@ -561,6 +561,14 @@ int cortex_a8_debug_entry(target_t *target)
LOG_DEBUG("dscr = 0x%08" PRIx32, cortex_a8->cpudbg_dscr); LOG_DEBUG("dscr = 0x%08" PRIx32, cortex_a8->cpudbg_dscr);
/* Enable the ITR execution once we are in debug mode */
mem_ap_read_atomic_u32(swjdp,
OMAP3530_DEBUG_BASE + CPUDBG_DSCR, &dscr);
dscr |= (1 << 13);
retval = mem_ap_write_atomic_u32(swjdp,
OMAP3530_DEBUG_BASE + CPUDBG_DSCR, dscr);
/* Examine debug reason */ /* Examine debug reason */
switch ((cortex_a8->cpudbg_dscr >> 2)&0xF) switch ((cortex_a8->cpudbg_dscr >> 2)&0xF)
{ {