interesting
/
riscv-openocd
mirror of https://github.com/riscv/riscv-openocd.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

Don't rely on havereset when deasserting reset. 

This removes the need for the supports_havereset config option as well.

Change-Id: Ic4391ce8c15d15e2ef662d170d483f336e8e8a5e
This commit is contained in:
Tim Newsome 2018-03-27 11:31:39 -07:00
parent c534a37fc3
commit 55e427b72b
3 changed files with 11 additions and 49 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

35
src/target/riscv/riscv-013.c
View File

@ -1343,8 +1343,7 @@ static int examine(struct target *target)
break;
r->hart_count = i + 1;
if (!riscv_havereset_not_supported &&
get_field(s, DMI_DMSTATUS_ANYHAVERESET))
if (get_field(s, DMI_DMSTATUS_ANYHAVERESET))
dmi_write(target, DMI_DMCONTROL,
set_field(DMI_DMCONTROL_DMACTIVE | DMI_DMCONTROL_ACKHAVERESET,
hartsel_mask(target), i));
@ -1577,27 +1576,8 @@ static int deassert_reset(struct target *target)
index = r->current_hartid;
}
if (!riscv_havereset_not_supported) {
LOG_DEBUG("Waiting for hart %d to be reset.", index);
do {
if (dmstatus_read(target, &dmstatus, true) != ERROR_OK)
return ERROR_FAIL;
if (time(NULL) - start > riscv_reset_timeout_sec) {
LOG_ERROR("Hart %d didn't reset in %ds; dmstatus=0x%x; "
"Increase the timeout with riscv set_reset_timeout_sec.",
r->current_hartid, riscv_reset_timeout_sec, dmstatus);
return ERROR_FAIL;
}
} while (get_field(dmstatus, DMI_DMSTATUS_ALLHAVERESET) == 0);
/* Ack reset. */
dmi_write(target, DMI_DMCONTROL,
set_field(control, hartsel_mask(target), index) |
DMI_DMCONTROL_ACKHAVERESET);
}
if (target->reset_halt) {
LOG_DEBUG("Waiting for hart %d to be halted.", index);
LOG_DEBUG("Waiting for hart %d to halt out of reset.", index);
do {
if (dmstatus_read(target, &dmstatus, true) != ERROR_OK)
return ERROR_FAIL;
@ -1612,7 +1592,7 @@ static int deassert_reset(struct target *target)
target->state = TARGET_HALTED;
} else {
LOG_DEBUG("Waiting for hart %d to be running.", index);
LOG_DEBUG("Waiting for hart %d to run out of reset.", index);
while (get_field(dmstatus, DMI_DMSTATUS_ALLRUNNING) == 0) {
if (dmstatus_read(target, &dmstatus, true) != ERROR_OK)
return ERROR_FAIL;
@ -1633,6 +1613,13 @@ static int deassert_reset(struct target *target)
target->state = TARGET_RUNNING;
}
if (get_field(dmstatus, DMI_DMSTATUS_ALLHAVERESET)) {
/* Ack reset. */
dmi_write(target, DMI_DMCONTROL,
set_field(control, hartsel_mask(target), index) |
DMI_DMCONTROL_ACKHAVERESET);
}
if (!target->rtos)
break;
}
@ -2566,7 +2553,7 @@ static bool riscv013_is_halted(struct target *target)
LOG_ERROR("Hart %d is unavailable.", riscv_current_hartid(target));
if (get_field(dmstatus, DMI_DMSTATUS_ANYNONEXISTENT))
LOG_ERROR("Hart %d doesn't exist.", riscv_current_hartid(target));
if (!riscv_havereset_not_supported && get_field(dmstatus, DMI_DMSTATUS_ANYHAVERESET)) {
if (get_field(dmstatus, DMI_DMSTATUS_ANYHAVERESET)) {
int hartid = riscv_current_hartid(target);
LOG_INFO("Hart %d unexpectedly reset!", hartid);
/* TODO: Can we make this more obvious to eg. a gdb user? */

22
src/target/riscv/riscv.c
View File

@ -188,8 +188,6 @@ int riscv_reset_timeout_sec = DEFAULT_RESET_TIMEOUT_SEC;
bool riscv_use_scratch_ram;
uint64_t riscv_scratch_ram_address;
bool riscv_havereset_not_supported;
/* In addition to the ones in the standard spec, we'll also expose additional
* CSRs in this list.
* The list is either NULL, or a series of ranges (inclusive), terminated with
@ -1249,17 +1247,6 @@ COMMAND_HANDLER(riscv_set_scratch_ram)
return ERROR_OK;
}
COMMAND_HANDLER(riscv_set_supports_havereset)
{
if (CMD_ARGC != 1) {
LOG_ERROR("Command takes exactly 1 parameter");
return ERROR_COMMAND_SYNTAX_ERROR;
}
COMMAND_PARSE_ON_OFF(CMD_ARGV[0], riscv_havereset_not_supported);
riscv_havereset_not_supported = !riscv_havereset_not_supported;
return ERROR_OK;
}
void parse_error(const char *string, char c, unsigned position)
{
char buf[position+2];
@ -1471,15 +1458,6 @@ static const struct command_registration riscv_exec_command_handlers[] = {
.usage = "riscv set_scratch_ram none|[address]",
.help = "Set address of 16 bytes of scratch RAM the debugger can use, or 'none'."
},
{
.name = "set_supports_havereset",
.handler = riscv_set_supports_havereset,
.mode = COMMAND_ANY,
.usage = "riscv set_supports_havereset on|off",
.help = "Set this off if one of the targets doesn't implement "
"allhavereset/anyhavereset in dmcontrol. When on, OpenOCD will wait "
"for these bits to go high during a reset."
},
{
.name = "expose_csrs",
.handler = riscv_set_expose_csrs,

3
src/target/riscv/riscv.h
View File

@ -128,9 +128,6 @@ extern int riscv_reset_timeout_sec;
extern bool riscv_use_scratch_ram;
extern uint64_t riscv_scratch_ram_address;
/* Negative so that the default value of 0 is what we want. */
extern bool riscv_havereset_not_supported;
/* Everything needs the RISC-V specific info structure, so here's a nice macro
* that provides that. */
static inline riscv_info_t *riscv_info(const struct target *target) __attribute__((unused));