interesting
/
riscv-openocd
mirror of https://github.com/riscv/riscv-openocd.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

Handle unavailability when deasserting reset

This commit is contained in:
cgsfv 2024-04-26 17:05:16 -07:00
parent 84ed43ec3a
commit 55ae2534b3
2 changed files with 9 additions and 5 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
src/target/riscv/riscv-013.c
View File

@ -2979,7 +2979,9 @@ static int deassert_reset(struct target *target)
info->dmi_busy_delay = orig_dmi_busy_delay; info->dmi_busy_delay = orig_dmi_busy_delay;
if (target->reset_halt) { if (get_field(dmstatus, DM_DMSTATUS_ALLUNAVAIL)) {
target->state = TARGET_UNAVAILABLE;
} else if (target->reset_halt) {
target->state = TARGET_HALTED; target->state = TARGET_HALTED;
target->debug_reason = DBG_REASON_DBGRQ; target->debug_reason = DBG_REASON_DBGRQ;
} else { } else {

6
src/target/startup.tcl
View File

@ -129,10 +129,12 @@ proc ocd_process_reset_inner { MODE } {
} else { } else {
$t invoke-event examine-end $t invoke-event examine-end
} }
}
# no need to wait for a target that is unavailable anyway
if { [$t curstate] == "unavailable" } { if { [$t curstate] == "unavailable" } {
continue continue
} }
}
# Wait up to 1 second for target to halt. Why 1sec? Cause # Wait up to 1 second for target to halt. Why 1sec? Cause
# the JTAG tap reset signal might be hooked to a slow # the JTAG tap reset signal might be hooked to a slow
@ -149,7 +151,7 @@ proc ocd_process_reset_inner { MODE } {
continue continue
} }
if { $s != "halted" } { if { $s != "halted" } {
return -code error [format "TARGET: %s - Not halted - Maybe unavailable %s" $t $s] return -code error [format "TARGET: %s - Not halted (%s)" $t $s]
} }
} }
} }