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Use LOG_TARGET_FOO() functions in more places. (#731) 

Change-Id: Id2266dbfb6209bf0676f28e7383a12705ce2a70e
Signed-off-by: Tim Newsome <tim@sifive.com>

Signed-off-by: Tim Newsome <tim@sifive.com>
This commit is contained in:
Tim Newsome 2022-09-29 15:09:49 -07:00 committed by GitHub
parent 23df83e830
commit 550a66e720
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GPG Key ID: 4AEE18F83AFDEB23
3 changed files with 34 additions and 43 deletions
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7
src/rtos/rtos.c
View File

@ -573,10 +573,9 @@ int rtos_get_gdb_reg_list(struct connection *connection)
struct rtos_reg *reg_list;
int num_regs;
LOG_DEBUG("RTOS: getting register list for thread 0x%" PRIx64
", target->rtos->current_thread=0x%" PRIx64 "\r\n",
current_threadid,
target->rtos->current_thread);
LOG_TARGET_DEBUG(target, "RTOS: getting register list for thread 0x%" PRIx64
", target->rtos->current_thread=0x%" PRIx64,
current_threadid, target->rtos->current_thread);
int retval = target->rtos->type->get_thread_reg_list(target->rtos,
current_threadid,

53
src/target/riscv/riscv-013.c
View File

@ -1282,8 +1282,7 @@ static bool has_sufficient_progbuf(struct target *target, unsigned size)
static int register_write_direct(struct target *target, unsigned number,
uint64_t value)
{
LOG_DEBUG("{%d} %s <- 0x%" PRIx64, riscv_current_hartid(target),
gdb_regno_name(number), value);
LOG_TARGET_DEBUG(target, "%s <- 0x%" PRIx64, gdb_regno_name(number), value);
int result = register_write_abstract(target, number, value,
register_size(target, number));
@ -1459,10 +1458,8 @@ static int register_read_direct(struct target *target, uint64_t *value, uint32_t
return ERROR_FAIL;
}
if (result == ERROR_OK) {
LOG_DEBUG("{%d} %s = 0x%" PRIx64, riscv_current_hartid(target),
gdb_regno_name(number), *value);
}
if (result == ERROR_OK)
LOG_TARGET_DEBUG(target, "%s = 0x%" PRIx64, gdb_regno_name(number), *value);
return result;
}
@ -1697,8 +1694,8 @@ static int examine(struct target *target)
bool halted = riscv_is_halted(target);
if (!halted) {
if (riscv013_halt_go(target) != ERROR_OK) {
LOG_ERROR("[%s] Fatal: Hart %d failed to halt during examine()",
target_name(target), r->current_hartid);
LOG_TARGET_ERROR(target, "Fatal: Hart %d failed to halt during examine()",
info->index);
return ERROR_FAIL;
}
}
@ -1717,16 +1714,16 @@ static int examine(struct target *target)
* need to take care of this manually. */
uint64_t s0, s1;
if (register_read_direct(target, &s0, GDB_REGNO_S0) != ERROR_OK) {
LOG_ERROR("Fatal: Failed to read s0 from hart %d.", r->current_hartid);
LOG_TARGET_ERROR(target, "Fatal: Failed to read s0.");
return ERROR_FAIL;
}
if (register_read_direct(target, &s1, GDB_REGNO_S1) != ERROR_OK) {
LOG_ERROR("Fatal: Failed to read s1 from hart %d.", r->current_hartid);
LOG_TARGET_ERROR(target, "Fatal: Failed to read s1.");
return ERROR_FAIL;
}
if (register_read_direct(target, &r->misa, GDB_REGNO_MISA)) {
LOG_ERROR("Fatal: Failed to read MISA from hart %d.", r->current_hartid);
LOG_TARGET_ERROR(target, "Fatal: Failed to read MISA.");
return ERROR_FAIL;
}
@ -1741,16 +1738,15 @@ static int examine(struct target *target)
/* Display this as early as possible to help people who are using
* really slow simulators. */
LOG_DEBUG(" hart %d: XLEN=%d, misa=0x%" PRIx64, r->current_hartid, r->xlen,
r->misa);
LOG_TARGET_DEBUG(target, " XLEN=%d, misa=0x%" PRIx64, r->xlen, r->misa);
/* Restore s0 and s1. */
if (register_write_direct(target, GDB_REGNO_S0, s0) != ERROR_OK) {
LOG_ERROR("Fatal: Failed to write s0 back to hart %d.", r->current_hartid);
LOG_TARGET_ERROR(target, "Fatal: Failed to write back s0.");
return ERROR_FAIL;
}
if (register_write_direct(target, GDB_REGNO_S1, s1) != ERROR_OK) {
LOG_ERROR("Fatal: Failed to write s1 back to hart %d.", r->current_hartid);
LOG_TARGET_ERROR(target, "Fatal: Failed to write back s1.");
return ERROR_FAIL;
}
@ -1772,10 +1768,9 @@ static int examine(struct target *target)
/* Some regression suites rely on seeing 'Examined RISC-V core' to know
* when they can connect with gdb/telnet.
* We will need to update those suites if we want to change that text. */
LOG_INFO("Examined RISC-V core; found %d harts",
LOG_TARGET_INFO(target, "Examined RISC-V core; found %d harts",
riscv_count_harts(target));
LOG_INFO(" hart %d: XLEN=%d, misa=0x%" PRIx64, r->current_hartid, r->xlen,
r->misa);
LOG_TARGET_INFO(target, " XLEN=%d, misa=0x%" PRIx64, r->xlen, r->misa);
return ERROR_OK;
}
@ -4057,7 +4052,7 @@ static int riscv013_get_register(struct target *target,
if (rid == GDB_REGNO_PC) {
/* TODO: move this into riscv.c. */
result = register_read_direct(target, value, GDB_REGNO_DPC);
LOG_DEBUG("[%d] read PC from DPC: 0x%" PRIx64, target->coreid, *value);
LOG_TARGET_DEBUG(target, "read PC from DPC: 0x%" PRIx64, *value);
} else if (rid == GDB_REGNO_PRIV) {
uint64_t dcsr;
/* TODO: move this into riscv.c. */
@ -4076,17 +4071,17 @@ static int riscv013_get_register(struct target *target,
static int riscv013_set_register(struct target *target, int rid, uint64_t value)
{
riscv013_select_current_hart(target);
LOG_DEBUG("[%d] writing 0x%" PRIx64 " to register %s",
target->coreid, value, gdb_regno_name(rid));
LOG_TARGET_DEBUG(target, "writing 0x%" PRIx64 " to register %s",
value, gdb_regno_name(rid));
if (rid <= GDB_REGNO_XPR31) {
return register_write_direct(target, rid, value);
} else if (rid == GDB_REGNO_PC) {
LOG_DEBUG("[%d] writing PC to DPC: 0x%" PRIx64, target->coreid, value);
LOG_TARGET_DEBUG(target, "writing PC to DPC: 0x%" PRIx64, value);
register_write_direct(target, GDB_REGNO_DPC, value);
uint64_t actual_value;
register_read_direct(target, &actual_value, GDB_REGNO_DPC);
LOG_DEBUG("[%d] actual DPC written: 0x%016" PRIx64, target->coreid, actual_value);
LOG_TARGET_DEBUG(target, " actual DPC written: 0x%016" PRIx64, actual_value);
if (value != actual_value) {
LOG_ERROR("Written PC (0x%" PRIx64 ") does not match read back "
"value (0x%" PRIx64 ")", value, actual_value);
@ -4207,8 +4202,8 @@ static int riscv013_halt_go(struct target *target)
if (dmi_read(target, &dmcontrol, DM_DMCONTROL) != ERROR_OK)
return ERROR_FAIL;
LOG_ERROR("[%s] Unable to halt hart %d. dmcontrol=0x%08x, dmstatus=0x%08x",
target_name(target), r->current_hartid, dmcontrol, dmstatus);
LOG_TARGET_ERROR(target, "Unable to halt. dmcontrol=0x%08x, dmstatus=0x%08x",
dmcontrol, dmstatus);
return ERROR_FAIL;
}
@ -4296,7 +4291,7 @@ static enum riscv_halt_reason riscv013_halt_reason(struct target *target)
if (result != ERROR_OK)
return RISCV_HALT_UNKNOWN;
LOG_DEBUG("dcsr.cause: 0x%" PRIx64, get_field(dcsr, CSR_DCSR_CAUSE));
LOG_TARGET_DEBUG(target, "dcsr.cause: 0x%" PRIx64, get_field(dcsr, CSR_DCSR_CAUSE));
switch (get_field(dcsr, CSR_DCSR_CAUSE)) {
case CSR_DCSR_CAUSE_EBREAK:
@ -4782,11 +4777,11 @@ static int riscv013_step_or_resume_current_hart(struct target *target,
bool step, bool use_hasel)
{
RISCV_INFO(r);
LOG_DEBUG("resuming hart %d (for step?=%d)", r->current_hartid, step);
if (!riscv_is_halted(target)) {
LOG_ERROR("Hart %d is not halted!", r->current_hartid);
return ERROR_FAIL;
}
LOG_TARGET_DEBUG(target, "resuming (for step?=%d)", step);
if (riscv_flush_registers(target) != ERROR_OK)
return ERROR_FAIL;
@ -4817,10 +4812,10 @@ static int riscv013_step_or_resume_current_hart(struct target *target,
dmi_write(target, DM_DMCONTROL, dmcontrol);
LOG_ERROR("unable to resume hart %d", r->current_hartid);
LOG_TARGET_ERROR(target, "unable to resume");
if (dmstatus_read(target, &dmstatus, true) != ERROR_OK)
return ERROR_FAIL;
LOG_ERROR(" dmstatus =0x%08x", dmstatus);
LOG_TARGET_ERROR(target, " dmstatus=0x%08x", dmstatus);
if (step) {
LOG_ERROR(" was stepping, halting");

17
src/target/riscv/riscv.c
View File

@ -796,7 +796,7 @@ int riscv_read_by_any_size(struct target *target, target_addr_t address, uint32_
int riscv_add_breakpoint(struct target *target, struct breakpoint *breakpoint)
{
LOG_DEBUG("[%d] @0x%" TARGET_PRIxADDR, target->coreid, breakpoint->address);
LOG_TARGET_DEBUG(target, "@0x%" TARGET_PRIxADDR, breakpoint->address);
assert(breakpoint);
if (breakpoint->type == BKPT_SOFT) {
/** @todo check RVC for size/alignment */
@ -1017,7 +1017,7 @@ int riscv_hit_watchpoint(struct target *target, struct watchpoint **hit_watchpoi
{
RISCV_INFO(r);
LOG_DEBUG("Current hartid = %d", riscv_current_hartid(target));
LOG_TARGET_DEBUG(target, "Hit Watchpoint");
/* If we identified which trigger caused the halt earlier, then just use
* that. */
@ -1297,7 +1297,7 @@ int riscv_halt(struct target *target)
return tt->halt(target);
}
LOG_DEBUG("[%d] halting all harts", target->coreid);
LOG_TARGET_DEBUG(target, "halting all harts");
int result = ERROR_OK;
if (target->smp) {
@ -1443,7 +1443,7 @@ static int resume_prep(struct target *target, int current,
target_addr_t address, int handle_breakpoints, int debug_execution)
{
RISCV_INFO(r);
LOG_DEBUG("[%d]", target->coreid);
LOG_TARGET_DEBUG(target, "target->state=%d", target->state);
if (!current)
riscv_set_register(target, GDB_REGNO_PC, address);
@ -1806,9 +1806,7 @@ static int riscv_get_gdb_reg_list_internal(struct target *target,
struct reg **reg_list[], int *reg_list_size,
enum target_register_class reg_class, bool read)
{
RISCV_INFO(r);
LOG_DEBUG("[%s] {%d} reg_class=%d, read=%d",
target_name(target), r->current_hartid, reg_class, read);
LOG_TARGET_DEBUG(target, "reg_class=%d, read=%d", reg_class, read);
if (!target->reg_cache) {
LOG_ERROR("Target not initialized. Return ERROR_FAIL.");
@ -2118,8 +2116,7 @@ static enum riscv_poll_hart riscv_poll_hart(struct target *target, int hartid)
if (riscv_set_current_hartid(target, hartid) != ERROR_OK)
return RPH_ERROR;
LOG_DEBUG("[%s] polling hart %d, target->state=%d", target_name(target),
hartid, target->state);
LOG_TARGET_DEBUG(target, "polling, target->state=%d", target->state);
/* If OpenOCD thinks we're running but this hart is halted then it's time
* to raise an event. */
@ -3544,7 +3541,7 @@ static int riscv_resume_go_all_harts(struct target *target)
{
RISCV_INFO(r);
LOG_DEBUG("[%s] resuming hart", target_name(target));
LOG_TARGET_DEBUG(target, "resuming hart, state=%d", target->state);
if (riscv_select_current_hart(target) != ERROR_OK)
return ERROR_FAIL;
if (riscv_is_halted(target)) {