- sw_bkpts fails if the target is not halted. The side effect is
that sw_bkpts also fails if the target is an unknown state(i.e. not examined yet). - feroceon embedded ICE registers are now set up after TRST has been deasserted(not tested, but it was broken as is anyway). git-svn-id: svn://svn.berlios.de/openocd/trunk@582 b42882b7-edfa-0310-969c-e2dbd0fdcd60
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@ -2434,6 +2434,12 @@ int handle_arm7_9_sw_bkpts_command(struct command_context_s *cmd_ctx, char *cmd,
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armv4_5_common_t *armv4_5;
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arm7_9_common_t *arm7_9;
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if (target->state != TARGET_HALTED)
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{
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LOG_ERROR("target not halted");
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return ERROR_TARGET_NOT_HALTED;
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}
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if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
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{
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command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target");
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@ -54,7 +54,7 @@
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#include <stdlib.h>
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#include <string.h>
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int feroceon_examine(struct command_context_s *cmd_ctx, struct target_s *target);
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int feroceon_target_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct target_s *target);
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int feroceon_bulk_write_memory(target_t *target, u32 address, u32 count, u8 *buffer);
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int feroceon_init_target(struct command_context_s *cmd_ctx, struct target_s *target);
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@ -94,7 +94,7 @@ target_type_t feroceon_target =
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.register_commands = arm926ejs_register_commands,
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.target_command = feroceon_target_command,
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.init_target = feroceon_init_target,
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.examine = arm9tdmi_examine,
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.examine = feroceon_examine,
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.quit = feroceon_quit
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};
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@ -568,32 +568,7 @@ int feroceon_bulk_write_memory(target_t *target, u32 address, u32 count, u8 *buf
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int feroceon_init_target(struct command_context_s *cmd_ctx, struct target_s *target)
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{
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armv4_5_common_t *armv4_5;
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arm7_9_common_t *arm7_9;
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arm9tdmi_init_target(cmd_ctx, target);
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armv4_5 = target->arch_info;
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arm7_9 = armv4_5->arch_info;
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/* the COMMS_CTRL bits are all contiguous */
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if (buf_get_u32(arm7_9->eice_cache->reg_list[EICE_COMMS_CTRL].value, 2, 4) != 6)
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LOG_ERROR("unexpected Feroceon EICE version signature");
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arm7_9->eice_cache->reg_list[EICE_DBG_CTRL].size = 6;
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arm7_9->eice_cache->reg_list[EICE_DBG_STAT].size = 5;
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arm7_9->has_monitor_mode = 1;
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/* vector catch reg is not initialized on reset */
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embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_VEC_CATCH], 0);
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/* clear monitor mode, enable comparators */
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embeddedice_read_reg(&arm7_9->eice_cache->reg_list[EICE_DBG_CTRL]);
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jtag_execute_queue();
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buf_set_u32(arm7_9->eice_cache->reg_list[EICE_DBG_CTRL].value, 4, 1, 0);
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buf_set_u32(arm7_9->eice_cache->reg_list[EICE_DBG_CTRL].value, 5, 1, 0);
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embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_DBG_CTRL]);
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return ERROR_OK;
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}
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@ -660,3 +635,39 @@ int feroceon_target_command(struct command_context_s *cmd_ctx, char *cmd, char *
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return ERROR_OK;
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}
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int feroceon_examine(struct command_context_s *cmd_ctx, struct target_s *target)
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{
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int retval;
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retval=feroceon_examine(cmd_ctx, target);
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if (retval!=ERROR_OK)
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return retval;
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armv4_5_common_t *armv4_5;
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arm7_9_common_t *arm7_9;
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armv4_5 = target->arch_info;
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arm7_9 = armv4_5->arch_info;
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/* the COMMS_CTRL bits are all contiguous */
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if (buf_get_u32(arm7_9->eice_cache->reg_list[EICE_COMMS_CTRL].value, 2, 4) != 6)
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LOG_ERROR("unexpected Feroceon EICE version signature");
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arm7_9->eice_cache->reg_list[EICE_DBG_CTRL].size = 6;
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arm7_9->eice_cache->reg_list[EICE_DBG_STAT].size = 5;
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arm7_9->has_monitor_mode = 1;
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/* vector catch reg is not initialized on reset */
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embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_VEC_CATCH], 0);
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/* clear monitor mode, enable comparators */
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embeddedice_read_reg(&arm7_9->eice_cache->reg_list[EICE_DBG_CTRL]);
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jtag_execute_queue();
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buf_set_u32(arm7_9->eice_cache->reg_list[EICE_DBG_CTRL].value, 4, 1, 0);
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buf_set_u32(arm7_9->eice_cache->reg_list[EICE_DBG_CTRL].value, 5, 1, 0);
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embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_DBG_CTRL]);
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return ERROR_OK;
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}
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