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target/arm_dpm: rename 'wp_pc' as 'wp_addr' 

The field 'wp_pc' was originally introduced in commit 55eeea7fce
("ARMv7a/Cortex-A8: report watchpoint trigger insn") in end 2009
to contain the address of the instruction which triggered a
watchpoint. Later on with commit 651b861d5d ("target/aarch64:
Add watchpoint support") it has been reused in to hold directly
the memory address that triggered a watchpoint.

Rename 'wp_pc' as 'wp_addr' and change its doxygen description.
While there, fix the format string to print the field.

Change-Id: I2e5ced1497e4a6fb6b38f91e881807512e8d8c47
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/6204
Tested-by: jenkins
Reviewed-by: Liming Sun <limings@nvidia.com>
This commit is contained in:
Antonio Borneo 2021-05-05 12:27:11 +02:00
parent 936cff887a
commit 510df38407
7 changed files with 14 additions and 13 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
src/target/aarch64.c
View File

@ -1856,7 +1856,7 @@ int aarch64_hit_watchpoint(struct target *target,
uint64_t exception_address; uint64_t exception_address;
struct watchpoint *wp; struct watchpoint *wp;
exception_address = armv8->dpm.wp_pc; exception_address = armv8->dpm.wp_addr;
if (exception_address == 0xFFFFFFFF) if (exception_address == 0xFFFFFFFF)
return ERROR_FAIL; return ERROR_FAIL;
@ -1867,12 +1867,12 @@ int aarch64_hit_watchpoint(struct target *target,
/* the EDWAR value needs to have 8 added to it so we add */ /* the EDWAR value needs to have 8 added to it so we add */
/* that check as well not sure if that is a core bug) */ /* that check as well not sure if that is a core bug) */
/**********************************************************/ /**********************************************************/
for (exception_address = armv8->dpm.wp_pc; exception_address <= (armv8->dpm.wp_pc + 8); for (exception_address = armv8->dpm.wp_addr; exception_address <= (armv8->dpm.wp_addr + 8);
exception_address += 8) { exception_address += 8) {
for (wp = target->watchpoints; wp; wp = wp->next) { for (wp = target->watchpoints; wp; wp = wp->next) {
if ((exception_address >= wp->address) && (exception_address < (wp->address + wp->length))) { if ((exception_address >= wp->address) && (exception_address < (wp->address + wp->length))) {
*hit_watchpoint = wp; *hit_watchpoint = wp;
if (exception_address != armv8->dpm.wp_pc) if (exception_address != armv8->dpm.wp_addr)
LOG_DEBUG("watchpoint hit required EDWAR to be increased by 8"); LOG_DEBUG("watchpoint hit required EDWAR to be increased by 8");
return ERROR_OK; return ERROR_OK;
} }

3
src/target/arm11.c
View File

@ -355,8 +355,7 @@ static int arm11_arch_state(struct target *target)
/* REVISIT also display ARM11-specific MMU and cache status ... */ /* REVISIT also display ARM11-specific MMU and cache status ... */
if (target->debug_reason == DBG_REASON_WATCHPOINT) if (target->debug_reason == DBG_REASON_WATCHPOINT)
LOG_USER("Watchpoint triggered at PC %#08x", LOG_USER("Watchpoint triggered at PC " TARGET_ADDR_FMT, arm11->dpm.wp_addr);
(unsigned) arm11->dpm.wp_pc);
return retval; return retval;
} }

2
src/target/arm_dpm.c
View File

@ -1010,7 +1010,7 @@ void arm_dpm_report_wfar(struct arm_dpm *dpm, uint32_t addr)
/* ?? */ /* ?? */
break; break;
} }
dpm->wp_pc = addr; dpm->wp_addr = addr;
} }
/*----------------------------------------------------------------------*/ /*----------------------------------------------------------------------*/

8
src/target/arm_dpm.h
View File

@ -137,8 +137,12 @@ struct arm_dpm {
struct dpm_bp *dbp; struct dpm_bp *dbp;
struct dpm_wp *dwp; struct dpm_wp *dwp;
/** Address of the instruction which triggered a watchpoint. */ /**
target_addr_t wp_pc; * Target dependent watchpoint address.
* Either the address of the instruction which triggered a watchpoint
* or the memory address whose access triggered a watchpoint.
*/
target_addr_t wp_addr;
/** Recent value of DSCR. */ /** Recent value of DSCR. */
uint32_t dscr; uint32_t dscr;

3
src/target/armv7a.c
View File

@ -571,8 +571,7 @@ int armv7a_arch_state(struct target *target)
if (arm->core_mode == ARM_MODE_ABT) if (arm->core_mode == ARM_MODE_ABT)
armv7a_show_fault_registers(target); armv7a_show_fault_registers(target);
if (target->debug_reason == DBG_REASON_WATCHPOINT) if (target->debug_reason == DBG_REASON_WATCHPOINT)
LOG_USER("Watchpoint triggered at PC %#08x", LOG_USER("Watchpoint triggered at PC " TARGET_ADDR_FMT, armv7a->dpm.wp_addr);
(unsigned) armv7a->dpm.wp_pc);
return ERROR_OK; return ERROR_OK;
} }

3
src/target/armv8.c
View File

@ -1169,8 +1169,7 @@ int armv8_arch_state(struct target *target)
armv8_show_fault_registers(target); armv8_show_fault_registers(target);
if (target->debug_reason == DBG_REASON_WATCHPOINT) if (target->debug_reason == DBG_REASON_WATCHPOINT)
LOG_USER("Watchpoint triggered at PC %#08x", LOG_USER("Watchpoint triggered at PC " TARGET_ADDR_FMT, armv8->dpm.wp_addr);
(unsigned) armv8->dpm.wp_pc);
return ERROR_OK; return ERROR_OK;
} }

2
src/target/armv8_dpm.c
View File

@ -1297,7 +1297,7 @@ void armv8_dpm_report_wfar(struct arm_dpm *dpm, uint64_t addr)
LOG_DEBUG("Unknown core_state"); LOG_DEBUG("Unknown core_state");
break; break;
} }
dpm->wp_pc = addr; dpm->wp_addr = addr;
} }
/* /*